Analog Devices ADSP-BF59x Blackfin Application guide

a
ADSP-BF59x Blackfin®Processor
Hardware Reference
Revision 1.0, May 2011
Part Number
82-100102-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106

Copyright Information
© 2011 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu-
ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
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Trademark and Service Mark Notice
The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, TigerSHARC,
and VisualDSP++ are registered trademarks of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.

ADSP-BF59x Blackfin Processor Hardware Reference i
CONTENTS
PREFACE
Purpose of This Manual ............................................................. xxxi
Intended Audience ....................................................................... xxxi
Manual Contents ........................................................................ xxxii
What’s New in This Manual ....................................................... xxxiv
Technical or Customer Support .................................................. xxxiv
Registration for MyAnalog.com ............................................. xxxv
EngineerZone ........................................................................ xxxv
Social Networking Web Sites ................................................ xxxvi
Supported Processors .................................................................. xxxvi
Product Information ................................................................. xxxvii
Analog Devices Web Site ..................................................... xxxvii
VisualDSP++ Online Documentation ................................ xxxviii
Technical Library CD ......................................................... xxxviii
Notation Conventions ................................................................ xxxix
INTRODUCTION
General Description of Processor ................................................... 1-1
Portable Low-Power Architecture ............................................. 1-2

Contents
ii ADSP-BF59x Blackfin Processor Hardware Reference
Peripherals .................................................................................... 1-3
Memory Architecture .................................................................... 1-4
Internal Memory ..................................................................... 1-5
I/O Memory Space .................................................................. 1-5
DMA Support .............................................................................. 1-6
General-Purpose I/O (GPIO) ........................................................ 1-7
Two-Wire Interface ....................................................................... 1-8
Parallel Peripheral Interface ........................................................... 1-9
SPORT Controllers .................................................................... 1-11
Serial Peripheral Interface (SPI) Ports .......................................... 1-13
Timers ....................................................................................... 1-13
UART Port ................................................................................. 1-14
Watchdog Timer ......................................................................... 1-15
Clock Signals .............................................................................. 1-16
Dynamic Power Management ..................................................... 1-16
Full-On Mode (Maximum Performance) ................................ 1-17
Active Mode (Moderate Power Savings) ................................. 1-17
Sleep Mode (High Power Savings) ......................................... 1-17
Deep Sleep Mode (Maximum Power Savings) ........................ 1-18
Hibernate State .................................................................... 1-18
Instruction Set Description ......................................................... 1-18
Development Tools ..................................................................... 1-19

ADSP-BF59x Blackfin Processor Hardware Reference iii
Contents
MEMORY
Memory Architecture .................................................................... 2-1
L1 Instruction SRAM ................................................................... 2-2
L1 Instruction ROM ..................................................................... 2-3
L1 Data SRAM ............................................................................. 2-3
Boot ROM ................................................................................... 2-4
External Memory .......................................................................... 2-4
Processor-Specific MMRs .............................................................. 2-4
DTEST_COMMAND Register ............................................... 2-5
ITEST_COMMAND Register ................................................. 2-6
DMEM_CONTROL Register ................................................. 2-7
IMEM_CONTROL Register ................................................... 2-7
DCPLB_DATAx Registers ....................................................... 2-8
ICPLB_DATAx Registers ......................................................... 2-9
CHIP BUS HIERARCHY
Chip Bus Hierarchy Overview ....................................................... 3-1
Interface Overview ........................................................................ 3-2
Internal Clocks ........................................................................ 3-3
Core Bus Overview .................................................................. 3-3
Peripheral Access Bus (PAB) ..................................................... 3-4
PAB Arbitration .................................................................. 3-5
PAB Agents (Masters, Slaves) ............................................... 3-5
PAB Performance ................................................................ 3-6

Contents
iv ADSP-BF59x Blackfin Processor Hardware Reference
DMA Access Bus (DAB), DMA Core Bus (DCB) .................... 3-6
DAB and DCB Arbitration ................................................. 3-6
DAB Bus Agents (Masters) .................................................. 3-7
DAB and DCB Performance ............................................... 3-8
SYSTEM INTERRUPTS
Specific Information for the ADSP-BF59x .................................... 4-1
Overview ...................................................................................... 4-1
Features .................................................................................. 4-2
Description of Operation .............................................................. 4-2
Events and Sequencing ............................................................ 4-2
System Peripheral Interrupts .................................................... 4-4
Programming Model ..................................................................... 4-7
System Interrupt Initialization ................................................. 4-7
System Interrupt Processing Summary ..................................... 4-8
System Interrupt Controller Registers .......................................... 4-10
System Interrupt Assignment (SIC_IAR) Register .................. 4-10
System Interrupt Mask (SIC_IMASK) Register ...................... 4-12
System Interrupt Status (SIC_ISR) Register ........................... 4-12
System Interrupt Wakeup-Enable (SIC_IWR) Register ........... 4-12
Programming Examples .............................................................. 4-13
Clearing Interrupt Requests ................................................... 4-13
Unique Information for the ADSP-BF59x Processor .................... 4-15
Interfaces .............................................................................. 4-15
System Peripheral Interrupts .................................................. 4-17

ADSP-BF59x Blackfin Processor Hardware Reference v
Contents
DIRECT MEMORY ACCESS
Specific Information for the ADSP-BF59x ..................................... 5-1
Overview and Features .................................................................. 5-2
DMA Controller Overview ............................................................ 5-4
External Interfaces ................................................................... 5-4
Internal Interfaces ................................................................... 5-4
Peripheral DMA ...................................................................... 5-5
Memory DMA ........................................................................ 5-6
Handshaked Memory DMA (HMDMA) Mode ................... 5-8
Modes of Operation ...................................................................... 5-9
Register-Based DMA Operation ............................................... 5-9
Stop Mode ........................................................................ 5-11
Autobuffer Mode .............................................................. 5-11
Two-Dimensional DMA Operation ........................................ 5-11
Examples of Two-Dimensional DMA ................................ 5-12
Descriptor-based DMA Operation ......................................... 5-13
Descriptor List Mode ........................................................ 5-14
Descriptor Array Mode ..................................................... 5-15
Variable Descriptor Size .................................................... 5-15
Mixing Flow Modes .......................................................... 5-16
Functional Description ............................................................... 5-17
DMA Operation Flow ........................................................... 5-17
DMA Startup .................................................................... 5-17
DMA Refresh ................................................................... 5-22

Contents
vi ADSP-BF59x Blackfin Processor Hardware Reference
Work Unit Transitions ...................................................... 5-24
DMA Transmit and MDMA Source .............................. 5-25
DMA Receive ............................................................... 5-26
Stopping DMA Transfers .................................................. 5-28
DMA Errors (Aborts) ............................................................ 5-28
DMA Control Commands .................................................... 5-31
Restrictions ...................................................................... 5-34
Transmit Restart or Finish ............................................. 5-34
Receive Restart or Finish ............................................... 5-35
Handshaked Memory DMA Operation .................................. 5-36
Pipelining DMA Requests ................................................. 5-37
HMDMA Interrupts ......................................................... 5-39
DMA Performance ................................................................ 5-40
DMA Throughput ............................................................ 5-41
Memory DMA Timing Details .......................................... 5-44
Static Channel Prioritization ............................................ 5-44
Temporary DMA Urgency ................................................ 5-44
Memory DMA Priority and Scheduling ............................. 5-46
Traffic Control ................................................................. 5-48
Programming Model .................................................................. 5-50
Synchronization of Software and DMA .................................. 5-50
Single-Buffer DMA Transfers ............................................ 5-52
Continuous Transfers Using Autobuffering ........................ 5-53
Descriptor Structures ........................................................ 5-55

ADSP-BF59x Blackfin Processor Hardware Reference vii
Contents
Descriptor Queue Management ......................................... 5-56
Descriptor Queue Using Interrupts on Every Descriptor 5-57
Descriptor Queue Using Minimal Interrupts .................. 5-58
Software Triggered Descriptor Fetches ............................... 5-60
DMA Registers ........................................................................... 5-62
DMA Channel Registers ........................................................ 5-62
DMA Peripheral Map Registers DMAx_PERIPHERAL_MAP/
MDMA_yy_PERIPHERAL_MAP) ................................ 5-66
DMA Configuration Registers
(DMAx_CONFIG/MDMA_yy_CONFIG) ................... 5-67
DMA Interrupt Status Registers
(DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS) ...... 5-71
DMA Start Address Registers
(DMAx_START_ADDR/MDMA_yy_START_ADDR) .. 5-74
DMA Current Address Registers
(DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR) .... 5-74
DMA Inner Loop Count Registers
(DMAx_X_COUNT/MDMA_yy_X_COUNT) ............. 5-75
DMA Current Inner Loop Count Registers
(DMAx_CURR_X_COUNT
/MDMA_yy_CURR_X_COUNT) ................................. 5-76
DMA Inner Loop Address Increment Registers
(DMAx_X_MODIFY/MDMA_yy_X_MODIFY) ........... 5-77
DMA Outer Loop Count Registers
(DMAx_Y_COUNT/MDMA_yy_Y_COUNT) .............. 5-78
DMA Current Outer Loop Count Registers
(DMAx_CURR_Y_COUNT/
MDMA_yy_CURR_Y_COUNT) .................................. 5-78

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viii ADSP-BF59x Blackfin Processor Hardware Reference
DMA Outer Loop Address Increment Registers
(DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY) ........... 5-79
DMA Next Descriptor Pointer Registers
(DMAx_NEXT_DESC_PTR/
MDMA_yy_NEXT_DESC_PTR) .................................. 5-80
DMA Current Descriptor Pointer Registers
(DMAx_CURR_DESC_PTR/
MDMA_yy_CURR_DESC_PTR) ................................. 5-81
HMDMA Registers ............................................................... 5-82
Handshake MDMA Control Registers
(HMDMAx_CONTROL) ............................................. 5-82
Handshake MDMA Initial Block Count Registers
(HMDMAx_BCINIT) ................................................... 5-84
Handshake MDMA Current Block Count Registers
(HMDMAx_BCOUNT) ............................................... 5-84
Handshake MDMA Current Edge Count Registers
(HMDMAx_ECOUNT) ............................................... 5-85
Handshake MDMA Initial Edge Count Registers
(HMDMAx_ECINIT) ................................................... 5-86
Handshake MDMA Edge Count Urgent Registers
(HMDMAx_ECURGENT) ........................................... 5-87
Handshake MDMA Edge Count Overflow Interrupt
Registers (HMDMAx_ECOVERFLOW) ........................ 5-87
DMA Traffic Control Registers
(DMA_TC_PER and DMA_TC_CNT) ............................. 5-88
DMA_TC_PER Register .................................................. 5-88
DMA_TC_CNT Register ................................................. 5-88
Programming Examples .............................................................. 5-90