Intel 80386 Quick user guide

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inter
80386
HARDWARE REFERENCE MANUAL
1987

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may
appear in this document nor does it make a commitment
tQ update the information contained herein.
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CINTEL CORPORATION 1987
ii
CG·5/26/87

PREFACE
The Intel 80386 is a high-performance 32-bit microprocessor. This manual provides complete
hardware reference information for 80386 system designs. It is written for system engineers
and hardware designers who understand the operating principles of microprocessors and
microcomputer systems. Readers of this manual should be familiar with the information in
the Introduction to the 80386 (Intel publication Order Number 231252).
RELATED PUBLICATIONS
In this manual, the 80386 is presented from a hardware perspective. Information on the
software architecture, instruction set, and programming of the 80386 can be found in these
related Intel publications:
• 80386 Programmer's Reference Manual, Order Number 230985
• 80386 System Software Writer's Guide, Order Number 231499
• 80386 Data Sheet, Order Number 231630
The 80386 Data Sheet contains device specifications for the 80386. Always consult the most
recent version of this publication for specific 80386 parameter values.
Detailed device specifications on 80386 family components can be found in the following
publications:
• 80387 Data Sheet, Order Number 231920
• 82380 Data Sheet, Order Number 290128
Together with the 80386 Hardware Reference Manual, these publications provide a complete
description of the 80386 system for hardware designers, software engineers, and all users of
80386 systems.
ORGANIZATION OF THIS MANUAL
The information in this manual is divided into 12 chapters and three appendices. The material
begins with a description of the 80386 microprocessor and continues with discussions of
hardware design information needed to implement 80386 system designs.
• Chapter 1, "System Overview." This chapter provides an overview of the 80386 and its
supporting devices.
• Chapter 2, "Internal Architecture." This chapter describes the internal architecture of
the 80386.
• Chapter 3, "Local Bus Interface." This chapter discusses the 80386 local bus interface.
This chapter includes 80386 signal descriptions, memory and I/O organization, and local
bus interface guidelines.
iii

PREFACE
• Chapter 4, "Performance Considerations." This chapter explores the factors that affect
the performance of an 80386 system.
o Chapter 5, "Coprocessor Hardware Interface." This chapter describes the interface
between the 80386 and the 80287 and 80387 Numeric Coprocessors. Each of these copro-
cessors expands the floating-point numerical processing capabilities of the 80386.
o Chapter 6, "Memory Interfacing." This chapter discusses techniques for designing memory
subsystems for the 80386.
• Chapter
7, "Cache Subsystems." This chapter describes cache memory subsystems, which
provide higher performance at lower relative cost.
o Chapter 8, "I/O Interfacing." This chapter discusses techniques for connecting I/O devices
to an 80386 system.
• Chapter 9, "MULTIBUS® I and 80386." This chapter describes the interface between
an 80386 system and the Intel MULTIBUS I multi-master system bus.
• Chapter 10, "MULTIBUS® II and 80386." This chapter describes the interface between
an 80386 system and the Intel
MUL TIBUS II multi-master system bus.
o Chapter 11, "Physical Design and Debugging." This chapter contains recommendations
for constructing and debugging 80386 systems.
• Chapter 12, "Test Capabilities." This chapter describes 80386 test procedures.
o Appendix A contains descriptions of the components of the basic memory. interface
described
in Chapter 6.
• Appendix B contains descriptions of the components of the 80387 emulator described in
Chapter
5.
o Appendix C contains descriptions of the components of the dynamic RAM subsystem
described
in Chapter 6.
iv

TABLE OF CONTENTS
CHAPTER 1 Page
SYSTEM OVERVIEW
1.1 Microprocessor ............................................................................................. 1-1
1.2 Coprocessors.................................................................................................. 1-3
1.3 Integrated System Peripheral ....................
l................................................... 1-4
1.4 Cache Controller ........................................................................................... 1-5
1.5 Clock Generator ............................................................................................ 1-5
1.6 8086/80286 Family Components
.... .............................................................. 1-5
CHAPTER 2
INTERNAL ARCHITECTURE
2.1 Bus Interface Unit .......................................................................................... 2-2
2.2 Code Prefetch Unit ........................................................................................ 2-3
2.3 Instruction Decode
Unit ................................................................................. 2-3
2.4 Execution Unit ............................................................................................... 2-3
2.5 Segmentation Unit ......................................................................................... 2-4
2.6 Paging Unit .................................................................................................... 2-4
CHAPTER 3
LOCAL BUS INTERFACE
3.1 Bus Operations ............................................................................................. 3-2
3.1.1 Bus States ................................................................................................. 3-4
3.1.2 Address Pipelining
.. .................................................................................... 3-5
3.1.3 32-Bit Data Bus Transfers
and Operand Alignment .... ............................... 3-5
3.1.4
Read Cycle .. ............................................................................................... 3-10
3.1.5 Write Cycle ................................................................................................. 3-13
3.1.6 Pipelined Address Cycle ............................................................................. 3-14
3.1.7 Interrupt Acknowledge Cycle ..................................................................... 3-17
3.1.8 Halt/Shutdown Cycle ................................................................................. 3-18
3.1.9 BS16 Cycle ................................................................................................ 3-19
3.1.10 16-Bit Byte Enables and Operand Alignment ........................................... 3·20
3.2 Bus Timing .................................................................................................... 3-22
3.2.1 Read Cycle Timing ..................................................................................... 3-24
3.2.2 Write Cycle Timing ..................................................................................... 3-24
3.2.3 READY# Signal Timing .............................................................................. 3-25
3.3 Clock Generation ........................................................................................... 3-26
3.3.1 82384 Clock Generator .............................................................................. 3-26
3.3.2 Clock Timing .............................................................................................. 3-26
3.3.3 Crystal Oscillator Clock Generator
.. ........................................................... 3-27
3.4 Interrupts ....................................................................................................... 3-29
3.4.1 Non-Maskable Interrupt (NMI) .................................................................... 3-30
3.4.2 Maskable Interrupt (INTR) .......................................................................... 3-31
3.4.3 Interrupt Latency ........................................................................................ 3-31
v

TABLE OF CONTENTS
. Page
3.5 Bus Lock ......... ... ................... ......... ............................ ... ................................ 3-32
3.5.1 Locked Cycle Activators .....
...... ........................................................ ... ....... 3-32
3.5.2 Locked Cycle
Timing .......... ......... ..................................................... ... .... ... 3-32
3.5.3
LOCK# Signal Duration ............ ...... ............................... ... ..... ...... .............. 3-33
3.6 HOLD/HLDA
(Hold Acknowledge) ................................................................. 3-34
3.6.1 HOLD/HLDA
Timing ................................................................................... 3-34
3.6.2 HOLD
Signal Latency............. ... ....................................... ... ....................... 3-36
3.6.3 HOLD State
Pin Conditions ........................................................................ 3-36
3.7 Reset ............................................................................................................. 3-37
3.7.1 RESET
Timing .......:.................................................................................... 3-37
3.7.2 80386
Internal States ................................................................................. 3-38
3.7.3 80386 External States ............................................................................... 3-38
CHAPTER 4
PERFORMANCE CONSIDERATIONS
4.1 Wait States and Pipelining ........................... ... ................... ... ......................... 4-1
CHAPTER 5
COPROCESSOR HARDWARE INTERFACE
5.1 80287 Numeric Coprocessor Interface .......................................................... 5-2
5.1.1 80287 Connections .................................................................................... 5-2
5.1.2 80287
Bus Cycles ...................................................................................... 5-2
5.1.3 80287 Clock
Input ...................................................................................... 5-4
5.2 80387 Numeric Coprocessor Interface .......................................................... 5-4
5.2.1 80387 Connections .................................................................................... 5-4
5.2.2 80387
Bus Cycles ...................................................................................... 5-6
5.2.3 80387 Clock
Input ...................................................................................... 5-6
5.3
Local Bus Activity with the 80287/80387 ...................................................... 5-7
5.4
Designing an Upgradable 80386 System ...................................................... 5-8
5.4.1 80287/80387 Recognition .......................................................................... 5-8
5.4.1.1 Hardware Recognition .of the NPX .......................................................... 5-8
5.4.1.2 Software Recognition of the NPX ............................................................ 5-8
5.4.2 80387 Emulator .......................................................................................... 5-10
CHAPTER 6
MEMORY INTERFACING
6.1 Memory Speed versus Performance and Cost ... ........................... ...... ....... ... 6-1
6.2 Basic Memory Interface ........... ... ................ ... .......... ...... ..... ... ........ ... .......... ... 6-1
6.2.1 PAL Devices ............................................................................................... 6-2
6.2.2 Address
Latch . ... ........ ... .............. ... ........... ... .................... ............... ........... 6-3
6.2.3 Address Decoder
.. ..................................... ... ...... ... .................................... 6-4
6.2.4 Data Transceiver
... ...................... ... ....................... ...... ............................... 6-5
6.2.5
Bus Control Logic ........................................................... ......... .................. 6-6
vi

TABLE OF CONTENTS
Page
6.2.6 EPROM Interface ....................................................................................... 6-9
6.2.7 SRAMlnterface ...........................................................................................
6-11
6.2.8 16-Bit Interface ........................................................................................... 6-14
6.3 Dynamic RAM (DRAM) Interface ................................................................... 6-15
6.3.1 Interleaved Memory .................................................................................... 6-15
6.3.2 DRAM Memory Performance .....................................................
.... ............ 6-15
6.3.3 DRAM Controller ........................................................................................ 6-16
6.3.3.1 3-CLK DRAM Controller .......................................................................... 6-17
6.3.3.2 2-CLK DRAM Controller ..........................................................................
6-21
6.3.4 DRAM Design Variations ............................................................................ 6-23
6.3.5 Refresh Cycles ........................................................................................... 6-25
6.3.5.1 Distributed Refresh ................................................................................. 6-25
6.3.5.2 Burst Refresh .......................................................................................... 6-26
6.3.5.3 DMA Refresh using the 82380 DRAM Refresh Controller ....................... 6-26
6.3.6 Initialization ...:............................................................................................. 6-27
6.3.7 Timing AnalysiS .......................................................................................... 6-28
CHAPTER 7
CACHE SUBSYSTEMS
7.1 Introduction to Caches .................................................................................. 7-2
7.1.1 Program Locality ........................................................................................ 7-2
7.1.2 Block Fetch ................................................................................................ 7-2
7.2 Cache Organizations ..................................................................................... 7-3
7.2.1 Fully Associative Cache .............................................................................. 7-3
7.2.2 Direct Mapped Cache ................................................................................. 7-4
7.2.3 Set Associative Cache ............................................................................... 7-6
7.3 Cache Updating ............................................................................................. 7-8
7.3.1 Write-Through System ............................................................................... 7-8
7.3.2 Buffered Write-Through System ................................................................. 7-8
7.3.3 Write-Back System .................................................................................... 7-9
7.3.4 Cache Coherency ....................................................................................... 7-10
7.4 Efficiency and Performance ........................................................................... 7-12
7.5 Cache and DMA ............................................................................................ 7-12'
7.6 Cache Example ............................................................................................. 7-13
7.6.1 Example Design ......................................................................................... 7-14
7.6.2 Example Cache Memory Organization
.. ..................................................... 7-14
7.6.3 Example Cache Implementation ................................................................. 7-15
CHAPTERS
I/O INTERFACING
8.1 I/O Mapping versus Memory Mapping .......................................................... 8-1
8.2 8-Bit, 16-Bit, and 32-Bit I/O Interfaces .......................................................... 8-1
8.2.1 Address Decoding ...................................................................................... 8-1
vii

TABLE OF CONTENTS
Page
8.2.2 8-Bit I/O .. ... ............... ... ................... ......... .............................. ... ................. 8-2
8.2.3 16-Bit I/O ........................................................................................... '" ..... 8-4
8.2.4 32-Bit I/O ......... .......................................................................................... 8-4
8.2.5 Linear Chip Selects .................................... '" ...................... ......... .............. 8-4
8.3 Basic I/O Interface ........................................................:................................ 8-4
8.3.1 Address Latch .......................... ...... .... ... .... ... .............................................. 8-5
8.3.2 Address Decoder .......................
... ...................................... ... .................... 8-6
8.3.3 Data Transceiver ........................................................, ... ............................ 8-8
8.3.4 Bus Control Logic .......................................................... ... ......................... 8-8
8.4 Timing Analysis for I/O Operations ................................................................ 8-9
8.5 Basic I/O Examples ...........
'" ......................................................................... 8-14
8.5.1 8274 Serial Controller .............................................................................. '" 8-14
8.5.2 82380 Programmable Interrupt Controller .. ................................................ 8-15
8.5.2.1 Cascaded Interrupt Controllers to the 82380 PIC ................................... 8-15
8.5.3 8259A Interrupt Controller .......................................................................... 8-15
8.5.3.1 Single Interrupt Controller ....................................................................... 8-16
8.5.3.2 Cascaded Interrupt Controllers ...................................................... ,.. ...... 8-16
8.5.3.3 Handling More Than 64 Interrupts ........................................................... 8-17
8.6 80286-Compatible Bus Cycles ....................................;................................. 8-17
8.6.1 AO/A 1 Generator ......................,.....................................................,........... 8-18
8.6.2 SO#/S1# Generator .................................................................................. 8-18
8.6.3 Wait-State Generator ................................................................................. 8-19
8.6.4 Bus Controller and Bus Arbiter .................................................................. 8-20
8.6.5 82380 Integrated System Peripheral........................................................... 8-21
8.6.6 82258 ADMA Controller ............................................................................. 8-23
8.6.6.1 82258 as Bus Master .............................................................................. 8-25
8.6.6.2 82258 as Peripheral ....................................:........................................... 8-26
8.6.7 82586 LAN Coprocessor ............................................................................ 8-27
8.6.7.1 Dedicated
CPU ........................................................................................ 8-28·
8.6.7.2 Decoupled Dual-Port Memory ................................................................. 8-29
8.6.7.3 Coupled Dual-Port Memory ..................................................................... 8-30
8.6.7.4 Shared Bus ............................................................................................. 8-30
CHAPTER 9
MUL
TIBUS® I AND 80386
9.1 MUL TIBUS® I (IEEE 796) ............................................................................... 9-1
9.2 MUL TIBUS® I Interface Example ................................................................... 9-2
9.2.1 Address Latches and Data Transceivers .................................................... 9-2
9.2.2 Address Decoder .. ..................................................................................... 9-5
9.2.3 Wait-State Generator ................................................................................. 9-5
9.2.4 Bus Controller and Bus Arbiter .................................................................. 9-7
9.3 Timing Analysis of MUL TIBUS® I Interface .................................................... 9-10
9.4 82289 Bus Arbiter ......................................................................................... 9-10
viii

TABLE OF CONTENTS
9.4.1 Priority Resolution ......................................................................................
9.4.2 82289 Operating Modes ............................................................................
Q.4.3 MUL TIBUS® I Locked Cycles .....................................................................
9.5 Other
MULTIBUS® I Design Considerations ..................................................
9.5.1 Interrupt-Acknowledge on MUL
TIBUS® I .................................................. ..
9.5.2 Byte Swapping during MUL TIBUS® I Byte Transfers .................................
9.5.3 Bus Timeout Function for MUL
TIBUS® I Accesses ....................................
9.5.4 MUL
TIBUS® I Power Failure Handling ........................................................
9.6
iL~XTM Bus Expansion ...................................................................................
9.7 Dual-Port RAM with
MULTIBUS® I ................................................................
9.7.1
AVOiding Deadlock with Dual-Port RAM
CHAPTER 10
MULTIBUS® II AND 80386
10.1 MUL TIBUS® II Standard
10.2 Parallel System Bus (iPSB) ........................................................:.................
10.2.1 iPSB Interface ..........................................................................................
10.2.1.1 BAC Signals ..........................................................................................
10.2.1.2 MIC Signals ...........................................................................................
10.3 Local Bus Extension
(iLBXTM II) ....................................................................
10.4 Serial System Bus (iSSB) ............................................................................
CHAPTER 11
PHYSICAL DESIGN AND DEBUGGING
Page
9-11
9-11
9-14
9-14
9-14
9-16
9-17
9-17
9-18
9-19
9-20
10-1
10-1
10-2
10-4
10-6
10-7
10-7
11.1 Power and Ground Requirements ............................................................... 11-1
11 .1.1 Power and Ground Planes ....................................................................... 11-1
11 .1.2 Decoupling Capacitors ............................................................................. 11-2
11.2 High-Frequency Design Considerations .... ... .... ... .......... ... ........................... 11-3
11.2.1 Line Termination ....................................................................................... 11-4
11.2.2 Interference
... .............................................................. ......... .................... 11-5
11.2.3 Latchup .................................................................................................... 11-7
11.3 Clock Distribution
and Termination ............................................................. 11-7
11.4 Thermal Characteristics ............................................................................... 11-7
11.5 Debugging Considerations .......................................................................... 11-10
11.5.1 Hardware Debugging Features ................................................................ 11-10
11.5.2 Bus Interface .................................................................................;.......... 11-11
11 .5.3 Simplest Diagnostic Program .. ......... ....... ...... ........................................... 11-11
11 .5.4 Building and Debugging a System Incrementally .. ......... ...... ........ ... ... ....... 11-12
11.5.5 Other Simple Diagnostic Software ........................................................... 11-14
11.5.6 Debugging Hints ....................................................................................... 11-14
ix

TABLE OF CONTENTS
CHAPTER 12
TEST CAPABILITIES
12.1 Internal Tests .............................................................................................. 12-1
12.1.1 Automatic Self-Test .................................................................................. 12-1
12.1.2 Translation Lookaside Buffer Tests .......................................................... 12-2
12.2 Board-Level Tests ....................................................................................... 12-5
APPENDIX A
LOCAL !:IUS CONTROL PAL DESCRIPTIONS
PAL-1 Functions ................................................................................................... A-1
PAL-2 Functions ................................................................................................... A-2
PAL Equations ..................................................................................................... A-2
APPENDIX B
80387 EMULATOR PAL DESCRIPTION
APPENDIX C
DRAM
PAL DESCRIPTIONS
DRAM State PAL .................................................................................................
DRAM Control PAL ..............................................................................................
Refresh Interval Counter
PAL ...............................................................................
Refresh Address Counter
PAL .............................................................................
Timing Parameters
Figures
C-1
C-13
C-13
C-13
C-25
Figure Title Page
1-1 80386 System Block Diagram ................................................................ 1-2
2-1 Instruction Pipelining ............................................................................... 2-1
2-2 80386 Functional Units ........................................................................... 2-2
3-1 CLK2 and CLK Relationship ................................................................... 3-5
3-2 80386 Bus States Timing Example ........................................................ 3-6
3-3 Bus State
Diagram (Does Not Include Address Pipelining) ..................... 3-7
3-4 Non-Pipelined Address
and Pipelined Address Differences .................... 3-8
3-5 Consecutive Bytes
in Hardware Implementation .................................... 3-9
3-6 Address, Data Bus, and Byte Enables for 32-Bit Bus ............................ 3-9
3-7 Misaligned Transfer ................................................................................ 3-11
3-8 Non-Pipelined Address Read Cycles ...................................................... 3-12
3-9 Non-Pipelined Address Write Cycles ...................................................... 3-15
3-10 Pipelined Address Cycles ....................................................................... 3-16
3-11 Interrupt Acknowledge Bus Cycles ......................................................... 3-18
3-12 Internal
NA# and BS16# Logic ............................................................. 3-20
3-13 32-Bit and 16-Bit Bus Cycle Timing ........................................................ 3-21
x

Figure
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
5-1
5-2
5-3
5-4
5-5
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
8-1
8-2
8-3
8-4
8-5
8-6
8-7
TABLE OF CONTENTS
Title
32-Bit and 16-Bit Data Addressing .........................................................
Connecting 82384 to 80386 ...................................................................
Using CLK to Determine Bus Cycle Start ...............................................
Clock Generator .....................................................................................
ADS#
Synchronizer ...............................................................................
Error Condition Caused by Unlocked Cycles ..........................................
LOCK# Signal during Address Pipelining ............................................. ..
Bus State Diagram with HOLD State ................................................... ..
Typical RC RESET Timing Circuit ...........................................................
RESET, CLK, and CLK2 Timing .............................................................
80386 System with 80287 Coprocessor ................................................
80386 System with 80387 Coprocessor .............................................. ..
Pseudo-Synchronous Interface ...............................................................
Software Routine to Recognize the 80287 .............................................
80387 Emulator Schematic ....................................................................
Basic Memory Interface Block Diagram ..................................................
PAL Equation and Implementation ....................................................... ..
PAL Naming Conventions .......................................................................
Bus Control Logic ...................................................................................
Bus Control Signal Timing ......................................................................
150-Nanosecond EPROM Timing Diagram .............................................
100-Nanosecond SRAM Timing Diagram ...............................................
3-CLK DRAM Controller Schematic ...................................................... ..
3-CLK DRAM Controller Cycles ............................................................ ..
2-CLK DRAM Controller Schematic ...................................................... ..
2-CLK DRAM Controller Cycles ..............................................................
Refresh Request Generation ..................................................................
Cache Memory System ..........................................................................
Fully Associative Cache Organization .....................................................
Direct Mapped Cache Organization ........................................................
Two-Way Set Associative Cache Organization ......................................
Stale Data Problem .................................................................................
Bus Watching .........................................................................................
Hardware Transparency .........................................................................
Non-Cacheable Memory .........................................................................
Example of Cache Memory Organization ...............................................
32-Bit to 8-Bit Bus Conversion ...............................................................
Linear Chip Selects .................................................................................
Basic I/O Interface Block Diagram ..........................................................
Basic I/O Interface Circuit .......................................................................
Basic I/O Timing Diagram .......................................................................
8274
Interface ........................................................................................
Single 8259A Interface ...........................................................................
xi
Page
3-22
3-27
3-28
3-28
3-29
3-33
3-34
3-35
3-37
3-38
5-3
5-5
5-7
5-9
5-11
6-2
6-4
6-5
6-7
6-8
6-10
6-12
6-18
6-20
6-22
6-24
6-27
7-1
7-4
7-5
7-7
7-9
7-10
7-11
7-12
7-15
8-3
8-5
8-6
8-7
8-11
_8-14
8-16

Figure
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
10-1
10-2
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
12-1
12-2
A-1
A-2
TABLE OF CONTENTS
Title
80286-Compatible Interface ...................................................................
AO, A1, and BHE# Logic ...................................................................... ..
SO#/S1 # Generator Logic .....................................................................
Wait-State Generator Logic ....................................................................
82288 and 82289 Connections ............................................................ ..
80386/82380 Interface ...........................................................................
HOLD and HLDA Logic for 80386-82258 Interface .............................. ..
82258 Slave Mode Interface ...................................................................
LAN Station ............................................................................................
Decoupled Dual-Port Memory Interface ................................................ ..
Coupled Dual-Port Memory Interface .....................................................
Shared Bus Interface ..............................................................................
80386-MUL TIBUS® I Interface ...............................................................
MUL TIBUS® I Address Latches and Data Transceivers .........................
Wait-State Generator Logic ........................,......................................... ..
MUL TIBUS® Arbiter and Bus Controller .................................................
MUL TIBUS® I Read Cycle Timing ........................................................ ..
MUL TIBUS® I Write Cycle Timing ........................................................ ..
Bus Priority Resolution ...........................................................................
Operating Mode Configurations ..............................................................
. Bus-Select Logic for Interrupt Acknowledge ........................................ ..
Byte-Swapping Logic ..............................................................................
Bus-Timeout Protection Circuit ...............................................................
iLBX'" Signal Generation ........................................................................
iPSB Bus Cycle Timing ...........................................................................
iPSB Bus Interface .................................................................................
Reducing Characteristic Impedance .......................................................
Circuit without Decoupling .................................................................... ;.
Decoupling Chip Capacitors ................................................................. ..
Decoupling Leaded Capacitors ...............................................................
Series Termination ..................................................................................
Split Termination ..........:.............................................................. ~ ...........
Avoid Closed-Loop Signal Paths .......................................................... ..
CLK2 Series Termination ...................................................................... ..
CLK2 Loading ....................................................................................... ..
CLK2 Waveforms ...................................................................................
4-Byte Diagnostic Program .....................................................................
More Complex Diagnostic Program ...................................................... ..
Object Code for Diagnostic Program ..............................................,..... ..
80386 Self-Test ......................................................................................
TLB Test Registers ................................................................................
PAL-1 State Listings ...............................................................................
PAL-2 State Listings ...............................................................................
xii
Page
8-19
8-21
8-22
8-22
8-23
8-24
8-25
8-26
8-28
8-29
8-30
8-31
9-3
9-4
9-6
9-7
9-8
9-9
9-12
9-13
9-16
9-18
9-19
9-20
10-3
10-4
11-2
11-2
11-3
11-4
11-5
11-5
11-6
11-8
11-9
11-9
11-12
11-15
11-16
12-2
12-3
A-3
A-9

TABLE OF CONTENTS
Figure Title Page
A-3 PAL-1 Equations ..................................................................................... A-14
A-4 PAL-2 Equations ..................................................................................... A-15
B-1 80387 Emulator PAL Equations ............................................................. B-1
C-1 PAL Sampling Edges .............................................................................. C-1
C-2 3-CLK DRAM State PAL Equations ........................................................ C-3
C-3 2-CLK DRAM State PAL Equations ........................................................ C-8
C-4
3-CLK DRAM Control PAL Equations .................................................... C-15
C-5 2-CLK DRAM Control PAL Equations .................................................... C-17
C-6 Refresh Interval Counter PAL Equations ................................................ C-20
C-7 Refresh Address Counter PAL Equations .............................................. C-23
C-8 DRAM Circuit Timing Diagram .............................,.................................. C-26
Tables
Table Title Page
1-1 80386 System Components ................................................................... 1-1
3-1 Summary of 80386 Signal Pins .............................................................. 3-3
3-2 Bus Cycle Definitions .............................................................................. 3-4
3-3 Possible Data Transfers
on 32-Bit Bus ................................................... 3-10
3-4 Misaligned Data Transfers on 32-Bit Bus ............................................... 3-13
3-5 Generation of BHE#, BLE#,
and A1 from Byte Enables ....................... 3-23
3-6 Byte Enables during BS16 Cycles ......................................................
.... 3-23
3-7 Output
Pin States during RESET ........................................................... 3-39
4-1 80386 Performance with Wait States and Pipelining .............................. 4-1
4-2 Performance versus Wait States and Operating Frequency ................... 4-3
6-1 Bus Cycles Generated by Bus Controller ............................................... 6-6
6-2 DRAM Memory Performance .................................................................. 6-16
6-3 Designs for Six
DRAM Types ................................................................. 6-28
7-1 Cache Hit Rates ..................................................................................... 7-13
8-1 Data Lines for 8-Bit I/O Addresses ......................................................... 8-2
8-2 Timings for Peripherals using Basic I/O Interface ................................... 8-13
8-3
AO, A1, and BHE# Truth Table .............................................................. 8-20
9-1 MUL TIBUS® I Timing Parameters .......................................................... 9-10
C-1 DRAM State PAL Pin Description .............................,............................. C-2
C-2 DRAM Control PAL Pin Description ........................................................ C-14
C-3 Refresh Interval Counter PAL Pin Description ........................................ C-19
C-4 Refresh Address Counter PAL Pin Description ....................................... C-22
C-5 DRAM Circuit Timing Parameters ........................................................... C-27
xiii

inter
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xiv

System Overview 1