Analog Devices dBCOOL ADT7463 User manual

a
ADT7463
*
dB COOL
™
Remote Thermal
Controller and Voltage Monitor
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
Monitors up to 5 Supply Voltages
Controls and Monitors up to 4 Fan Speeds
1 On-Chip and 2 Remote Temperature Sensors
Monitors up to 6 Processor VID Bits
Dynamic TMIN Control Mode Optimizes System
Acoustics Intelligently
Automatic Fan Speed Control Mode Controls System
Cooling Based on Measured Temperature
Enhanced Acoustic Mode Dramatically Reduces User
Perception of Changing Fan Speeds
Thermal Protection Feature via THERM Output
Monitors Performance Impact of Intel®Pentium®4
Processor Thermal Control Circuit via THERM Input
2-Wire and 3-Wire Fan Speed Measurement
Limit Comparison of All Monitored Values
Meets SMBus 2.0 Electrical Specifications
(Fully SMBus 1.1 Compliant)
APPLICATIONS
Low Acoustic Noise PCs
Networking and Telecommunications Equipment
FUNCTIONAL BLOCK DIAGRAM
BAND GAP
REFERENCE
10-BIT
ADC
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
GND
SERIAL BUS
INTERFACE
SCL SDA
ADDRESS
POINTER
REGISTER
ADT7463
VALUE AND
LIMIT
REGISTERS
LIMIT
COMPARATORS
PWM
CONFIGURATION
REGISTERS
INTERRUPT
STATUS
REGISTERS
BAND GAP
TEMP. SENSOR
V
CC
TO ADT7463
INTERRUPT
MASKING
SMBALERT
V
CC
SMBUS
ADDRESS
SELECTION
ADDR EN
ADDR
SELECT
THERMAL
PROTECTION
PERFORMANCE
MONITORING
THERM
PWM
REGISTERS
AND
CONTROLLERS
PWM1
PWM2
PWM3
ACOUSTIC
ENHANCEMENT
CONTROL
AUTOMATIC
FAN SPEED
CONTROL
DYNAMIC
T
MIN
CONTROL
FAN SPEED
COUNTER
TACH1
TACH2
TACH3
TACH4
D1+
D1–
D2+
D2–
V
CC
+5V
IN
+12V
IN
+2.5V
IN
V
CCP
VID
REGISTER
VID5
VID4
VID3
VID2
VID1
VID0
GENERAL DESCRIPTION
The ADT7463 dBCOOL controller is a complete systems
monitor and multiple PWM fan controller for noise-sensitive
applications requiring active system cooling. It can monitor
12 V, 5 V, and 2.5 V CPU supply voltages, plus its own supply
voltage. It can monitor the temperature of up to two remote
sensor diodes, plus its own internal temperature. It can measure
and control the speed of up to four fans so that they operate at the
lowest possible speed for minimum acoustic noise. The automatic
fan speed control loop optimizes fan speed for a given temperature.
A unique dynamic T
MIN
control mode enables the system
thermals/acoustics to be intelligently managed. The effectiveness
of the system’s thermal solution can be monitored using the
THERM input. The ADT7463 also provides critical thermal
protection to the system using the bidirectional THERM pin
as an output to prevent system or component overheating.
*Protected by U.S. Patent Nos. 6,188,189; 6,169,442; 6,097,239; 5,982,221; and 5,867,012. Other patents pending.
www.BDTIC.com/ADI

REV. C–2–
ADT7463–SPECIFICATIONS
1, 2, 3, 4
(TA= TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.)
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Supply Voltage 3.0 5.0 5.5 V
Supply Current, I
CC
3mAInterface Inactive, ADC Active
20 µAStandby Mode
TEMPERATURE-TO-DIGITAL CONVERTER
Local Sensor Accuracy ±0.5 ±1.5 ⬚C0⬚C ⱕT
A
ⱕ70⬚C
±3⬚C–40⬚C ⱕT
A
ⱕ+120⬚C
Resolution 0.25 ⬚C
Remote Diode Sensor Accuracy ±0.5 ±1.5 ⬚C
0 ⬚ C ⱕT
A
ⱕ70 ⬚ C; 0 ⬚ C ⱕT
D
ⱕ120 ⬚ C
±2.5 ⬚C 0 ⬚ C ⱕT
A
ⱕ105 ⬚ C; 0 ⬚ C ⱕT
D
ⱕ120 ⬚ C
±3⬚C 0 ⬚ C ⱕT
A
ⱕ120 ⬚ C; 0 ⬚ C ⱕT
D
ⱕ120 ⬚ C
Resolution 0.25 ⬚C
Remote Sensor Source Current 180 µAHigh Level
11 µALow Level
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error, TUE ±1.5 %
Differential Nonlinearity, DNL ±1LSB
Power Supply Sensitivity ±0.1 %/V
Conversion Time (Voltage Input) 11.38 13 ms Averaging Enabled
Conversion Time (Local Temperature) 12.09 13.50 ms Averaging Enabled
Conversion Time (Remote Temperature) 25.59 28 ms Averaging Enabled
Total Monitoring Cycle Time 120.17 134.50 ms Averaging Enabled
Total Monitoring Cycle Time 13.51 15 ms Averaging Disabled
Input Resistance 100 140 200 kΩ
FAN RPM-TO-DIGITAL CONVERTER
Accuracy ±7%0⬚C ⱕT
A
ⱕ70⬚C
±11 % 0⬚C ⱕT
A
ⱕ105⬚C
±13 % –40⬚C ⱕT
A
ⱕ+120⬚C
Full-Scale Count 65,535
Nominal Input RPM 109 RPM Fan Count = 0xBFFF
329 RPM Fan Count = 0x3FFF
5,000 RPM Fan Count = 0x0438
10,000 RPM Fan Count = 0x021C
Internal Clock Frequency 82.8 90.0 97.2 kHz
OPEN-DRAIN DIGITAL OUTPUTS,
PWM1 to PWM3, XTO
Current Sink, I
OL
8.0 mA
Output Low Voltage, V
OL
0.4 V I
OUT
= –8.0 mA, V
CC
= 3.3 V
High Level Output Current, I
OH
0.1 1 µAV
OUT
= V
CC
OPEN-DRAIN SERIAL DATA
BUS OUTPUT (SDA)
Output Low Voltage, V
OL
0.4 V I
OUT
= –4.0 mA, V
CC
= 3.3 V
High Level Output Current, I
OH
0.1 1 µAV
OUT
= V
CC
SMBUS DIGITAL INPUTS
(SCL, SDA)
Input High Voltage, V
IH
2.0 V
Input Low Voltage, V
IL
0.4 V
Hysteresis 500 mV
DIGITAL INPUT LOGIC LEVELS
(VID0 to VID5)
Input High Voltage, V
IH
1.7 V Bit 6 (THLD) Reg. 0x43 = 0
Input Low Voltage, V
IL
0.8 V (VID Threshold = 1 V)
Input High Voltage, V
IH
0.8 V Bit 6 (THLD) Reg. 0x43 = 1
Input Low Voltage, V
IL
0.4 V (VID Threshold = 0.6 V)
www.BDTIC.com/ADI

REV. C
ADT7463
–3–
Parameter Min Typ Max Unit Test Conditions/Comment
DIGITAL INPUT LOGIC LEVELS
(TACH INPUTS)
Input High Voltage, V
IH
2.0 V
5.5 V Maximum Input Voltage
Input Low Voltage, V
IL
+0.8 V
–0.3 V Minimum Input Voltage
Hysteresis 0.5 V p-p
DIGITAL INPUT LOGIC LEVELS
(THERM) AGTL+
Input High Voltage, V
IH
0.75 ⫻V
CCP
V
Input Low Voltage, V
IL
0.4 V
DIGITAL INPUT CURRENT
Input High Current, I
IH
–1 µAV
IN
= V
CC
Input Low Current, I
IL
+1 µAV
IN
= 0
Input Capacitance, C
IN
5pF
SERIAL BUS TIMING
5
Clock Frequency, f
SCLK
400 kHz See Figure 1
Glitch Immunity, t
SW
50 ns See Figure 1
Bus Free Time, t
BUF
1.3 µsSee Figure 1
Start Setup Time, t
SU;STA
0.6 µsSee Figure 1
Start Hold Time, t
HD;STA
0.6 µsSee Figure 1
SCL Low Time, t
LOW
1.3 µsSee Figure 1
SCL High Time, t
HIGH
0.6 50 µsSee Figure 1
SCL, SDA Rise Time, t
R
1000 ns See Figure 1
SCL, SDA Fall Time, t
F
300 µsSee Figure 1
Data Setup Time, t
SU;DAT
100 ns See Figure 1
Data Hold Time, t
HD;DAT
300 ns See Figure 1
Detect Clock Low Timeout, t
TIMEOUT
15 35 ms Can Be Optionally Disabled
NOTES
1
All voltages are measured with respect to GND, unless otherwise specified.
2
Typicals are at T
A
= 25°C and represent the most likely parametric norm.
3
Logic inputs accept input high voltages up to V
MAX
even when the device is operating down to V
MIN
.
4
Timing specifications are tested at logic levels of V
IL
= 0.8 V for a falling edge and V
IH
= 2.0 V for a rising edge.
5
Guaranteed by design, not production tested.
Specifications subject to change without notice.
P
S
tSU;DAT
tHIGH
tF
tHD;DAT
tR
tLOW
tSU;STO
PS
SCL
SDA
tHD;STA
tHD;STA
tSU;STA
tBUF
Figure 1. Diagram for Serial Bus Timing
www.BDTIC.com/ADI

REV. C–4–
ADT7463
ABSOLUTE MAXIMUM RATINGS*
Positive Supply Voltage (V
CC
) . . . . . . . . . . . . . . . . . . . . . 6.5 V
Voltage on +12V
IN
Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Voltage on Any Other Input or Output Pin . . . . –0.3 V to +6.5 V
Input Current at Any Pin . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
Package Input Current . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Maximum Junction Temperature (T
J
max) . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering
IR Reflow Peak Temperature . . . . . . . . . . . . . . . . . . . 220°C
IR Reflow Peak Temperature for Pb-free . . . . . . . . . . 260°C
Lead Temperature (soldering 10 sec) . . . . . . . . . . . . . 300°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
24-Lead QSOP Package:
θ
JA
= 105°C/W, θ
JC
= 39°C/W.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADT7463 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
ADT7463
TACH2
TACH1
PWM2/SMBALERT
TACH3
VID3
SDA
SCL
GND
V
CC
VID2
VID1
VID0
PWM3/ADDRESS ENABLE
TACH4/ADDRESS SELECT/THERM
D2–
D2+
D1–
PWM1/XTO
V
CCP
+2.5V
IN
/SMBALERT
+12V
IN
/VID5
D1+
VID4
+5V
IN
/THERM
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
ADT7463ARQ –40⬚C to +120⬚C24-Lead QSOP RQ-24
ADT7463ARQ-REEL –40⬚C to +120⬚C24-Lead QSOP RQ-24
ADT7463ARQ-REEL7 –40⬚C to +120⬚C24-Lead QSOP RQ-24
ADT7463ARQZ* –40⬚C to +120⬚C24-Lead QSOP RQ-24
ADT7463ARQZ-REEL* –40⬚C to +120⬚C24-Lead QSOP RQ-24
ADT7463ARQZ-REEL7* –40⬚C to +120⬚C24-Lead QSOP RQ-24
EVAL-ADT7463EB Evaluation Board
*Z = Pb-free part.
www.BDTIC.com/ADI

REV. C
ADT7463
–5–
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1SDA Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus.
2SCL Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
3GND Ground Pin for the ADT7463.
4V
CC
Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is required. V
CC
is also
monitored through this pin. The ADT7463 can also be powered from a 5 V supply. Setting Bit 7 of Configura-
tion Register 1 (Reg. 0x40) rescales the V
CC
input attenuators to correctly measure a 5 V supply.
5VID0 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
6VID1 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
7VID2 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
8VID3 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
9TACH3 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3. Can be reconfigured as an analog
input (AIN3) to measure the speed of 2-wire fans.
10 PWM2 Digital Output (Open Drain). Requires 10 kΩtypical pull-up. Pulse-width modulated output to control FAN 2
speed.
SMBALERT Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to signal
out-of-limit conditions.
11 TACH1 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1. Can be reconfigured as an analog
input (AIN1) to measure the speed of 2-wire fans.
12 TACH2 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. Can be reconfigured as an analog
input (AIN2) to measure the speed of 2-wire fans.
13 PWM3 Digital I/O (Open Drain). Pulse-width modulated output to control Fan 3/Fan 4 speed. Requires 10 kΩtypical
pull-up.
ADDRESS ENABLE If pulled low on power-up, this places the ADT7463 into address select mode, and the state of Pin 14 will determine
the ADT7463’s slave address.
14 TACH4 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4. Can be reconfigured as an analog
input (AIN4) to measure the speed of 2-wire fans.
ADDRESS If in address select mode, this pin determines the SMBus device address.
SELECT
THERM Alternatively, the pin may be reconfigured as a bidirectional THERM pin. Can be used to time and monitor
assertions on the THERM input. For example, can be connected to the PROCHOT output of Intel’s Pentium 4
processor or to the output of a trip point temperature sensor. Can be used as an output to signal
overtemperature conditions.
15 D2– Cathode Connection to Second Thermal Diode.
16 D2+ Anode Connection to Second Thermal Diode.
17 D1– Cathode Connection to First Thermal Diode.
18 D1+ Anode Connection to First Thermal Diode.
19 VID4 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
20 +5V
IN
Analog Input. Monitors 5 V power supply.
THERM Alternatively, this pin may be reconfigured as a bidirectional THERM pin. Can be used to time and monitor
assertions on the THERM input. For example, can be connected to the PROCHOT output of Intel’s Pentium 4
processor or to the output of a trip point temperature sensor. Can be used as an output to signal
overtemperature conditions.
21 +12V
IN
Analog Input. Monitors 12 V power supply.
VID5 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
Supports VRM10 solutions.
22 +2.5V
IN
Analog Input. Monitors 2.5 V supply, typically a chipset voltage.
SMBALERT Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to signal
out-of-limit conditions.
23 V
CCP
Analog Input. Monitors processor core voltage (0 V to 3 V).
24 PWM1/ Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩtypical pull-up.
XTO Also functions as the output from the XOR tree in XOR test mode.
www.BDTIC.com/ADI

REV. C–6–
ADT7463
FUNCTIONAL DESCRIPTION
General Description
The ADT7463 is a complete systems monitor and multiple fan
controller for any system requiring monitoring and cooling. The
device communicates with the system via a serial system
management bus. The serial bus controller has an optional
address line for device selection (Pin 14), a serial data line
for reading and writing addresses and data (Pin 1), and an input
line for the serial clock (Pin 2). All control and programming
functions of the ADT7463 are performed over the serial bus. In
addition, two of the pins can be reconfigured as an SMBALERT
output to indicate out-of-limit conditions.
Measurement Inputs
The device has six measurement inputs, four for voltage and
two for temperature. It can also measure its own supply voltage
and can measure ambient temperature with its on-chip tempera-
ture sensor.
Pins 20 through 23 are analog inputs with on-chip attenuators,
configured to monitor 5 V, 12 V, 2.5 V, and the processor core
voltage (2.25 V input), respectively.
Power is supplied to the chip via Pin 4, and the system also
monitors V
CC
through this pin. In PCs, this pin is normally
connected to a 3.3 V standby supply. This pin can, however, be
connected to a 5 V supply and monitor it without overranging.
Remote temperature sensing is provided by the D1⫾and D2⫾
inputs, to which diode-connected, external temperature-sensing
transistors, such as a 2N3904 or CPU thermal diode, may be
connected.
The ADC also accepts input from an on-chip band gap tem-
perature sensor that monitors system ambient temperature.
Sequential Measurement
When the ADT7463 monitoring sequence is started, it cycles
sequentially through the measurement of analog inputs and the
temperature sensors. Measured values from these inputs are
stored in value registers. These can be read out over the serial
bus or can be compared with programmed limits stored in the
limit registers. The results of out-of-limit comparisons are stored
in the status registers, which can be read over the serial bus to
flag out-of-limit conditions.
Processor Voltage ID
Five digital inputs (VID0 to VID5—Pins 5 to 8, 19, and 21) read
the processor voltage ID code and store it in the VID register,
from which it can be read out by the management system over
the serial bus. The VID code monitoring function is compatible
with both VRM9.x and future VRM10 solutions. Additionally,
an SMBALERT can be generated to flag a change in VID code.
ADT7463 Address Selection
Pin 13 is the dual-function PWM3/ADDRESS ENABLE pin.
If Pin 13 is pulled low on power-up, the ADT7463 reads the
state of Pin 14 (TACH4/ADDRESS SELECT/ THERM pin) to
determine the ADT7463’s slave address. If Pin 13 is high on
power-up, then the ADT7463 defaults to the SMBus slave
Address 0x2E. This function is described in more detail later.
INTERNAL REGISTERS OF THE ADT7463
A brief description of the ADT7463’s principal internal registers
is given below. More detailed information on the function of
each register is given in Tables IV to XLII.
Configuration Registers
The configuration registers provide control and configuration of
the ADT7463, including alternate pinout functionality.
Address Pointer Register
This register contains the address that selects one of the other
internal registers. When writing to the ADT7463, the first byte
of data is always a register address, which is written to the
address pointer register.
Status Registers
These registers provide the status of each limit comparison and
are used to signal out-of-limit conditions on the temperature,
voltage, or fan speed channels. If Pin 10 or Pin 22 is con-
figured as SMBALERT, then this pin asserts low whenever a
status bit gets set.
Interrupt Mask Registers
These registers allow each interrupt status event to be masked
when Pin 10 or Pin 22 is configured as an SMBALERT output.
VID Register
The status of the VID0 to VID5 pins of the processor can read
from this register. VID code changes can also generate
SMBALERT interrupts.
Value and Limit Registers
The results of analog voltage inputs, temperature, and fan speed
measurements are stored in these registers, along with their
limit values.
Offset Registers
These registers allow each temperature channel reading to be
offset by a twos complement value written to these registers.
T
MIN
Registers
These registers program the starting temperature for each fan
under automatic fan speed control.
T
RANGE
Registers
These registers program the temperature-to-fan speed control
slope in automatic fan speed control mode for each PWM output.
Operating Point Registers
These registers define the target operating temperatures for each
thermal zone when running under dynamic T
MIN
control. This
function allows the cooling solution to adjust dynamically in
response to measured temperature and system performance.
Enhance Acoustics Registers
These registers allow each PWM output controlling fan to be
tweaked to enhance the system’s acoustics.
www.BDTIC.com/ADI

REV. C
Typical Performance Characteristics–ADT7463
–7–
LEAKAGE RESISTANCE (M⍀)
REMOTE TEMPERATURE ERROR (ⴗC)
15
10
–201.0 3.3 100.0
10.0 30.0
0
–5
–10
–15
5DXP TO GND
DXP TO V
CC
(3.3V)
TPC 1. Remote Temperature Error
vs. Leakage Resistance
TEMPERATURE ( C)
LOCAL TEMPERATURE ERROR ( C)
–3
–40 10 110
60
1
0
–2
–1
3
2
LOW LIMIT
HIGH LIMIT
–3 SIGMA
+3 SIGMA
TPC 4. Local Temperature Error
vs. Actual Temperature
1.9
1.8
1.7
1.6
1.5
1.4
2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
TPC 7. Supply Voltage vs.
Supply Current
DXP TO DXN CAPACITANCE (nF)
REMOTE TEMPERATURE ERROR (ⴗC)
3
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
2.2 3.3 4.7 22.0 47.0
–30
–33
–36
REMOTE TEMPERATURE
ERROR (ⴗC)
1.0 10.0
TPC 2. Remote Temperature Error
vs. Capacitance between D+ and D–
FREQUENCY (Hz)
REMOTE TEMPERATURE ERROR (ⴗC)
14
12
–2
100k 550k 50M
5M
6
4
0
2
10
8
100mV
250mV
TPC 5. Remote Temperature Error
vs. Power Supply Noise Frequency
FREQUENCY (Hz)
REMOTE TEMPERATURE ERROR (ⴗC)
16
60k
14
12
10
8
6
4
2
0
–2
110k 1M 10M 50M
10mV
20mV
TPC 8. Remote Temperature Error vs.
Differential Mode Noise Frequency
TEMPERATURE ( C)
REMOTE TEMPERATURE ERROR ( C)
3
–40
2
1
0
–1
–2
–3 10 60 110
–3 SIGMA
+3 SIGMA
LOW LIMIT
HIGH LIMIT
TPC 3. Remote Temperature Error
vs. Actual Temperature
FREQUENCY (Hz)
LOCAL TEMPERATURE ERROR (ⴗC)
12.5
10.0
–5.0
100k 550k 50M
5M
5.0
2.5
–2.5
0
7.5
100mV
250mV
TPC 6. Local Temperature Error vs.
Power Supply Noise Frequency
FREQUENCY (Hz)
REMOTE TEMPERATURE ERROR (ⴗC)
40
10k
35
30
25
20
15
10
5
0
–5
–10 100k 1M 10M
20mV
40mV
100mV
TPC 9. Remote Temperature Error vs.
Common-Mode Noise Frequency
www.BDTIC.com/ADI

REV. C–8–
ADT7463
TACH2
PWM3
TACH3
D1+
D1–
3.3VSB
5V
12V/VID5
CURRENT
V
CORE
GND
SMBALERT
ADT7463
SCL
SDA
THERM
D2+
D2–
VID[0:4]/VID[0:5]
TACH1
PWM1
ADP316x
VRM
CONTROLLER
FRONT
CHASSIS
FAN
REAR
CHASSIS
FAN
AMBIENT
TEMPERATURE
V
COMP
5(VRM9)/6(VRM10)
PROCHOT
Figure 2. Recommended Implementation
RECOMMENDED IMPLEMENTATION
Configuring the ADT7463 as in Figure 2 allows the systems
designer the following features:
• Six VID inputs (VID0 to VID5) for VRM10 support.
• Two PWM outputs for fan control of up to three fans
(the front and rear chassis fans are connected in parallel).
• Three TACH fan speed measurement inputs.
• V
CC
measured internally through Pin 4.
• CPU core voltage measurement (V
CORE
).
• 2.5 V measurement input used to monitor CPU current
(connected to V
COMP
output of ADP316x VRM controller).
This is used to determine CPU power consumption.
• 5 V measurement input.
• VRM temperature uses local temperature sensor.
• CPU temperature measured using Remote 1 temperature
channel.
• Ambient temperature measured through Remote 2 temperature
channel.
• If not using VID5, this pin can be reconfigured as the 12 V
monitoring input.
• Bidirectional THERM pin. Allows Intel Pentium 4 PROCHOT
monitoring and can function as an overtemperature THERM
output.
• SMBALERT system interrupt output.
See the AN-612 ADT7463 Configuration application note for more
information and register settings for all possible configurations
(www.analog.com/UploadedFiles/Application_Notes/408599520AN612_0.pdf).
www.BDTIC.com/ADI

REV. C
ADT7463
–9–
SERIAL BUS INTERFACE
Control of the ADT7463 is carried out using the serial system
management bus (SMBus). The ADT7463 is connected to this
bus as a slave device, under the control of a master controller.
The ADT7463 has a 7-bit serial bus address. When the device
is powered up with Pin 13 (PWM3/ADDRESS ENABLE) high,
the ADT7463 has a default SMBus address of 0101110 or
0x2E. The read/write bit must be added to get the 8-bit address. If
more than one ADT7463 is used in a system, then each ADT7463
should be placed in address select mode by strapping Pin 13 low on
power-up. The logic state of Pin 14 then determines the device’s
SMBus address. The logic of these pins is sampled upon power-up.
The device address is sampled and latched on the first valid
SMBus transaction, more precisely on the low-to-high transition
at the beginning of the 8th SCL pulse, when the serial bus address
byte matches the selected slave address. The selected slave address
is chosen using the address enable/address select pins. Any
attempted changes in the address will have no effect after this.
Table I. Address Select Mode
Pin 13 State Pin 14 State Address
0Low (10 kΩto GND) 0101100 (0x2C)
0High (10 kΩPull-Up) 0101101 (0x2D)
1Don’t Care 0101110 (0x2E)
(Default)
ADT7463
14
13
ADDR_SEL
PWM3/ADDR_EN
V
CC
10k⍀
ADDRESS = 0x2E
Figure 3. Default SMBus Address = 0x2E
ADT7463
14
13
ADDR_SEL
PWM3/ADDR_EN
10k⍀
ADDRESS = 0x2C
Figure 4. SMBus Address = 0x2C (Pin 14 = 0)
The ability to make hardwired changes to the SMBus slave
address allows the user to avoid conflicts with other devices sharing
the same serial bus, for example, if more than one ADT7463 is
used in a system.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
START condition and shift in the next eight bits, consisting
of a 7-bit address (MSB first) plus a R/Wbit, which deter-
mines the direction of the data transfer, i.e., whether data
will be written to or read from the slave device.
ADT7463
ADDR_SEL
PWM3/ADDR_EN
ADDRESS = 0x2D
14
13
V
CC
10k⍀
Figure 5. SMBus Address = 0x2D (Pin 14 = 1)
ADT7463
14
13
ADDR_SEL
PWM3/ADDR_EN
VCC
10k⍀
DO NOT LEAVE ADDR_EN
UNCONNECTED! CAN
CAUSE UNPREDICTABLE
ADDRESSES.
NC
CARE SHOULD BE TAKEN TO ENSURE THAT PIN 13
(PWM3/ADDR_EN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 13
FLOATING COULD CAUSE THE ADT7463 TO POWER UP WITH AN
UNEXPECTED ADDRESS.
NOTE THAT IF THE ADT7463 IS PLACED INTO ADDRESS SELECT
MODE, PINS 13 AND 14 CANNOT BE USED AS THE ALTERNATE
FUNCTIONS (PWM3, TACH4/THERM) ONLY IF THE CORRECT
CIRCUIT IS MUXED IN AT THE CORRECT TIME.
Figure 6. Unpredictable SMBus Address if Pin 13
Is Unconnected
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowl-
edge Bit. All other devices on the bus now remain idle while
the selected device waits for data to be read from or written
to it. If the R/Wbit is a 0, then the master writes to the
slave device. If the R/Wbit is a 1, the master reads from
the slave device.
www.BDTIC.com/ADI

REV. C–10–
ADT7463
R/W
0
SCL
SDA 10
11A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7463
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
19
1
ACK. BY
ADT7463
9
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7463
STOP BY
MASTER
FRAME 3
DATA
BYTE
19
SCL (CONTINUED)
SDA (CONTINUED)
Figure 7. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected Register
2. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an Acknowledge Bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, as a low-to-high transition
when the clock is high may be interpreted as a STOP signal.
The number of data bytes that can be transmitted over the
serial bus in a single READ or WRITE operation is limited
only by what the master and slave devices can handle.
3. When all data bytes have been read or written, stop conditions
are established. In WRITE mode, the master pulls the data line
high during the tenth clock pulse to assert a STOP condition.
In READ mode, the master device overrides the acknowledge
bit by pulling the data line high during the low period before
the ninth clock pulse. This is known as No Acknowledge.
The master then takes the data line low during the low pe-
riod before the 10th clock pulse, and then high during the
10th clock pulse to assert a STOP condition.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
In the case of the ADT7463, write operations contain either one
or two bytes, and read operations contain one byte and perform
the following functions.
To write data to one of the device data registers or read data from
it, the address pointer register must be set so that the correct data
register is addressed, then data can be written into that register
or read from it. The first byte of a write operation always contains
an address that is stored in the address pointer register. If data
is to be written to the device, then the write operation contains
asecond data byte that is written to the register selected by the
address pointer register.
This is illustrated in Figure 7. The device address is sent over
the bus followed by R/Wbeing set to 0. This is followed by two
data bytes. The first data byte is the address of the internal data
register to be written to, which is stored in the address pointer
register. The second data byte is the data to be written to the
internal data register.
www.BDTIC.com/ADI

REV. C
ADT7463
–11–
When reading data from a register, there are two possibilities:
1. If the ADT7463’s address pointer register value is unknown
or not the desired value, it is first necessary to set it to the
correct value before data can be read from the desired data
register. This is done by performing a write to the ADT7463
as before, however, only the data byte is sent and this con-
tains the register address. This is shown in Figure 8.
A read operation is then performed consisting of the serial
bus address, R/Wbit set to 1, followed by the data byte read
from the data register. This is shown in Figure 9.
2. If the address pointer register is already at the desired address,
data can be read from the corresponding data register without
first writing to the address pointer register, so Figure 8 can
be omitted.
Notes
1. It is possible to read a data byte from a data register without
first writing to the address pointer register if the address
pointer register is already at the correct value. However, it is
not possible to write data to a register without writing to the
address pointer register because the first data byte of a write
is always written to the address pointer register.
2. In Figures 7 to 9, the serial bus address is shown as the
default value 01011(A1)(A0), where A1 and A0 are set by
the address select mode function previously defined.
3. In addition to supporting the Send Byte and Receive Byte
protocols, the ADT7463 also supports the Read Byte protocol
(see System Management Bus specifications Rev. 2.0 for
more information).
4. If it is required to perform several read or write operations in
succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
R/W
0
SCL
SDA 10
11A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7463
STOP BY
MASTER
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
19
1
ACK. BY
ADT7463
9
Figure 8. Writing to the Address Pointer Register Only
R/W
0
SCL
SDA 10
11A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
NO ACK. BY
MASTER
STOP BY
MASTER
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
DATA BYTE FROM ADT7463
19
1
ACK. BY
ADT7463
9
Figure 9. Reading Data from a Previously Selected Register
www.BDTIC.com/ADI

REV. C–12–
ADT7463
ADT7463 WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the ADT7463
are discussed below. The following abbreviations are used in the
diagrams:
S – START
P– STOP
R– READ
W – WRITE
A– ACKNOWLEDGE
A–NO ACKNOWLEDGE
The ADT7463 uses the following SMBus write protocols.
Send Byte
In this operation, the master device sends a single command
byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
For the ADT7463, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This is illustrated in Figure 10.
SSLAVE
ADDRESS WA AP
12 3 4 56
REGISTER
ADDRESS
Figure 10. Setting a Register Address for Subsequent Read
If it is required to read data from the register immediately after
setting up the address, the master can assert a repeat start con-
dition immediately after the final ACK and carry out a single
byte read without asserting an intermediate stop condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA to end the
transaction.
This is illustrated in Figure 11.
SSLAVE
ADDRESS WA
12 3 4 56
ADATA AP
78
REGISTER
ADDRESS
Figure 11. Single Byte Write to a Registe r
ADT7463 READ OPERATIONS
The ADT7463 uses the following SMBus read protocols.
Receive Byte
This is useful when repeatedly reading a single register. The
register address needs to have been set up previously. In this
operation, the master device receives a single byte from a slave
device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA and the trans-
action ends.
In the ADT7463, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation.
SSLAVE
ADDRESS RADATA AP
12 3456
Figure 12. Single Byte Read from a Register
ALERT RESPONSE ADDRESS
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as an interrupt output or
can be used as an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
procedure occurs:
1. SMBALERT is pulled low.
2. Master initiates a read operation and sends the alert response
address (ARA = 0001 100). This is a general call address
that must not be used as a specific device address.
3. The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and it can
be interrogated in the usual way.
4. If more than one device’s SMBALERT output is low, the one
with the lowest device address will have priority in accordance
with normal SMBus arbitration.
5. Once the ADT7463 has responded to the alert response
address, the master must read the status registers and the
SMBALERT will only be cleared if the error condition has
gone away.
SMBUS TIMEOUT
The ADT7463 includes an SMBus timeout feature. If there is
no SMBus activity for 35 ms, the ADT7463 assumes that the bus
is locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it
can be disabled.
CONFIGURATION REGISTER 1 – Register 0x40
<6> TODIS = 0; SMBus Timeout ENABLED (Default)
<6> TODIS = 1; SMBus Timeout DISABLED
www.BDTIC.com/ADI

REV. C
ADT7463
–13–
VOLTAGE MEASUREMENT INPUTS
The ADT7463 has four external voltage measurement channels.
It can also measure its own supply voltage, V
CC
.
Pins 20 to 23 are dedicated to measuring 5 V, 12 V, and 2.5 V
supplies and the processor core voltage V
CCP
(0 V to 3 V input).
The V
CC
supply voltage measurement is carried out through
the V
CC
pin (Pin 4). Setting Bit 7 of Configuration Register 1
(Reg. 0x40) allows a 5 V supply to power the ADT7463 and be
measured without overranging the V
CC
measurement channel.
The 2.5 V input can be used to monitor a chipset supply voltage
in computer systems.
ANALOG-TO-DIGITAL CONVERTER (ADC)
All analog inputs are multiplexed into the on-chip, successive
approximation, ADC. This has a resolution of 10 bits. The basic
input range is 0 V to 2.25 V, but the inputs have built-in attenu-
ators to allow measurement of 2.5 V, 3.3 V, 5 V, 12 V, and the
processor core voltage V
CCP
without any external components. To
allow for the tolerance of these supply voltages, the ADC pro-
duces an output of 3/4 full scale (decimal 768 or 300 hex) for
the nominal input voltage and so has adequate headroom to
cope with overvoltages.
INPUT CIRCUITRY
The internal structure for the analog inputs is shown in Figure 13.
Each input circuit consists of an input protection diode, an
attenuator, plus a capacitor to form a first-order, low-pass filter
that gives the input immunity to high frequency noise.
VOLTAGE MEASUREMENT REGISTERS
Reg. 0x20 2.5 V Reading = 0x00 Default
Reg. 0x21 V
CCP
Reading = 0x00 Default
Reg. 0x22 V
CC
Reading = 0x00 Default
Reg. 0x23 5 V Reading = 0x00 Default
Reg. 0x24 12 V Reading = 0x00 Default
VOLTAGE MEASUREMENT LIMIT REGISTERS
Associated with each voltage measurement channel are high and
low limit registers. Exceeding the programmed high or low limit
causes the appropriate status bit to be set. Exceeding either limit
can also generate SMBALERT interrupts.
Reg. 0x44 2.5 V Low Limit = 0x00 Default
Reg. 0x45 2.5 V High Limit = 0xFF Default
Reg. 0x46 V
CCP
Low Limit = 0x00 Default
Reg. 0x47 V
CCP
High Limit = 0xFF Default
Reg. 0x48 V
CC
Low Limit = 0x00 Default
Reg. 0x49 V
CC
High Limit = 0xFF Default
Reg. 0x4A 5 V Low Limit = 0x00 Default
Reg. 0x4B 5 V High Limit = 0xFF Default
Reg. 0x4C 12 V Low Limit = 0x00 Default
Reg. 0x4D 12 V High Limit = 0xFF Default
30pF
120k⍀
30pF
93k⍀
MUX
30pF
68k⍀
30pF
45k⍀
52.5k⍀35pF
17.5k⍀
94k⍀
71k⍀
47k⍀
20k⍀
12V
IN
5V
IN
3.3V
IN
2.5V
IN
V
CCP
Figure 13. Structure of Analog Inputs
Table II shows the input ranges of the analog inputs and output
codes of the 10-bit ADC.
When the ADC is running, it samples and converts a voltage
input in 711 µs and averages 16 conversions to reduce noise;
ameasurement on each input takes nominally 11.38 ms.
www.BDTIC.com/ADI

REV. C–14–
ADT7463
Table II. 10-Bit A/D Output Code vs. V
IN
Input Voltage A/D Output
+12V
IN
+5V
IN
V
CC
(3.3V
IN
)*+2.5V
IN
+V
CCP
Decimal Binary (10 Bits)
<0.0156 <0.0065 <0.0042 <0.0032 <0.00293 0 00000000 00
0.0156–0.0312 0.0065–0.0130 0.0042–0.0085 0.0032–0.0065 0.0293–0.0058 1 00000000 01
0.0312–0.0469 0.0130–0.0195 0.0085–0.0128 0.0065–0.0097 0.0058–0.0087 2 00000000 10
0.0469–0.0625 0.0195–0.0260 0.0128–0.0171 0.0097–0.0130 0.0087–0.0117 3 00000000 11
0.0625–0.0781 0.0260–0.0325 0.0171–0.0214 0.0130–0.0162 0.0117–0.0146 4 00000001 00
0.0781–0.0937 0.0325–0.0390 0.0214–0.0257 0.0162–0.0195 0.0146–0.0175 5 00000001 01
0.0937–0.1093 0.0390–0.0455 0.0257–0.0300 0.0195–0.0227 0.0175–0.0205 6 00000001 10
0.1093–0.1250 0.0455–0.0521 0.0300–0.0343 0.0227–0.0260 0.0205–0.0234 7 00000001 11
0.1250–0.14060 0.0521–0.0586 0.0343–0.0386 0.0260–0.0292 0.0234–0.0263 8 00000010 00
•
•
•
4.0000–4.0156 1.6675–1.6740 1.1000–1.1042 0.8325–0.8357 0.7500–0.7529 256 (1/4 scale) 01000000 00
•
•
•
8.0000–8.0156 3.3300–3.3415 2.2000–2.2042 1.6650–1.6682 1.5000–1.5029 512 (1/2 scale) 10000000 00
•
•
•
12.0000–12.0156 5.0025–5.0090 3.3000–3.3042 2.4975–2.5007 2.2500–2.2529 768 (3/4 scale) 11000000 00
•
•
•
15.8281–15.8437 6.5983–6.6048 4.3527–4.3570 3.2942–3.2974 2.9677–2.9707 1013 11111101 01
15.8437–15.8593 6.6048–6.6113 4.3570–4.3613 3.2974–3.3007 2.9707–2.9736 1014 11111101 10
15.8593–15.8750 6.6113–6.6178 4.3613–4.3656 3.3007–3.3039 2.9736–2.9765 1015 11111101 11
15.8750–15.8906 6.6178–6.6244 4.3656–4.3699 3.3039–3.3072 2.9765–2.9794 1016 11111110 00
15.8906–15.9062 6.6244–6.6309 4.3699–4.3742 3.3072–3.3104 2.9794–2.9824 1017 11111110 01
15.9062–15.9218 6.6309–6.6374 4.3742–4.3785 3.3104–3.3137 2.9824–2.9853 1018 11111110 10
15.9218–15.9375 6.6374–6.4390 4.3785–4.3828 3.3137–3.3169 2.9853–2.9882 1019 11111110 11
15.9375–15.9531 6.6439–6.6504 4.3828–4.3871 3.3169–3.3202 2.9882–2.9912 1020 11111111 00
15.9531–15.9687 6.6504–6.6569 4.3871–4.3914 3.3202–3.3234 2.9912–2.9941 1021 11111111 01
15.9687–15.9843 6.6569–6.6634 4.3914–4.3957 3.3234–3.3267 2.9941–2.9970 1022 11111111 10
>15.9843 >6.6634 >4.3957 >3.3267 >2.9970 1023 11111111 11
*The V
CC
output codes listed assume that V
CC
is 3.3 V. If V
CC
input is reconfigured for 5 V operation (by setting Bit 7 of Configuration Register 1), then the V
CC
output codes are the same as for the +5V
IN
column.
www.BDTIC.com/ADI

REV. C
ADT7463
–15–
VID CODE MONITORING
The ADT7463 has five dedicated voltage ID (VID code) inputs.
These are digital inputs that can be read back through the
VID register (Reg. 0x43) to determine the processor voltage
required/being used in the system. Five VID code inputs support
VRM9.x solutions. In addition, Pin 21 (12 V input) can be recon-
figured as a sixth VID input to satisfy future VRM requirements.
VID CODE REGISTER – Register 0x43
<0> = VID0 (reflects logic state of Pin 5)
<1> = VID1 (reflects logic state of Pin 6)
<2> = VID2 (reflects logic state of Pin 7)
<3> = VID3 (reflects logic state of Pin 8)
<4> = VID4 (reflects logic state of Pin 19)
<5> = VID5 (reconfigurable 12 V input). This bit reads 0 when
Pin 21 is configured as the 12 V input. This bit reflects the logic
state of Pin 21 when the pin is configured as VID5.
VID CODE INPUT THRESHOLD VOLTAGE
The switching threshold for the VID code inputs is approximately
1 V. To enable future compatibility, it is possible to reduce the
VID code input threshold to 0.6 V. Bit 6 (THLD) of VID register
(Reg. 0x43) controls the VID input threshold voltage.
VID CODE REGISTER – Register 0x43
<6> THLD = 0; VID Switching Threshold = 1 V,
V
OL
< 0.8 V, V
IH
> 1.7 V, V
MAX
= 3.3 V
THLD = 1; VID Switching Threshold = 0.6 V,
V
OL
< 0.4 V, V
IH
> 0.8 V, V
MAX
= 3.3 V
RECONFIGURING PIN 21 (+12V/VID5) AS VID5 INPUT
Pin 21 can be reconfigured as a sixth VID code input (VID5)
for VRM10-compatible systems. Since the pin is configured as
VID5, it is no longer possible to monitor a 12 V supply.
Bit 7 of the VID register (Reg. 0x43) determines the function of
Pin 21. System or BIOS software can read the state of Bit 7 to
determine whether the system is designed to monitor 12 V or is
monitoring a sixth VID input.
VID CODE REGISTER – Register 0x43
<7> VIDSEL = 0; Pin 21 functions as a 12 V measurement
input. Software can read this bit to determine that there are five
VID inputs being monitored. Bit 5 of Register 0x43 (VID5)
always reads back 0. Bit 0 of Status Register 2 (Reg. 0x42)
reflects 12 V out-of-limit measurements.
VIDSEL = 1; Pin 21 functions as the sixth VID code input
(VID5). Software can read this bit to determine that there are
six VID inputs being monitored. Bit 5 of Register 0x43 reflects
the logic state of Pin 21. Bit 0 of Status Register 2 (Reg. 0x42)
reflects VID code changes.
VID CODE CHANGE DETECT FUNCTION
The ADT7463 has a VID code change detect function. When
Pin 21 is configured as the VID5 input, VID code changes can
be detected and reported back by the ADT7463. Bit 0 of Status
Register 2 (Reg. 0x42) is the 12V/VC bit and denotes a VID
change when set. The VID code change bit gets set when the
logic states on the VID inputs are different than they were 11 µs
previously. The change of VID code can be used to generate
an SMBALERT interrupt. If an SMBALERT interrupt is
not required, Bit 0 of Interrupt Mask Register 2 (Reg. 0x75),
when set, prevents SMBALERTs from occurring on VID code
changes.
STATUS REGISTER 2 – Register 0x42
<0> 12V/VC = 0; If Pin 21 is configured as VID5, then a
Logic 0 denotes no change in VID code within last 11 µs.
<0> 12V/VC = 1; If Pin 21 is configured as VID5, then a Logic 1
means that a change has occurred on the VID code inputs within
the last 11 µs. An SMBALERT generates if this function is en-
abled.
ADDITIONAL ADC FUNCTIONS
A number of other functions are available on the ADT7463 to
offer the systems designer increased flexibility, including:
Turn-Off Averaging
For each voltage measurement read from a value register,
16 readings have actually been made internally and the results
averaged before being placed into the value register. There may
be an instance where you would like to speed up conversions.
Setting Bit 4 of Configuration Register 2 (Reg. 0x73) turns
averaging off. This effectively gives a reading 16 times faster
(711 µs), but the reading may be noisier.
Bypass Voltage Input Attenuators
Setting Bit 5 of Configuration Register 2 (Reg 0x73) removes
the attenuation circuitry from the 2.5 V, V
CCP
, V
CC
, 5 V, and
12 V inputs. This allows the user to directly connect external
sensors or rescale the analog voltage measurement inputs for
other applications. The input range of the ADC without the
attenuators is 0 V to 2.25 V.
Single-Channel ADC Conversion
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7463 into single-channel ADC conversion mode. In this mode,
the ADT7463 can be made to read a single voltage channel
only. If the internal ADT7463 clock is used, the selected input
is read every 711 µs. The appropriate ADC channel is selected
by writing to Bits <7:5> of the TACH1 Minimum High Byte
Register (0x55).
Bits <7:5> Channel
Reg 0x55 Selected
000 2.5 V
001 V
CCP
010 V
CC
011 5 V
100 12 V
Configuration Register 2 (Reg. 0x73)
<4> = 1 Averaging Off
<5> = 1 Bypass Input Attenuators
<6> = 1 Single-Channel Convert Mode
TACH1 Minimum High Byte (Reg. 0x55)
<7:5> Selects ADC Channel for Single-Channel Convert Mode
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REV. C–16–
ADT7463
D+
D–
REMOTE
SENSING
TRANSISTOR
INⴛI I
BIAS
V
DD
V
OUT+
TO ADC
V
OUT–
BIAS
DIODE LOW-PASS
FILTER
f
C
= 65kHz
THERMDA
THERMDC
CPU
Figure 14. Signal Conditioning for Remote Diode Temperature Sensors
TEMPERATURE MEASUREMENT SYSTEM
Local Temperature Measurement
The ADT7463 contains an on-chip band gap temperature sensor
whose output is digitized by the on-chip 10-bit ADC. The 8-bit
MSB temperature data is stored in the local temperature register
(Address 26h). As both positive and negative temperatures can be
measured, the temperature data is stored in twos complement
format, as shown in Table III. Theoretically, the temperature sensor
and ADC can measure temperatures from –128⬚C to +127⬚C
with a resolution of 0.25⬚C. However, this exceeds the operating
temperature range of the device, so local temperature measure-
ments outside this range are not possible.
Remote Temperature Measurement
The ADT7463 can measure the temperature of two remote diode
sensors or diode-connected transistors connected to Pins 15 and
16, or 17 and 18.
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about –2 mV/⬚C. Unfortunately, the absolute
value of V
BE
varies from device to device and individual calibra-
tion is required to null this out, so the technique is unsuitable
for mass production. The technique used in the ADT7463 is to
measure the change in V
BE
when the device is operated at two
different currents.
This is given by
∆VKTq N
BE =×ln( )
where:
Kis Boltzmann’s constant.
qis the charge on the carrier.
Tis the absolute temperature in Kelvins.
Nis the ratio of the two currents.
Figure 14 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows the
external sensor as a substrate transistor, provided for temperature
monitoring on some microprocessors. It could equally well be a
discrete transistor, such as a 2N3904.
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ADT7463
–17–
If a discrete transistor is used, the collector will not be grounded
and should be linked to the base. If a PNP transistor is used, the
base is connected to the D– input and the emitter to the D+
input. If an NPN transistor is used, the emitter is connected to
the D– input and the base to the D+ input. Figures 15a and 15b
show how to connect the ADT7463 to an NPN or PNP transis-
tor for temperature measurement. To prevent ground noise from
interfering with the measurement, the more negative terminal of
the sensor is not referenced to ground but is biased above ground
by an internal diode at the D– input.
To measure ∆V
BE
, the sensor is switched between operating currents
of I and N ⴛI. The resulting waveform is passed through a
65 kHz low-pass filter to remove noise and to a chopper-stabilized
amplifier that performs the functions of amplification and recti-
fication of the waveform to produce a dc voltage proportional to
∆V
BE
. This voltage is measured by the ADC to give a tempera-
ture output in 10-bit, twos complement format. To further reduce
the effects of noise, digital filtering is performed by averaging
the results of 16 measurement cycles. A remote temperature
measurement takes nominally 25.5 ms. The results of remote
temperature measurements are stored in 10-bit, twos complement
format, as illustrated in Table III. The extra resolution for the
temperature measurements is held in the Extended Resolution
Register 2 (Reg. 0x77). This gives temperature readings with a
resolution of 0.25⬚C.
Table III. Temperature Data Format
Temperature Digital Output (10-Bit)*
–128⬚C1000 0000 00
–125⬚C1000 0011 00
–100⬚C1001 1100 00
–75⬚C1011 0101 00
–50⬚C1100 1110 00
–25⬚C1110 0111 00
–10⬚C1111 0110 00
0⬚C0000 0000 00
+10.25⬚C0000 1010 01
+25.5⬚C0001 1001 10
+50.75⬚C0011 0010 11
+75⬚C0100 1011 00
+100⬚C0110 0100 00
+125⬚C0111 1101 00
+127⬚C0111 1111 00
*Bold denotes 2 LSBs of measurement in Extended
Resolution Register 2 (Reg. 0x77) with 0.25⬚C resolution.
ADT7463
2N3904
NPN D+
D–
Figure 15a. Measuring Temperature Using an
NPN Transistor
2N3906
PNP
ADT7463
D+
D–
Figure 15b. Measuring Temperature Using a PNP
Transistor
Nulling Out Temperature Errors
As CPUs run faster, it is getting more difficult to avoid high
frequency clocks when routing the D+, D– traces around a
sys
tem board. Even when recommended layout guidelines are
followed, there may still be temperature errors attributed to
noise being coupled onto the D+/D– lines. High frequency noise
generally has the effect of giving temperature measurements that are
too high by a constant amount. The ADT7463 has temperature
offset registers at Addresses 0x70, 0x72 for the Remote 1 and
Remote 2 temperature channels. By doing a one-time calibration
of the system, one can determine the offset caused by system
board noise and null it out using the offset registers. The offset
registers automatically add a twos complement 8-bit reading to
every temperature measurement. The LSBs add 0.25°C offset to
the temperature reading so the 8-bit register effectively allows
temperature offsets of up to ⫾32
⬚ C with a resolution of 0.25 ⬚ C.
This ensures that the readings in the temperature measurement
registers are as accurate as possible.
Temperature Offset Registers
Reg. 0x70 Remote 1 Temperature Offset = 0x00 (0°C Default)
Reg. 0x71 Local Temperature Offset = 0x00 (0°C Default)
Reg. 0x72 Remote 2 Temperature Offset = 0x00 (0°C Default)
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REV. C–18–
ADT7463
Temperature Measurement Registers
Reg. 0x25 Remote 1 Temperature = 0x80 Default
Reg. 0x26 Local Temperature = 0x80 Default
Reg. 0x27 Remote 2 Temperature = 0x80 Default
Reg. 0x77 Extended Resolution 2 = 0x00 Default
<7:6> TDM2 = Remote 2 Temperature LSBs
<5:4> LTMP = Local Temperature LSBs
<3:2> TDM1 = Remote 1 Temperature LSBs
Temperature Measurement Limit Registers
Associated with each temperature measurement channel are
high and low limit registers. Exceeding the programmed high or
low limit causes the appropriate status bit to be set. Exceeding
either limit can also generate SMBALERT interrupts.
Reg. 0x4E Remote 1 Temp Low Limit = 0x81 Default
Reg. 0x4F Remote 1 Temp High Limit = 0x7F Default
Reg. 0x50 Local Temp Low Limit = 0x81 Default
Reg. 0x51 Local Temp High Limit = 0x7F Default
Reg. 0x52 Remote 2 Temp Low Limit = 0x81 Default
Reg. 0x53 Remote 2 Temp High Limit = 0x7F Default
Reading Temperature from the ADT7463
It is important to note that temperature can be read from the
ADT7463 as an 8-bit value (with 1°C resolution) or as a 10-bit
value (with 0.25°C resolution). If only 1°C resolution is required,
the temperature readings can be read back at any time and in no
particular order.
If the 10-bit measurement is required, this involves a 2-register
read for each measurement. The extended resolution register
(Reg. 0x77) should be read first. This causes all temperature
reading registers to be frozen until all temperature reading regis-
ters have been read from. This prevents an MSB reading from
being updated while its 2 LSBs are being read and vice versa.
ADDITIONAL ADC FUNCTIONS
A number of other functions are available on the ADT7463 to
offer the systems designer increased flexibility.
Turn-Off Averaging
For each temperature measurement read from a value register,
16 readings have actually been made internally and the results
averaged before being placed into the value register. Sometimes
it may be necessary to take a very fast measurement, e.g., of CPU
temperature. Setting Bit 4 of Configuration Register 2 (Reg. 0x73)
turns averaging off. This takes a reading every 13 ms. The mea-
surement itself takes 4 ms.
Single-Channel ADC Conversions
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7463 into single-channel ADC conversion mode. In this
mode, the ADT7463 can be made to read a single temperature
channel only. If the internal ADT7463 clock is used, the
selected input is read every 1.4 ms. The appropriate ADC chan-
nel is selected by writing to Bits <7:5> of TACH1 Minimum
High Byte Register (0x55).
Bits <7:5> Reg 0x55 Channel Selected
101 Remote 1 Temperature
110 Local Temperature
111 Remote 2 Temperature
Configuration Register 2 (Reg. 0x73)
<4> = 1 Averaging Off
<6> = 1 Single-Channel Convert Mode
TACH1 Minimum High Byte (Reg. 0x55)
<7:5> Selects ADC Channel for Single-Channel Convert Mode
Overtemperature Events
Overtemperature events on any of the temperature channels can
be detected and dealt with automatically in automatic fan speed
control mode. Registers 0x6A to 0x6C are the THERM limits.
When a temperature exceeds its THERM limit, all fans run at
100% duty cycle. The fans stay running at 100% until the
temperature drops below THERM – Hysteresis (this can be
disabled by setting the boost bit in Configuration Register 3,
Bit 2, Register 0x78). The hysteresis value for that THERM
limit is the value programmed into Registers 0x6D, 0x6E
(hysteresis registers). The default hysteresis value is 4°C.
FANS
T
HERM LIMIT
TEMPERATURE
100%
HYSTERESIS (ⴗC)
Figure 16. THERM Limit Operation
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REV. C
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LIMITS, STATUS REGISTERS, AND INTERRUPTS
Limit Values
Associated with each measurement channel on the ADT7463
are high and low limits. These can form the basis of system
status monitoring: a status bit can be set for any out-of-limit
condition and detected by polling the device. Alternatively,
SMBALERT interrupts can be generated to flag a processor or
microcontroller of out-of-limit conditions.
8-Bit Limits
The following is a list of 8-bit limits on the ADT7463.
Voltage Limit Registers
Reg. 0x44 2.5 V Low Limit = 0x00 Default
Reg. 0x45 2.5 V High Limit = 0xFF Default
Reg. 0x46 V
CCP
Low Limit = 0x00 Default
Reg. 0x47 V
CCP
High Limit = 0xFF Default
Reg. 0x48 V
CC
Low Limit = 0x00 Default
Reg. 0x49 V
CC
High Limit = 0xFF Default
Reg. 0x4A 5 V Low Limit = 0x00 Default
Reg. 0x4B 5 V High Limit = 0xFF Default
Reg. 0x4C 12 V Low Limit = 0x00 Default
Reg. 0x4D 12 V High Limit = 0xFF Default
Temperature Limit Registers
Reg. 0x4E Remote 1 Temp Low Limit = 0x81 Default
Reg. 0x4F Remote 1 Temp High Limit = 0x7F Default
Reg. 0x6A Remote 1 THERMTHERM
THERMTHERM
THERM Limit = 0x64 Default
Reg. 0x50 Local Temp Low Limit = 0x81 Default
Reg. 0x51 Local Temp High Limit = 0x7F Default
Reg. 0x6B Local THERMTHERM
THERMTHERM
THERM Limit = 0x64 Default
Reg. 0x52 Remote 2 Temp Low Limit = 0x81 Default
Reg. 0x53 Remote 2 Temp High Limit = 0x7F Default
Reg. 0x6C Remote 2 THERMTHERM
THERMTHERM
THERM Limit = 0x64 Default
THERM Limit Register
Reg. 0x7A THERMTHERM
THERMTHERM
THERM Limit = 0x00 Default
16-Bit Limits
The fan TACH measurements are 16-bit results. The fan TACH
limits are also 16 bits, consisting of a high byte and low byte.
Since fans running under speed or stalled are normally the only
conditions of interest, only high limits exist for fan TACHs. Since
fan TACH period is actually being measured, exceeding the limit
indicates a slow or stalled fan.
Fan Limit Registers
Reg. 0x54 TACH1 Minimum Low Byte = 0xFF Default
Reg. 0x55 TACH1 Minimum High Byte = 0xFF Default
Reg. 0x56 TACH2 Minimum Low Byte = 0xFF Default
Reg. 0x57 TACH2 Minimum High Byte = 0xFF Default
Reg. 0x58 TACH3 Minimum Low Byte = 0xFF Default
Reg. 0x59 TACH3 Minimum High Byte = 0xFF Default
Reg. 0x5A TACH4 Minimum Low Byte = 0xFF Default
Reg. 0x5B TACH4 Minimum High Byte = 0xFF Default
Out-of-Limit Comparisons
Once all limits are programmed, the ADT7463 can be enabled
for monitoring. The ADT7463 measures all parameters in
round-robin format and sets the appropriate status bit for out-
of-limit conditions. Comparisons are done differently depending
on whether the measured value is being compared to a high or
low limit.
HIGH LIMIT: > COMPARISON PERFORMED
LOW LIMIT: < OR = COMPARISON PERFORMED
NO INT
LOW LIMIT
TEMP >
LOW LIMIT
Figure 17. Temperature > Low Limit: No INT
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REV. C–20–
ADT7463
INT
LOW LIMIT
TEMP =
LOW LIMIT
Figure 18. Temperature = Low Limit: INT Occurs
NO INT
HIGH LIMIT
TEMP =
HIGH LIMIT
21.00C
Figure 19. Temperature = High Limit: No INT
HIGH LIMIT
INT
TEMP >
HIGH LIMIT
Figure 20. Temperature > High Limit: INT Occurs
Analog Monitoring Cycle Time
The analog monitoring cycle begins when a 1 is written to the
start bit (Bit 0) of Configuration Register 1 (Reg. 0x40). The ADC
measures each analog input in turn and as each measurement is
completed, the result is automatically stored in the appropriate
value register. This round-robin monitoring cycle continues
unless disabled by writing a 0 to Bit 0 of Configuration Register 1.
Because the ADC is normally left to free-run in this manner, the
time taken to monitor all the analog inputs is normally not of
interest, since the most recently measured value of any input
can be read out at any time.
For applications where the monitoring cycle time is important,
it is easily calculated.
The total number of channels measured is:
•Four dedicated supply voltage inputs
•3.3 V
STBY
or 5 V supply (V
CC
pin)
•Local temperature
•Two remote temperatures
As mentioned previously, the ADC performs round-robin
conversions and takes 11.38 ms for each voltage measurement,
12 ms for a local temperature reading, and 25.5 ms for each remote
temperature reading.
The total monitoring cycle time for averaged voltage and tempera-
ture monitoring is therefore nominally
51138 122255120×
()
++×
()
=..ms
Fan TACH measurements are made in parallel and are not
synchronized with the analog measurements in any way.
Status Registers
The results of limit comparisons are stored in Status Registers 1
and 2. The status register bit for each channel reflects the status
of the last measurement and limit comparison on that channel.
If a measurement is within limits, the corresponding status register
bit is cleared to 0. If the measurement is out-of-limits, the corre-
sponding status register bit is set to 1.
The state of the various measurement channels may be polled
by reading the status registers over the serial bus. In Bit 7 (OOL)
of Status Register 1 (Reg. 0x41), 1 means that an out-of-limit
event has been flagged in Status Register 2. This means that a
user need only read Status Register 2 when this bit is set. Alter-
natively, Pin 10 or Pin 22 can be configured as an SMBALERT
output. This automatically notifies the system supervisor of an
out-of-limit condition. Reading the status registers clears the
appropriate status bit as long as the error condition that caused
the interrupt has cleared. Status register bits are “sticky.” When-
ever a status bit gets set, indicating an out-of-limit condition,
it remains set even if the event that caused it has gone away
(until read). The only way to clear the status bit is to read the
status register after the event has gone away. Interrupt status
mask registers (Reg. 0x74, 0x75) allow individual interrupt
sources to be masked from causing an SMBALERT. However,
if one of these masked interrupt sources goes out-of-limit, its
associated status bit gets set in the interrupt status registers.
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