Analog Devices dBCool ADT7468 User manual

dB Cool
®
Remote Thermal
Controller and Voltage Monitor
ADT7468
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.
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Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Monitors up to 5 voltages
Controls and monitors up to 4 fans
High and low frequency fan drive signal
1 on-chip and 2 remote temperature sensors
Series resistance cancellation on the remote channel
Extended temperature measurement range, up to 191°C
Dynamic TMIN control mode intelligently optimizes system
acoustics
Automatic fan speed control mode manages system
cooling based on measured temperature
Enhanced acoustic mode dramatically reduces user
perception of changing fan speeds
Thermal protection feature via THERM output
Monitors performance impact of Intel® Pentium®4 processor
Thermal control circuit via THERM input
2-wire, 3-wire, and 4-wire fan speed measurement
Limit comparison of all monitored values
Meets SMBus 2.0 electrical specifications
(fully SMBus 1.1-compliant)
GENERAL DESCRIPTION
The ADT7468 dBCool controller is a thermal monitor and
multiple PWM fan controller for noise sensitive or power
sensitive applications requiring active system cooling. The
ADT7468 can drive a fan using either a low or high frequency
drive signal, monitor the temperature of up to two remote
sensor diodes plus its own internal temperature, and measure
and control the speed of up to four fans, so that they operate at
the lowest possible speed for minimum acoustic noise.
The automatic fan speed control loop optimizes fan speed for a
given temperature. A unique, dynamic TMIN control mode
enables the system thermals/acoustics to be intelligently
managed. The effectiveness of the system’s thermal solution can
be monitored using the THERM input. The ADT7468 also
provides critical thermal protection to the system using the
bidirectional THERM pin as an output to prevent system or
component overheating.
FUNCTIONAL BLOCK DIAGRAM
04499-0-001
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
GND
SERIAL BUS
INTERFACE
SCL SDA
VALUE AND
LIMIT
REGISTERS
LIMIT
COMPARATORS
INTERRUPT
STATUS
REGISTERS
BAND GAP
TEMP SENSOR
V
CC
TOADT7468
ADDRESS
POINTER
REGISTER
PWM
CONFIGURATION
REGISTERS
INTERRUPT
MASKING
V
CC
D1+
D1–
D2+
D2–
+5V
IN
THERMAL
PROTECTION
PERFORMANCE
MONITORING
PWM REGISTERS
AND
CONTROLLERS
HF & LF
PWM1
PWM2
PWM3
ACOUSTIC
ENHANCEMENT
CONTROL
BAND GAP
REFERENCE
10-BIT
ADC
ADT7468
AUTOMATIC
FAN SPEED
CONTROL
DYNAMIC
T
MIN
CONTROL
FAN SPEED
COUNTER
TACH1
TACH2
TACH3
TACH4
ACOUSTIC
ENHANCEMENT
CONTROL
SRC
+12V
IN
+2.5V
IN
V
CCP
VID5
VID4
VID3
VID2
VID1
VID0
THERM
SMBALERT
Figure 1.
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ADT7468
Rev. A | Page 2 of 84
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 8
Product Description....................................................................... 10
Comparison between ADT7463 and ADT7468..................... 10
Recommended Implementation............................................... 11
Serial Bus Interface......................................................................... 12
Write Operations ........................................................................ 13
Read Operations ......................................................................... 14
SMBus Timeout .......................................................................... 14
VID Code Monitoring ................................................................... 15
VID Code Registers.................................................................... 15
Analog-to-Digital Converter ........................................................ 16
Voltage Measurement Input...................................................... 16
Additional ADC Functions for Voltage Measurements ........ 16
Temperature Measurement ....................................................... 18
Additional ADC Functions for
Temperature Measurement ....................................................... 21
Limits, Status Registers, and Interrupts....................................... 22
Limit Values................................................................................. 22
Status Registers ........................................................................... 23
Interrupts..................................................................................... 23
Active Cooling ................................................................................ 28
Driving the Fan Using PWM Control ..................................... 28
Laying Out 2-Wire and 3-Wire Fans ....................................... 30
Fan Speed Measurement............................................................ 31
Fan Spin-Up ................................................................................ 33
PWM Logic State........................................................................ 34
Fan Speed Control...................................................................... 34
Miscellaneous Functions ............................................................... 35
Operating from 3.3 V Standby ................................................. 35
XNOR Tree Test Mode .............................................................. 35
Power-On Default ...................................................................... 35
Automatic Fan Control Overview................................................ 37
Dynamic TMIN Control Mode ................................................... 38
Programming the Automatic Fan Speed Control Loop ............ 40
Step 1: Hardware Configuration .............................................. 40
Step 2: Configuring the Mux .................................................... 43
Step 3: TMIN Settings for Thermal Calibration Channels ...... 45
Step 4: PWMMIN for Each PWM (Fan) Output ...................... 46
Step 5: PWMMAX for PWM (Fan) Outputs.............................. 46
Step 6: TRANGE for Temperature Channels................................ 47
Step 7: TTHERM for Temperature Channels ............................... 50
Step 8: THYST for Temperature Channels.................................. 51
Step 9: Operating Points for Temperature Channels............. 52
Step 10: High and Low Limits for Temperature Channels ... 53
Step 11: Monitoring THERM ................................................... 56
Step 12: Ramp Rate for Acoustic Enhancement..................... 57
Enhancing System Acoustics ........................................................ 60
Acoustic Enhancement Mode Overview ................................ 60
Register Tables ................................................................................ 62
ADT7468 Programming Block Diagram .................................... 81
Outline Dimensions ....................................................................... 82
Ordering Guide .......................................................................... 82
REVISION HISTORY
7/05—Rev. 0 to Rev. A
Changes to Absolute Maximum Ratings................................... 5
Changes to Table 17.................................................................... 62
Changes to Ordering Guide ...................................................... 80
4/04—Revision 0: Initial Version

ADT7468
Rev. A | Page 3 of 84
SPECIFICATIONS
TA= TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.
All voltages are measured with respect to GND, unless otherwise specified. Typicals are at TA= 25°C and represent most likely parametric
norms. Logic inputs accept input high voltages up to VMAX even when device is operating down to VMIN. Timing specifications are tested at
logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge. SMBus timing specifications are guaranteed by design and
are not production tested.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Supply Voltage 3.0 3.3 5.5 V
Supply Current, ICC 3 mA Interface inactive, ADC active
20 μA Standby mode
TEMP-TO-DIGITAL CONVERTER
Local Sensor Accuracy ±1.5 °C 0°C ≤ TA≤ 70°C
−3.5 +2 °C −40°C ≤ TA≤ +100°C
−4 +2 °C −40°C ≤ TA≤ +120°C
Resolution 0.25 °C
Remote Diode Sensor Accuracy ±1.5 °C 0°C ≤ TA≤ 70°C; 0°C ≤ TD≤ 120°C
−3.5 +2 °C −40°C ≤ TA≤ +100°C; 0°C ≤ TD ≤ +120°C
−4.5 +2 °C −40°C ≤ TA≤ +120°C; 0°C ≤ TD≤ +120°C
Resolution 0.25 °C
Remote Sensor Source Current 6 μA First current
36 μΑ Second current
96 μΑ Third current
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error (TUE) ±2 % For 12 V and 5 V channels
±1.5 % For all other channels
Differential Nonlinearity (DNL) ±1 LSB 8 bits
Power Supply Sensitivity ±0.1 %/V
Conversion Time (Voltage Input) 11 ms Averaging enabled
Conversion Time (Local Temperature) 12 ms Averaging enabled
Conversion Time (Remote Temperature) 38 ms Averaging enabled
Total Monitoring Cycle Time 145 ms Averaging enabled
Total Monitoring Cycle Time 19 ms Averaging disabled
Input Resistance 40 70 100 kΩ For VCC channel
80 140 200 kΩ For all other channels
FAN RPM-TO-DIGITAL CONVERTER
Accuracy ±5 % 0°C ≤ TA≤ 70°C , 3.3 V
±7 % −40°C ≤ TA≤ +120°C , 3.3 V
±10 % −40°C ≤ TA≤ +120°C , 5.5 V
Full-Scale Count 65,535
Nominal Input RPM 109 RPM Fan count = 0xBFFF
329 RPM Fan count = 0x3FFF
5000 RPM Fan count = 0x0438
10000 RPM Fan count = 0x021C
Internal Clock Frequency 85.5 90 94.5 kHz 0°C ≤ TA≤ 70°C, VCC = 3.3 V
83.7 90 96.3 kHz −40°C ≤ TA≤ +120°C, VCC = 3.3 V
81 90 99 kHz −40°C ≤ TA≤ +120°C, VCC = 5.5 V

ADT7468
Rev. A | Page 4 of 84
Parameter Min Typ Max Unit Test Conditions/Comments
OPEN-DRAIN DIGITAL OUTPUTS,
PWM1 TO PWM3, XTO
Current Sink, IOL 8.0 mA
Output Low Voltage, VOL 0.4 V IOUT = −8.0 mA, VCC = +3.3 V
High Level Output Current, IOH 0.1 1.0 μA VOUT = VCC
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL 0.4 V IOUT = −4.0 mA, VCC = +3.3 V
High Level Output Current, IOH 0.1 1.0 μA VOUT = VCC
SMBUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.4 V
Hysteresis 500 mV
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH 2.0 V
5.5 V Maximum input voltage
Input Low Voltage, VIL 0.8 V
−0.3 V Minimum input voltage
Hysteresis 0.5 V p-p
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH 0.75 × VCCP V
Input Low Voltage, VIL 0.4 V
DIGITAL INPUT CURRENT
Input High Current, IIH −1 μA VIN = VCC
Input Low Current, IIL 1 μA VIN = 0
Input Capacitance, CIN 5 pF
SERIAL BUS TIMING See Figure 2
Clock Frequency, fSCLK 10 400 kHz
Glitch Immunity, tSW 50 ns
Bus Free Time, tBUF 4.7 μs
Start Setup Time, tSU;STA 4.7 μs
Start Hold Time, tHD;STA 4.0 μs
SCL Low Time, tLOW 4.7 μs
SCL High Time, tHIGH 4.0 50 μs
SCL, SDA Rise Time, tR1000 ns
SCL, SDA Fall Time, tF300 μs
Data Setup Time, tSU;DAT 250 ns
Data Hold Time, tHD;DAT 300 ns
Detect Clock Low Timeout, tTIMEOUT 15 35 ms Can be optionally disabled
SCL
SD
A
PS SP
t
BUF
t
HD; STA
t
HD; DAT
t
SU; DAT
t
F
t
R
t
LOW
t
SU; STA
t
HIGH
t
HD; STA
t
SU; STO
04499-0-002
Figure 2. Serial Bus Timing Diagram

ADT7468
Rev. A | Page 5 of 84
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Positive Supply Voltage (VCC) 5.5 V
Maximum Voltage on 12 VIN Pin 20 V
Voltage on Any Input or Output Pin −0.3 V to +6.5 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJMAX) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering
IR Reflow Peak Temperature 220°C
For Pb-free 260°C
Lead Temperature (Soldering 10 sec) 300°C
ESD Rating 1000 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Thermal Characteristics
24-lead QSOP package:
θJA = 150°C/W
θJC = 39°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

ADT7468
Rev. A | Page 6 of 84
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04499-0-003
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
VID0
VID1
VID2
VID3
TACH1
TACH2
+5V
IN
/THERM
VID4
D1+
TACH3
PWM2/SMBALERT
D1–
1
2
3
4
24
23
22
21
SDA
SCL
GND
V
CC
PWM1/XTO
V
CCP
+2.5V
IN
+12V
IN
/VID5
D2+
D2–
PWM3
TACH4/GPIO/THERM/SMBALERT
ADT7468
TOP VIEW
(NOT TO SCALE)
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin
No. Mnemonic Description
1 SDA Digital I/O (Open Drain). SMBus bidirectional serial data. Requires pull-up resistor.
2 SCL Digital Input (Open Drain). SMBus serial clock input. Requires pull-up resistor.
3 GND Ground Pin.
4 VCC Power Supply. Can be powered by 3.3 V standby, if monitoring in low power states is required. VCC is also monitored
through this pin. The ADT7468 can also be powered from a 5 V supply. Setting Bit 7 of Configuration Register 1
(Reg. 0x40) rescales the VCC input attenuators to correctly measure a 5 V supply.
5 VID0 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
6 VID1 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
7 VID2 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
8 VID3 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
9 TACH3 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3. Can be reconfigured as an analog input
(AIN3) to measure the speed of 2-wire fans.
10 PWM2 Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse width modulated output to control Fan 2 speed.
Can be configured as a high or low frequency drive.
SMBALERT Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit
conditions.
11 TACH1 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1. Can be reconfigured as an analog input
(AIN1) to measure the speed of 2-wire fans.
12 TACH2 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. Can be reconfigured as an analog input
(AIN2) to measure the speed of 2-wire fans.
13 PWM3 Digital I/O (Open Drain). Pulse width modulated output to control speed of Fan 3 and Fan 4. Requires 10 kΩ typical
pull-up. Can be configured as a high or low frequency drive.
14 TACH4 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4. Can be reconfigured as an analog input
(AIN4) to measure the speed of 2-wire fans.
GPIO General Purpose Open Drain Digital I/O.
THERM Alternatively, the pin can be reconfigured as a bidirectional THERM pin. Can be used to time and monitor assertions
on the THERM input. For example, this pin can be connected to the PROCHOT output of an Intel Pentium 4 processor
or to the output of a trip point temperature sensor. This pin can also be used as an output to signal overtemperature
conditions.
SMBALERT Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit
conditions.
15 D2– Cathode Connection to Second Thermal Diode.
16 D2+ Anode Connection to Second Thermal Diode.
17 D1– Cathode Connection to First Thermal Diode.

ADT7468
Rev. A | Page 7 of 84
Pin
No. Mnemonic Description
18 D1+ Anode Connection to First Thermal Diode.
19 VID4 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
20 +5VIN Analog Input. Monitors +5 V power supply.
THERM Alternatively, this pin can be reconfigured as a bidirectional THERM pin. Can be used to time and monitor assertions
on the THERM input. For example, it can be connected to the PROCHOT output of an Intel Pentium 4 processor or to
the output of a trip point temperature sensor. This pin can also be used as an output to signal overtemperature
conditions.
21 +12VIN Analog Input. Monitors +12 V power supply.
VID5 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
Supports VRM10 solutions.
22 +2.5VIN Analog Input. Monitors +2.5 V supply, typically a chipset voltage.
23 VCCP Analog Input. Monitors processor core voltage (0 V to 3 V).
24 PWM1 Digital Output (Open Drain). Pulse width modulated output to control Fan 1 speed. Requires 10 kΩ typical pull-up.
XTO Also functions as the output from the XOR tree in XOR test mode.

ADT7468
Rev. A | Page 8 of 84
TYPICAL PERFORMANCE CHARACTERISTICS
04499-0-045
CAPACITANCE (nF)
1 4.73.3 100 2.2
TEMPERATURE ERROR (°C)
–60
0
–20
–50
–30
–10
–40
Figure 4. Temperature Error vs. Capacitance between D+ and D−
04499-0-046
CAPACITANCE (nF) 2501020515
TEMPERATURE ERROR (°C)
–100
0
–20
–50
–30
–60
–70
–80
–90
–10
–40
Figure 5. External Temperature Error vs. D+/D− Capacitance
04499-0-047
RESISTANCE (MΩ)1000 3.3 20110
TEMPERATURE ERROR (°C)
–80
60
20
–40
0
–60
40
–20
D+ TO GND
D+ TO VCC
Figure 6. Remote Temperature Error vs. PCB Resistance
04499-0-048
FREQUENCY (kHz) 1G10 100 1M 10M 100M
TEMPERATURE ERROR (°C)
–10
20
15
0
10
–5
5
100mV
40mV
60mV
Figure 7. Remote Temperature Error vs. Common Mode Noise Frequency
04499-0-049
FREQUENCY (kHz) 1G10 100 1M 10M 100M
TEMPERATURE ERROR (°C)
–4
6
4
–2
2
–3
0
5
–1
3
1
10mV
20mV
Figure 8. Remote Temperature Error vs. Differential Mode Noise Frequency
04499-0-050
POWER SUPPLY VOLTAGE (V)
3.0 3.8 5.23.4 4.43.6 4.83.2 4.0 5.44.6 5.04.2
I
DD
(mA)
1.05
1.40
1.30
1.20
1.15
1.10
1.35
1.25
Figure 9. Normal IDD vs. Power Supply

ADT7468
Rev. A | Page 9 of 84
04499-0-051
POWER SUPPLY VOLTAGE (V)
3.0 3.8 5.23.4 4.43.6 4.83.2 4.0 5.44.6 5.04.2
I
DD
(μA)
0
7
5
3
2
1
6
4
Figure 10. Shutdown IDD vs. Power Supply
04499-0-052
POWER SUPPLY NOISE FREQUENCY (kHz) 1G10 100 1M 10M 100M
TEMPERATURE ERROR (°C)
–20
20
10
–5
5
–10
–15
15
0
INT ERROR, 100mV
INT ERROR, 250mV
Figure 11. Internal Temperature Error vs. Power Supply
04499-0-053
POWER SUPPLY NOISE FREQUENCY (kHz) 1G10 100 1M 10M 100M
TEMPERATURE ERROR (°C)
–20
20
10
–5
5
–10
–15
15
0
EXT ERROR, 100mV
EXT ERROR, 250mV
Figure 12. Remote Temperature Error vs. Power Supply Noise Frequency
04499-0-091
TEMPERATURE (°C) 120–40 –20 0 20 40 60 80 100
ERROR (°C)
1.0
0
0.5
–1.0
–0.5
–2.0
–1.5
–2.5
–3.5
–3.0
–4.0
Figure 13. Internal Temperature Error vs. ADT7468 Temperature
04499-0-092
TEMPERATURE (°C) 120–40 –20 0 20 40 60 80 100
ERROR (°C)
1.0
0
0.5
–1.0
–0.5
–2.0
–1.5
–2.5
–3.5
–3.0
–4.0
Figure 14. Remote Temperature Error vs. ADT7468 Temperature

ADT7468
Rev. A | Page 10 of 84
PRODUCT DESCRIPTION
The ADT7468 is a complete thermal monitor and multiple fan
controller for any system requiring thermal monitoring and
cooling. The device communicates with the system via a serial
system management bus. The serial bus controller has a serial
data line for reading and writing addresses and data (Pin 1), and
an input line for the serial clock (Pin 2). All control and
programming functions for the ADT7468 are performed over
the serial bus. In addition, a pin can be reconfigured as an
SMBALERT output to signal out-of-limit conditions.
COMPARISON BETWEEN ADT7463 AND ADT7468
The ADT7468 is an upgrade to the ADT7463. The ADT7468
and ADT7463 are almost pin and register map compatible. The
ADT7468 and ADT7463 have the following differences:
1. On the ADT7468, the PWM drive signals can be config-
ured as either high frequency or low frequency drives. The
low frequency option is programmable between 10 Hz and
100 Hz. The high frequency option is 22.5 kHz. On the
ADT7463, only the low frequency option is available.
2. Once VCC is powered up, monitoring of temperature and
fan speeds is enabled on the ADT7468 when VCCP is
powered up. If VCCP is never powered up, this is enabled
when the first SMBus transaction with the ADT7468 is
completed. On the ADT7463, the STRT bit in Configur-
ation Register 1 must be set to enable monitoring.
3. The fans are switched off by default upon power-up. On
the ADT7463, the fans run at full speed on power-up.
Fail-safe cooling is provided such that when the measured
temperature exceeds the THERM limit (100°C), the fans
run at full speed.
Fail-safe cooling is also provided 4.6 secs after VCCP is
powered-up (see Figure 48). The fans operate at full speed
if the ADT7468 has not been addressed via the SMBus
within 4.6 secs of when the VCCP is powered up. This
protects the system in the event that the SMBus fails. The
ADT7468 can be programmed at any time, and it behaves
as programmed. If VCCP is never powered-up, fail-safe
cooling is effectively disabled. If VCCP is disabled, writing to
the ADT7468 at any time causes the ADT7468 to operate
normally.
4. Series resistance cancellation (SRC) is provided on the
remote temperature channels on the ADT7468, but not on
the ADT7463. SRC automatically cancels linear offset
introduced by a series resistance between the thermal
diode and the sensor.
5. The ADT7468 has an extended temperature measurement
range. The measurement range goes from–64°C to +191°C.
On the ADT7463, the measurement range is from −127°C
to +127°C. This means that the ADT7468 can measure
higher temperatures. The ADT7468 also includes the
ADT7463 temperature range; the temperature measure-
ment range can be switched by setting Bit 0 of
Configuration Register 5.
6. The ADT7468 maximum fan speed (% duty cycle) in the
automatic fan speed control loop can be programmed. The
maximum fan speed is 100% duty cycle on the ADT7463
and is not programmable.
7. The offset register in the ADT7468 is programmable up
to ±64°C with 0.50°C resolution. The offset register of
the ADT7463 is programmable up to ±32°C with
0.25°C resolution.
8. VCCP is monitored on Pin 23 of the ADT7468 and can be
used to set the threshold for THERM (PROCHOT) (2/3 of
VCCP). The threshold for THERM (PROCHOT) is set at
VIH = 1.7 V and VIL = 0.8 V on the ADT7463.
9. On the ADT7463, Pin 22 can be reconfigured as SMBus
ALERT. This is not available on the ADT7468; instead,
SMBALERT can be enabled on Pin 14.
10. A GPIO can also be made available on Pin 14 on the
ADT7468. This is not available on the ADT7463. Set the
GPIO polarity and direction in Configuration Register 5.
The GPIO status bit is Bit 5 of Status Register 2 (shared
with TACH4 and THERM, because only one can be
enabled at a time).
11. The ADT7463 has three possible SMBus addresses, which
are selectable using the address select and address enable
pins. The ADT7468 has one SMBus address available at
Address 0x2E.
Due to the inclusion of extra functionality, the register map has
changed, including an additional configuration register:
Configuration Register 5 at Address 0x7C.
Configuration Register 5
Bit 0: If Bit 0 is set to 1, in terms of temperature the ADT7468 is
backward-compatible with the ADT7463. Measurements
including the TMIN calibration circuit, and fan control work in
the range of −127°C to +127°C. Also, care should be taken in
reprogramming the temperature limits (TMIN, operating point,
and THERM limits) to their desired twos complement value,
because the power-on default for them is at Offset 64. The
extended temperature range is −64°C to 191°C. The default is 1,
which is in the −64°C to +191°C temperature range.
Bit 1= 0 is the high frequency (22.5 kHz) fan drive signal.

ADT7468
Rev. A | Page 11 of 84
Bit 1 = 1 switches the fan drive to low frequency PWM,
programmable between 10 Hz and 100 Hz, the same as the
ADT7463. The default = 0 = HF PWM.
Bit 2 sets the direction for the GPIO: 0 = input, 1 = output.
Bit 3 sets the GPIO polarity: 0 = active low, 1 = active high.
Setting the Functionality of Pin 14
Pin 14 on the ADT7468 has four possible functions:
SMBALERT, THERM, GPIO, and TACH4. The user chooses
the required functionality by setting Bit 0 and Bit 1 of
Configuration Register 4 at Address 0x7D.
Table 4. Pin 14 Settings
Bit 0 Bit 1 Function
0 0 TACH4
0 1 THERM
1 0 SMBALERT
1 1 GPIO
RECOMMENDED IMPLEMENTATION
Configuring the ADT7468 as in Figure 15 allows the system
designer to use the following features:
•Two PWM outputs for fan control of up to three fans (the
front and rear chassis fans are connected in parallel).
•Three TACH fan speed measurement inputs.
•VCC measured internally through Pin 3.
•CPU temperature measured using Remote 1 temperature
channel.
•Ambient temperature measured through Remote 2
temperature channel.
•Bidirectional THERM pin. This feature allows Intel
Pentium 4 PROCHOT monitoring and can function as an
overtemperature THERM output. Alternatively, it can be
programmed as an SMBALERT system interrupt output.
TACH2
PWM3
TACH3
D1+
D1–
3.3VSB
5V
12V/VID5
CURRENT
V
CORE
GND
ADT7468
SCL
SDA
D2+
D2–
TACH1
VID[0:4]/VID[0:5]
PWM1
AMBIENT
TEMPERATURE
SMBALERT
THERM
04499-0-004
FRONT
CHASSIS
FAN
REAR
CHASSIS
FAN
5(VRM9)/6(VRM10)
ADP316x
VRM
CONTROLLER
V
COMP
PROCHOT
CPU FAN
CPU
ICH
Figure 15. ADT7468 Configuration

ADT7468
Rev. A | Page 12 of 84
SERIAL BUS INTERFACE
On PCs and servers, control of the ADT7468 is carried out
using the serial system management bus (SMBus). The
ADT7468 is connected to this bus as a slave device, under the
control of a master controller, which is usually (but not
necessarily) the ICH.
The ADT7468 has a fixed 7-bit serial bus address of 0101110 or
0x2E. The read/write bit must be added to get the 8-bit address
(01011100 or 0x5C). Data is sent over the serial bus in
sequences of nine clock pulses: eight bits of data followed by an
acknowledge bit from the slave device. Transitions on the data
line must occur during the low period of the clock signal and
remain stable during the high period, because a low-to-high
transition might be interpreted as a stop signal when the clock
is high. The number of data bytes that can be transmitted over
the serial bus in a single read or write operation is limited only
by what the master and slave devices can handle.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition. In
read mode, the master device overrides the acknowledge bit by
pulling the data line high during the low period before the
ninth clock pulse. This is known as a no acknowledge. The
master then takes the data line low during the low period before
the 10th clock pulse, and then high during the 10th clock pulse
to assert a stop condition.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
In the ADT7468, write operations contain either one or two
bytes, and read operations contain one byte and perform the
following functions. To write data to one of the device data
registers or read data from it, the address pointer register must
be set so that the correct data register is addressed, then data
can be written into that register or read from it. The first byte of
a write operation always contains an address that is stored in the
address pointer register. If data is to be written to the device,
then the write operation contains a second data byte that is
written to the register selected by the address pointer register.
This write operation is illustrated in Figure 16. The device
address is sent over the bus, and then R/Wis set to 0. This is
followed by two data bytes. The first data byte is the address of
the internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to be
written to the internal data register.
When reading data from a register, there are two possibilities:
•If the ADT7468’s address pointer register value is unknown
or not the desired value, it must be set to the correct value
before data can be read from the desired data register. This
is done by performing a write to the ADT7468, but only
the data byte containing the register address is sent, since
no data is written to the register. This is shown in
Figure 17.
A read operation is then performed consisting of the serial
bus address, R/W, bit set to 1, followed by the data byte
read from the data register. This is shown in Figure 18.
•If the address pointer register is known to be at the desired
address, data can be read from the corresponding data
register without first writing to the address pointer register,
as shown in Figure 18
R/W
0
SCL
SDA 101110D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7468
START BY
MASTER
19
1
ACK. BY
ADT7468
9
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7468 STOP BY
MASTER
19
SCL (CONTINUED)
SDA (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
04499-0-005
Figure 16. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

ADT7468
Rev. A | Page 13 of 84
R/W
0
SCL
SDA 101110D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7468 STOP BY MASTER
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE
119
ACK. BY
ADT7468
9
04499-0-006
Figure 17. Writing to the Address Pointer Register Only
R/W
0
SCL
S
D
A
101110D7 D6 D5 D4 D3 D2 D1 D0
NO ACK. BY
MASTER STOP BY MASTER
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS BYTE FRAME 2 DATA BYTE FROM ADT7468
119
ACK. BY
ADT7468
9
04499-0-007
Figure 18. Reading Data from a Previously Selected Register
It is possible to read a data byte from a data register without
first writing to the address pointer register, if the address
pointer register is already at the correct value. However, it is not
possible to write data to a register without writing to the
address pointer register, because the first data byte of a write is
always written to the address pointer register.
In addition to supporting the send byte and receive byte
protocols, the ADT7468 also supports the read byte protocol.
(See Intel’s System Management Bus Specifications Rev. 2 for
more information.)
If several read or write operations must be performed in
succession, the master can send a repeat start condition instead
of a stop condition to begin a new operation.
WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the
ADT7468 are discussed below. The following abbreviations are
used in the diagrams:
S: START
P: STOP
R: READ
W: WRITE
A: ACKNOWLEDGE
A: NO ACKNOWLEDGE
The ADT7468 uses the following SMBus write protocols.
Send Byte
In this operation, the master device sends a single command
byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
For the ADT7468, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This operation is illustrated in Figure 19.
SLAVE
ADDRESS WASA
REGISTER
ADDRESS
23154
04499-0-008
P
6
Figure 19. Setting a Register Address for a Subsequent Read
If the master is required to read data from the register
immediately after setting up the address, it can assert a repeat
start condition immediately after the final ACK and carry out a
single byte read without asserting an intermediate stop
condition.

ADT7468
Rev. A | Page 14 of 84
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA to end the
transaction.
This operation is illustrated in Figure 20.
SLAVE
ADDRESS SLAVE ADDRESS DATAAAWS
246531
04499-0-009
AP
78
Figure 20. Single Byte Write to a Register
READ OPERATIONS
The ADT7468 uses the following SMBus read protocols.
Receive Byte
This operation is useful when repeatedly reading a single
register. The register address must have been set up previously.
In this operation, the master device receives a single byte from a
slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
In the ADT7468, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation. This operation
is illustrated in Figure 21.
SLAVE
ADDRESS
SRAAPDATA
21354
04499-0-010
6
Figure 21. Single Byte Read from a Register
Alert Response Address
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as either an interrupt
output or an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
procedure occurs:
1. SMBALERT is pulled low.
2. The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
3. The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and can
be interrogated in the usual way.
4. If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority in accor-
dance with normal SMBus arbitration.
5. Once the ADT7468 has responded to the alert response
address, the master must read the status registers and the
SMBALERT is cleared only if the error condition is absent.
SMBUS TIMEOUT
The ADT7468 includes an SMBus timeout feature. If there is no
SMBus activity for 35 ms, the ADT7468 assumes that the bus is
locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it can
be disabled.
Configuration Register 1 (Reg. 0x40)
<6> TODIS = 0, SMBus timeout enabled (default).
<6> TODIS = 1, SMBus timeout disabled.

ADT7468
Rev. A | Page 15 of 84
VID CODE MONITORING
The ADT7468 has five dedicated voltage ID (VID code)
inputs. These are digital inputs that can be read back through
the VID register (Reg. 0x43) to determine the processor voltage
required or being used in the system. Five VID code inputs
support VRM9.x solutions. In addition, Pin 21 (12 V input)
can be reconfigured as a sixth VID input to satisfy future
VRM requirements.
VID CODE REGISTERS
VID Code Register 0x43
<0> = VID0, reflects the logic state of Pin 5.
<1> = VID1, reflects the logic state of Pin 6.
<2> = VID2, reflects the logic state of Pin 7.
<3> = VID3, reflects the logic state of Pin 8.
<4> = VID4, reflects the logic state of Pin 19.
<5> = VID5, reconfigurable 12 V input. This bit reads 0 when
Pin 21 is configured as the 12 V input. This bit reflects the logic
state of Pin 21 when the pin is configured as VID5.
<6> THLD = 0, VID switching threshold = 1 V,
VOL < 0.8 V, VIH > 1.7 V, VMAX = 3.3 V
THLD = 1, VID switching threshold = 0.6 V,
VOL < 0.4 V, VIH > 0.8 V, VMAX = 3.3 V
<7> VIDSEL = 0, Pin 21 functions as a 12 V measurement
input. Software can read this bit to determine that there are five
VID inputs being monitored. Bit 5 of Register 0x43 (VID5)
always reads back 0. Bit 0 of Status Register 2 (Reg. 0x42)
reflects 12 V out-of-limit measurements.
VIDSEL = 1, Pin 21 functions as the sixth VID code input
(VID5). Software can read this bit to determine that there are
six VID inputs being monitored. Bit 5 of Register 0x43 reflects
the logic state of Pin 21. Bit 0 of Status Register 2 (Reg. 0x42)
reflects VID code changes.
VID Code Input Threshold Voltage
The switching threshold for the VID code inputs is approxi-
mately 1 V. To enable future compatibility, it is possible to
reduce the VID code input threshold to 0.6 V. Bit 6 (THLD)
of the VID register (Reg. 0x43) controls the VID input
threshold voltage.
Reconfiguring Pin 21 as VID5 Input
Pin 21 can be reconfigured as a sixth VID code input (VID5)
for VRM10-compatible systems. Because the pin is configured
as VID5, it is not possible to monitor a 12 V supply.
Bit 7 of the VID register (Reg. 0x43) determines the function of
Pin 21. System or BIOS software can read the state of Bit 7 to
determine whether the system is designed to monitor 12 V or is
monitoring a sixth VID input.
Status Register 2 (Reg. 0x42
<0> 12 V/VC = 0, if Pin 21 is configured as VID5, then Logic 0
denotes no change in VID code within the last 11 μs.
<0> 12 V/VC = 1, if Pin 21 is configured as VID5, then Logic 1
means that a change has occurred on the VID code inputs
within the last 11 μs. An SMBALERT is generated, if this
function is enabled.
VID Code Change Detect Function
The ADT7468 has a VID code change detect function. When
Pin 21 is configured as the VID5 input, VID code changes can
be detected and reported back by the ADT7468. Bit 0 of Status
Register 2 (Reg. 0x42) is the 12 V/VC bit and denotes a VID
change when set. The VID code change bit is set when the logic
states on the VID inputs are different than they were 11 μs
previously. The change of VID code can be used to generate an
SMBALERT interrupt. If an SMBALERT interrupt is not
required, Bit 0 of Interrupt Mask Register 2 (Reg. 0x75),
when set, prevents SMBALERTs from occurring on VID
code changes.

ADT7468
Rev. A | Page 16 of 84
ANALOG-TO-DIGITAL CONVERTER
All analog inputs are multiplexed into the on-chip, successive
approximation, analog-to-digital converter, which has a resolu-
tion of 10 bits. The basic input range is 0 V to 2.25 V, but the
inputs have built-in attenuators to allow measurement of 2.5 V,
3.3 V, 5 V, 12 V, and the processor core voltage VCCP without any
external components. To allow for the tolerance of these supply
voltages, the ADC produces an output of 3/4 full scale (decimal
768 or 300 hex) for the nominal input voltage and therefore has
adequate headroom to cope with overvoltages.
VOLTAGE MEASUREMENT INPUT
The ADT7468 has four external voltage measurement channels
and can measure its own supply voltage, VCC. Pins 20 to 23 can
measure 5 V, 12 V, 2.5 V supplies, and the processor core voltage
VCCP (0 V to 3 V input). The VCC supply voltage measurement is
carried out through the VCC pin (Pin 4). Setting Bit 7 of Config-
uration Register 1 (Reg. 0x40) allows a 5 V supply to power the
ADT7468 and be measured without overranging the VCC
measurement channel. The 2.5 V input can be used to monitor
a chipset supply voltage in computer systems.
Input Circuitry
The internal structure for the analog inputs is shown in
Figure 22. The input circuit consists of an input protection
diode, an attenuator, and a capacitor to form a first-order low-
pass filter that gives input immunity to high frequency noise.
V
CCP
17.5kΩ
52.5kΩ35pF
2.5V
IN
45kΩ
94kΩ30pF
3.3V
IN
68kΩ
71kΩ30pF
5V
IN
93kΩ
47kΩ30pF
12V
IN
120kΩ
20kΩ30pF
04499-0-011
MUX
Figure 22. Structure of Analog Inputs
Voltage Measurement Registers
Reg. 0x20, 2.5 V reading = 0x00 default
Reg. 0x21, VCCP reading = 0x00 default
Reg. 0x22, VCC reading = 0x00 default
Reg. 0x23, 5 V reading = 0x00 default
Reg. 0x24, 12 V reading = 0x00 default
Voltage Limit Registers
Associated with each voltage measurement channel is a high
and low limit register. Exceeding the programmed high or low
limit causes the appropriate status bit to be set. Exceeding either
limit can also generate SMBALERT interrupts.
Reg. 0x44, 2.5 V low limit = 0x00 default
Reg. 0x45, 2.5 V high limit = 0xFF default
Reg. 0x46, VCCP low limit = 0x00 default
Reg. 0x47, VCCP high limit = 0xFF default
Reg. 0x48, VCC low limit = 0x00 default
Reg. 0x49, VCC high limit = 0xFF default
Reg. 0x4A, 5 V low limit = 0x00 default
Reg. 0x4B, 5 V high limit = 0xFF default
Reg. 0x4C, 12 V Low Limit = 0x00 default
Reg. 0x4D, 12 V High Limit = 0xFF default
Table 6 shows the input ranges of the analog inputs and output
codes of the 10-bit ADC.
When the ADC is running, it samples and converts a voltage
input in 0.7 ms and averages 16 conversions to reduce noise; a
measurement takes nominally 11 ms.
ADDITIONAL ADC FUNCTIONS FOR VOLTAGE
MEASUREMENTS
A number of other functions are available on the ADT7468 to
offer the system designer increased flexibility.
Turn-Off Averaging
For each voltage measurement read from a value register,
16 readings have actually been made internally and the results
averaged before being placed into the value register. For
instance, where faster conversions are needed, setting Bit 4 of
Configuration Register 2 (Reg. 0x73) turns averaging off. This
effectively gives a reading 16 times faster (0.7 ms), but the
reading may be noisier.
Bypass Voltage Input Attenuator
Setting Bit 5 of Configuration Register 2 (Reg. 0x73) removes
the attenuation circuitry from the 2.5 V, VCCP, VCC, 5 V, and 12
V inputs, which allows the user to directly connect external
sensors or rescale the analog voltage measurement inputs for
other applications. The input range of the ADC without the
attenuators is 0 V to 2.25 V.

ADT7468
Rev. A | Page 17 of 84
Single-Channel ADC Conversion
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7468 into single-channel ADC conversion mode. In this
mode, the ADT7468 can be made to read a single voltage
channel only. If the internal ADT7468 clock is used, the selected
input is read every 0.7 ms. The appropriate ADC channel is
selected by writing to Bits <7:5> of the TACH1 minimum high
byte register (0x55).
Configuration Register 2 (Reg. 0x73)
<4> = 1, averaging off.
<5> = 1, bypass input attenuators.
<6> = 1, single-channel convert mode.
TACH1 Minimum High Byte (Reg. 0x55)
<7:5> Selects ADC channel for single-channel convert mode.
Table 5. Programming the Single Channel ADC Function
Bits <7:5> Reg. 0x55 Channel Selected
000 2.5 V
001 VCCP
010 VCC
011 5 V
100 12 V
101 Remote 1 temperature
110 Local temperature
111 Remote 2 temperature
Table 6. 10-Bit A/D Output Code vs. VIN
Input Voltage A/D Output
12 VIN 5 VIN VCC (3.3 VIN)12.5 VIN VCCP Decimal Binary (10 Bits)
<0.0156 <0.0065 <0.0042 <0.0032 <0.00293 0 00000000 00
0.0156–0.0312 0.0065–0.0130 0.0042–0.0085 0.0032–0.0065 0.0293–0.0058 1 00000000 01
0.0312–0.0469 0.0130–0.0195 0.0085–0.0128 0.0065–0.0097 0.0058–0.0087 2 00000000 10
0.0469–0.0625 0.0195–0.0260 0.0128–0.0171 0.0097–0.0130 0.0087–0.0117 3 00000000 11
0.0625–0.0781 0.0260–0.0325 0.0171–0.0214 0.0130–0.0162 0.0117–0.0146 4 00000001 00
0.0781–0.0937 0.0325–0.0390 0.0214–0.0257 0.0162–0.0195 0.0146–0.0175 5 00000001 01
0.0937–0.1093 0.0390–0.0455 0.0257–0.0300 0.0195–0.0227 0.0175–0.0205 6 00000001 10
0.1093–0.1250 0.0455–0.0521 0.0300–0.0343 0.0227–0.0260 0.0205–0.0234 7 00000001 11
0.1250–0.1406 0.0521–0.0586 0.0343–0.0386 0.0260–0.0292 0.0234–0.0263 8 00000010 00
•
•
•
4.0000–4.0156 1.6675–1.6740 1.1000–1.1042 0.8325–0.8357 0.7500–0.7529 256 (1/4 scale) 01000000 00
•
•
•
8.0000–8.0156 3.3300–3.3415 2.2000–2.2042 1.6650–1.6682 1.5000–1.5029 512 (1/2 scale) 10000000 00
•
•
•
12.0000–12.0156 5.0025–5.0090 3.3000–3.3042 2.4975–2.5007 2.2500–2.2529 768 (3/4 scale) 11000000 00
•
•
•
15.8281–15.8437 6.5983–6.6048 4.3527–4.3570 3.2942–3.2974 2.9677–2.9707 1013 11111101 01
15.8437–15.8593 6.6048–6.6113 4.3570–4.3613 3.2974–3.3007 2.9707–2.9736 1014 11111101 10
15.8593–15.8750 6.6113–6.6178 4.3613–4.3656 3.3007–3.3039 2.9736–2.9765 1015 11111101 11
15.8750–15.8906 6.6178–6.6244 4.3656–4.3699 3.3039–3.3072 2.9765–2.9794 1016 11111110 00
15.8906–15.9062 6.6244–6.6309 4.3699–4.3742 3.3072–3.3104 2.9794–2.9824 1017 11111110 01
15.9062–15.9218 6.6309–6.6374 4.3742–4.3785 3.3104–3.3137 2.9824–2.9853 1018 11111110 10
15.9218–15.9375 6.6374–6.4390 4.3785–4.3828 3.3137–3.3169 2.9853–2.9882 1019 11111110 11
15.9375–15.9531 6.6439–6.6504 4.3828–4.3871 3.3169–3.3202 2.9882–2.9912 1020 11111111 00
15.9531–15.9687 6.6504–6.6569 4.3871–4.3914 3.3202–3.3234 2.9912–2.9941 1021 11111111 01
15.9687–15.9843 6.6569–6.6634 4.3914–4.3957 3.3234–3.3267 2.9941–2.9970 1022 11111111 10
>15.9843 >6.6634 >4.3957 >3.3267 >2.9970 1023 11111111 11
1The VCC output codes listed assume that VCC is 3.3 V. If VCC input is reconfigured for 5 V operation (by setting Bit 7 of Configuration Register 1), then the VCC output
codes are the same as for the 5 VIN column.

ADT7468
Rev. A | Page 18 of 84
TEMPERATURE MEASUREMENT
A simple method of measuring temperature is to exploit the
negative temperature coefficient of a diode, measuring the base-
emitter voltage (VBE) of a transistor, operated at constant
current. Unfortunately, this technique requires calibration to
null the effect of the absolute value of VBE, which varies from
device to device.
The technique used in the ADT7468 is to measure the change
in VBE when the device is operated at three currents. Previous
devices have used only two operating currents, but the use of a
third current allows automatic cancellation of resistances in
series with the external temperature sensor.
Figure 24 shows the input signal conditioning used to measure
the output of an external temperature sensor. This figure shows
the external sensor as a substrate transistor, but it could equally
be a discrete transistor. If a discrete transistor is used, the
collector is not grounded and should be linked to the base. To
prevent ground noise from interfering with the measurement,
the more negative terminal of the sensor is not referenced to
ground, but is biased above ground by an internal diode at the
D− input. C1 can optionally be added as a noise filter (the
recommended maximum value is 1000 pF). However, a better
option in noisy environments is to add a filter, as described in
the Noise Filtering section.
Local Temperature Measurement
The ADT7468 contains an on-chip band gap temperature
sensor whose output is digitized by the on-chip 10-bit ADC.
The 8-bit MSB temperature data is stored in the local tempera-
ture register (Address 0x26). Because both positive and negative
temperatures can be measured, the temperature data is stored in
Offset 64 format or twos complement format, as shown in
Table 7 and Table 8. Theoretically, the temperature sensor and
ADC can measure temperatures from −128°C to +127°C (or
−61°C to +191°C in the extended temperature range) with a
resolution of 0.25°C. However, this exceeds the operating
temperature range of the device, so local temperature
measurements outside the ADT7468 operating temperature
range are not possible.
Remote Temperature Measurement
The ADT7468 can measure the temperature of two remote
diode sensors or diode-connected transistors connected to
Pins 17 and 18, or Pins 15 and 16.
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about –2 mV/°C. Unfortunately, the absolute
value of VBE varies from device to device and individual
calibration is required, and therefore the technique is unsuitable
for mass production. The technique used in the ADT7468 is to
measure the change in VBE when the device is operated at three
currents.
This is given by
(
) NnqKTVBE 1/
×
=
Δ
where:
Kis Boltzmann’s constant.
qis the charge on the carrier.
Tis the absolute temperature in Kelvin.
Nis the ratio of the two currents.
Figure 23 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows
the external sensor as a substrate transistor, provided for
temperature monitoring on some microprocessors. It could also
be a discrete transistor such as a 2N3904/2N3906.
N2 × IIN1×II
BIAS
D+
D– LPF
V
DD
V
OUT+
V
OUT–
f
C
= 65kHz
TO ADC
04499-0-012
REMOTE
SENSING
TRANSISTOR
Figure 23. Signal Conditioning for Remote Diode Temperature Sensors
If a discrete transistor is used, the collector is not grounded and
should be linked to the base. If a PNP transistor is used, the
base is connected to the D– input and the emitter is connected
to the D+ input. If an NPN transistor is used, the emitter is
connected to the D– input and the base to the D+ input. Figure
25 and Figure 26 show how to connect the ADT7468 to an NPN
or PNP transistor for temperature measurement. To prevent
ground noise from interfering with the measurement, the more
negative terminal of the sensor is not referenced to ground, but
is biased above ground by an internal diode at the D– input.
To measu re ΔV BE, the operating current through the sensor is
switched among three related currents. Shown in Figure 23,
N1 × I and N2 × I are different multiples of the current I. The
currents through the temperature diode are switched between
I and N1 × I, giving ΔVBE1, and then between I and N2 × I,
giving ΔVBE2. The temperature can then be calculated using
the two ΔVBE measurements. This method can also cancel the
effect of any series resistance on the temperature measurement.
The resulting ΔVBE waveforms are passed through a 65 kHz
low-pass filter to remove noise and then sent to a chopper-
stabilized amplifier that amplifies and rectifies the waveform to
produce a dc voltage proportional to ΔVBE. The ADC digitizes
this voltage, and a temperature measurement is produced. To
reduce the effects of noise, digital filtering is performed by
averaging the results of 16 measurement cycles.

ADT7468
Rev. A | Page 19 of 84
The results of remote temperature measurements are stored in
10-bit, twos complement format, as illustrated in Table 7. The
extra resolution for the temperature measurements is held in
the Extended Resolution Register 2 (Reg. 0x77). This gives
temperature readings with a resolution of 0.25°C.
Noise Filtering
For temperature sensors operating in noisy environments,
previous practice was to place a capacitor across the D+ and D−
pins to decrease the effects of noise. However, large capacitances
affect the accuracy of the temperature measurement, leading to a
recommended maximum capacitor value of 1000 pF. A capacitor
of this value reduces the noise, but does not eliminate it, making
use of the sensor difficult in a very noisy environment.
The ADT7468 has a major advantage over other devices for
eliminating the effects of noise on the external sensor. Using the
series resistance cancellation feature, a filter can be constructed
between the external temperature sensor and the part. The effect
of any filter resistance seen in series with the remote sensor is
automatically canceled from the temperature result.
The construction of a filter allows the ADT7468 and the remote
temperature sensor to operate in noisy environments. Figure 24
shows a low-pass R-C-R filter, with the following values:
R= 100 Ω, C= 1 nF.
This filtering reduces both common-mode noise and
differential noise.
04499-0-093
D+
1nF
100Ω
REMOTE
T
EMPERATURE
SENSOR D–
100Ω
Figure 24. Filter Between Remote Sensor and ADT7468
Series Resistance Cancellation
Parasitic resistance to the ADT7468 D+ and D− inputs (seen in
series with the remote diode) is caused by a variety of factors,
including PCB track resistance and track length. This series
resistance appears as a temperature offset in the remote sensor’s
temperature measurement. This error typically causes a
0.5°C offset per Ω of parasitic resistance in series with the
remote diode.
The ADT7468 automatically cancels out the effect of this series
resistance on the temperature reading, giving a more accurate
result, without the need for user characterization of this
resistance. The ADT7468 is designed to automatically cancel,
typically, up to 3 kΩ of resistance. By using an advanced
temperature measurement method, this is transparent to the
user. This feature allows resistances to be added to the sensor
path to produce a filter, allowing the part to be used in noisy
environments. See the Noise Filtering section for details.
Factors Affecting Diode Accuracy
Remote Sensing Diode
The ADT7468 is designed to work with either substrate
transistors built into processors or with discrete transistors.
Substrate transistors are generally PNP types with the collector
connected to the substrate. Discrete types can be either PNP or
NPN transistors connected as a diode (base-shorted to the
collector). If an NPN transistor is used, the collector and base
are connected to D+, and the emitter is connected to D−. If a
PNP transistor is used, the collector and base are connected to
D− and the emitter is connected to D+.
To reduce the error due to variations in both substrate and
discrete transistors, a number of factors should be taken into
consideration:
•The ideality factor, nf, of the transistor is a measure of the
deviation of the thermal diode from ideal behavior. The
ADT7468 is trimmed for an nfvalue of 1.008. Use the
following equation to calculate the error introduced at a
temperature T (°C), when using a transistor whose nfdoes
not equal 1.008. See the processor data sheet for the
nfvalues.
ΔT= (nf−1.008) × (273.15 K + T)
To correct for this error, the user can write the ΔT value to
the offset register. The ADT7468 then automatically adds
or subtracts it from the temperature measurement.
•Some CPU manufacturers specify the high and low current
levels of the substrate transistors. The high current level of
the ADT7468, IHIGH, is 96 μA and the low level current,
ILOW, is 6 μA. If the ADT7468 current levels do not match
the current levels specified by the CPU manufacturer, it
might be necessary to remove an offset. The CPU’s data
sheet should advise whether this offset needs to be
removed and how to calculate it. This offset can be
programmed to the offset register. It is important to note
that, if more than one offset must be considered, the
algebraic sum of these offsets must be programmed to the
offset register.
If a discrete transistor is used with the ADT7468, the best
accuracy is obtained by choosing devices according to the
following criteria:
•Base-emitter voltage greater than 0.25 V at 6 μA, with the
highest operating temperature.
•Base-emitter voltage less than 0.95 V at 100 μA, with the
lowest operating temperature.
•Base resistance less than 100 Ω.
•Small variation in hFE (from 50 to 150), which indicates
tight control of VBE characteristics.

ADT7468
Rev. A | Page 20 of 84
Transistors, such as 2N3904, 2N3906, or equivalents in SOT-23
packages, are suitable devices to use.
Table 7. Temperature Data Format
Temperature Digital Output (10-Bit)1
–128°C 1000 0000 00
–125°C 1000 0011 00
–100°C 1001 1100 00
–75°C 1011 0101 00
–50°C 1100 1110 00
–25°C 1110 0111 00
–10°C 1111 0110 00
0°C 0000 0000 00
10.25°C 0000 1010 01
25.5°C 0001 1001 10
50.75°C 0011 0010 11
75°C 0100 1011 00
100°C 0110 0100 00
125°C 0111 1101 00
127°C 0111 1111 00
1 Bold numbers denote 2 LSB of measurement in Extended Resolution
Register 2 (Reg. 0x77) with 0.25°C resolution.
Table 8. Extended Range, Temperature Data Format
Temperature Digital Output (10-Bit)1
–64°C 0000 0000 00
–1°C 0011 1111 00
0°C 0100 0000 00
1°C 0100 0001 00
10°C 0100 1010 00
25°C 0101 1001 00
50°C 0111 0010 00
75°C 1000 1001 00
100°C 1010 0100 00
125°C 1011 1101 00
191°C 1111 1111 00
1Bold numbers denote 2 LSB of measurement in Extended Resolution
Register 2 (Reg. 0x77) with 0.25°C resolution.
2
N3904
NPN
ADT7468
D+
D–
04499-0-013
Figure 25. Measuring Temperature Using an NPN Transistor
2
N3906
PNP
ADT7468
D+
D–
04499-0-014
Figure 26. Measuring Temperature Using a PNP Transistor
Nulling Temperature Errors
As CPUs are developed that run faster, it is getting more
difficult to avoid high frequency clocks when routing the
D+/D– traces around a system board. Even when
recommended layout guidelines are followed, some temperature
errors may still be attributed to noise coupled onto the D+/D–
lines. Constant high frequency noise usually attenuates or
increases temperature measurements by a linear, constant value.
The ADT7468 has temperature offset registers at Addresses 0x70
and 0x72 for the Remote 1 and Remote 2 temperature channels.
By doing a one-time calibration of the system, the user can
determine the offset caused by system board noise and null it
using the offset registers. The offset registers automatically add
an Offset 64/twos complement 8-bit reading to every
temperature measurement. The LSBs add 0.5°C offset to the
temperature reading; therefore, the 8-bit register effectively
allows temperature offsets up to ±64°C with a resolution of
0.5°C. This ensures that the readings in the temperature
measurement registers are as accurate as possible.
Temperature Offset Registers
Reg. 0x70, Remote 1 temperature offset = 0x00 (0°C default)
Reg. 0x71, Local temperature offset = 0x00 (0°C default)
Reg. 0x72, Remote 2 temperature offset = 0x00 (0°C default)
ADT7463/ADT7468 Backwards Compatible Mode
By setting Bit 1 of Configuration Register 5 (0x7C), all tempera-
ture measurements are stored in the zone temperature value
registers (0x25, 0x26, and 0x27) in twos complement in the
range of −64°C to +127°C (the ADT7468 makes calculations
based on the Offset 64 extended range and clamps the results, if
necessary.) The temperature limits must be reprogrammed in
twos complement. If a twos complement temperature below
−63°C is entered, the temperature is clamped to −63°C.
In this mode, the diode fault condition remains at −128°C =
1000 0000, while in the extended temperature range (−64°C to
+191°C) the fault condition is represented by −64°C =
0000 0000.
Temperature Measurement Registers
Reg. 0x25, Remote 1 temperature
Reg. 0x26, Local temperature
Reg. 0x27, Remote 2 temperature
Reg. 0x77, Extended Resolution 2 = 0x00 default
<7:6> TDM2, Remote 2 temperature LSBs
<5:4> LTMP, local temperature LSBs
<3:2> TDM1, Remote 1 temperature LSBs