Aniotek Ufc100-l2 User manual

Aniotek Inc.

UNIFIED FIELDBUS CONTROLLER

UFC100-L2

BASIC MODE

USER’S MANUAL

Rev. 1.0 Proprietary and confidential information of Aniotek Inc. 21 May 2018

This document may be printed or copied only for the purpose of evaluating the product described in this document for the purpose of

including it as a part of another product or for developing and testing another product that uses the product described in this document as a

part. This document can not be used for any other purpose.

The product described in this document is meant for commercial and industrial applications and it is not meant for military, space, medical

or life-sustaining equipment. Aniotek Inc. does not make any warranty of fitness or suitability of this product for any purpose. Aniotek Inc.

reserves the right to make any changes to this document or the specifications of the product or discontinue the production of the product

described in this document at any time and without notice.

For further information contact:

Aniotek Inc.

10 April Drive

Dayton, NJ 08810

+1 732 274 2648

info@aniotek.com

Revision History

Rev. no. Reason for change

1.0 Released UFC100-L2, the second source from another foundry, technical changes are documented in 1.5

Changes between UFC100-L1 and UFC100-L2.

The Version number read from register 0x00 has changed –see Table 2: Basic mode registers and 2.2.3

Reset, version

iii

Rev. 1.0 Proprietary and confidential information of Aniotek Inc. 21 May 2018

TABLE OF CONTENTS

INTRODUCTION........................................................................................................................................ 1

1.1

OVERVIEW .............................................................................................................................................. 1

1.2

FEATURES ............................................................................................................................................... 1

1.3

APPLICATIONS......................................................................................................................................... 2

1.4

ORDERING INFORMATION ........................................................................................................................ 2

1.5

CHANGES BETWEEN UFC100-L1 AND UFC100-L2................................................................................... 2

1.6

PIN DESCRIPTION.................................................................................................................................... 2

BASIC MODE OPERATION...................................................................................................................... 4

2.1

OPERATION ............................................................................................................................................. 4

2.1.1

Transmit Machine ........................................................................................................................... 4

2.1.2

Receive Machine............................................................................................................................. 4

2.1.3

Data Link Timers............................................................................................................................ 4

2.1.4

MAU Interface................................................................................................................................ 4

2.1.5

CPU Bus Interface........................................................................................................................... 4

2.2

BASIC MODE REGISTERS........................................................................................................................... 5

2.2.1

Register list..................................................................................................................................... 5

2.2.2

Performance Improvement............................................................................................................... 5

2.2.3

Reset, version.................................................................................................................................. 6

2.2.4

Mode .............................................................................................................................................. 6

2.2.5

Control............................................................................................................................................ 7

2.2.6

Status.............................................................................................................................................. 8

2.2.7

Interrupt status................................................................................................................................ 8

2.2.8

Error status...................................................................................................................................... 9

2.2.9

Interrupt mask................................................................................................................................10

2.2.10

Error mask.....................................................................................................................................11

2.2.11

Transmit frame length....................................................................................................................11

2.2.12

FIFO control Register.....................................................................................................................12

2.2.13

FIFO status ....................................................................................................................................13

2.2.14

FIFO data.......................................................................................................................................13

2.2.15

Clock mode....................................................................................................................................14

2.2.16

Timer status...................................................................................................................................14

2.2.17

Node time ......................................................................................................................................14

2.2.18

GAP time.......................................................................................................................................15

2.2.19

Watch time.....................................................................................................................................15

2.2.20

Token counter................................................................................................................................15

2.2.21

Timer control .................................................................................................................................15

EXTERNAL INTERFACES.......................................................................................................................17

3.1

CLOCK INPUT .........................................................................................................................................17

3.2

CPU BUS INTERFACE..............................................................................................................................17

3.2.1

Renesas CPU with RDY.................................................................................................................18

3.2.2

Intel X86 Type CPU with /READY................................................................................................20

3.2.3

Freescale Type CPU with /DTACK, Existing Design......................................................................21

3.2.4

Freescale Type CPU with /DTACK, New Design ...........................................................................22

3.2.5

Power PC.......................................................................................................................................22

3.3

MAU INTERFACE ...................................................................................................................................23

3.3.1

Transmitter Interface......................................................................................................................23

3.3.2

Receiver Interface ..........................................................................................................................23

3.4

OTHER INTERFACES................................................................................................................................25

3.4.1

Reset and Interrupt Signals.............................................................................................................25

ELECTRICAL AND TEMPERATURE SPECIFICATIONS....................................................................26

Rev. 1.0 Proprietary and confidential information of Aniotek Inc. 21 May 2018

4.1

ABSOLUTE MAXIMUM RATINGS ..............................................................................................................26

4.2

OPERATING CONDITIONS ........................................................................................................................26

4.2.1

Current Consumption.....................................................................................................................27

4.3

CLOCK INPUT TIMINGS ...........................................................................................................................28

4.4

CPU BUS ACCESS TIMINGS.....................................................................................................................29

4.4.1

Intel Type CPU..............................................................................................................................29

4.4.2

Freescale Type CPU.......................................................................................................................31

4.4.3

DMA Request Timings...................................................................................................................32

4.5

MAU INTERFACE TIMINGS .....................................................................................................................33

4.5.1

MAU Interface Timings.................................................................................................................33

4.6

OTHER TIMINGS .....................................................................................................................................34

4.6.1

Reset Timings................................................................................................................................34

4.6.2

Interrupt Timings...........................................................................................................................34

PACKAGE.............................................................................FEHLER! TEXTMARKE NICHT DEFINIERT.

TEST PROCEDURES.................................................................................................................................37

2.1

REGISTER ACCESS...................................................................................................................................37

2.2

INITIALIZATION ......................................................................................................................................37

2.3

FRAME TRANSMISSION............................................................................................................................37

2.3.1

Using non-DMA Write to the Transmit FIFO..................................................................................37

2.3.2

Using DMA Write to the Transmit FIFO.........................................................................................38

2.4

FRAME RECEPTION..................................................................................................................................38

2.4.1

Using non-DMA access to the FIFO...............................................................................................38

2.4.2

Using DMA access to the FIFO......................................................................................................39

2.5

WATCH TIMER........................................................................................................................................39

2.6

TOKEN TIMER.........................................................................................................................................39

Unified Fieldbus Controller UFC100-L2 –Basic mode operation Page 1

Rev. 1.0 Proprietary and confidential information of Aniotek Inc. 21 May 2018

1 I

NTRODUCTION

The UFC100-L2 (Unified Fieldbus Controller) is a peripheral that that can be used in a Fieldbus Device or Host to provide a

complete solution for implementing Fieldbus equipment. The UFC100-L2 includes all of time-critical functions in the

hardware. It implements part of Physical and Data Link Layers for the Foundation Fieldbus H1 and Profibus-PA. This

document describes the mode of operation that is compatible with existing Fieldbus controllers. It shows the pin signals, the

internal registers that can be accessed by a software program, electrical specifications and package dimensions. It also

includes procedures for software device drivers and hardware test.

1.1 Overview

Figure 1: UFC100-L2 Block Diagram

1.2 Features

It is:

·Compliant to IEC 61158-2 Physical layer at 31.25 Kbit/s,

·Compliant to IEC 61158-4 Data Link layer,

·RoHS certified 44 pin LQFP package,

·Operating voltage 2.7 to 3.6 V,

·Low current consumption suitable for Field devices,

·Flexible 8-bit CPU bus interface suitable for all types of processors,

·128 byte Transmit and Receive FIFO to reduce the number of the interrupts to the CPU.

CPU Bus

Interface

Interrupt Encoder

Jabber Control and Data Link Timers

(Bus Inactivity, GAP, Token, Node Time)

MAU

Interface

Clock

Generator

Data Link State Machine

Clock

Synchronizer

Serial to

Parallel FCS

Checker

Manchester

Decoder

Delimiter

Detector

Decoder

FIFO

(128)

Data Link Address Filter

Receive

Machine

Control

Receive Machine

INTn

CSn4

RDn2

WRn3

RDY

D7-D036-

RSTn

ATYP

CTYP

A6, A5

9, 8

FIFO

(128) Parallel

to Serial FCS

Generator

Manchester

Encoder

Delimiter

Generator

Transmit

Machine

Control

Transmit Machine

TxS 19

TxEn 20

RxS 21

RxA 22

RES1 13

RES2 14

CLKIN

RES0

FLT1n

FLT0n

Shade indicates

Enhanced

Functions

A4-A0

1, 44-

TxA 15

Unified Fieldbus Controller UFC100-L2 –Basic mode operation Page 2

Rev. 1.0 Proprietary and confidential information of Aniotek Inc. 21 May 2018

1.3 Applications

The UFC100-L2 can be used for:

·FF-H1 Fieldbus Device,

·PROFIBUS-PA Fieldbus Device,

·H1 Host Interface,

·HSE Linking Device.

1.4 Ordering Information

UFC100-L2 Unified Fieldbus Controller in LQFP package

Order number of UFC100-L2: IFL-KK-02091

1.5 Changes between UFC100-L1 and UFC100-L2

The UFC100-L2 has function, package and pins same as UFC100-L1, except in L2 the following pins are not 5 V tolerant.

Pin Signal

RESETn

RxS

RxA

FLT0n

CTYP

ATYP

The UFC100-L2 draws lower current for its operation –see Current Consumption.

1.6 PIN Description

The following conventions are used.

Name If the name ends in ‘n’then that signal is active low.

Type It specifies the type of input or output.

P Power

ICH Input –CMOS with hysteresis

O Output –always active

BCH

Input / Output CMOS with hysteresis

Reset value For output signals, it specifies the value when external (hardware) reset is applied.

H High

L Low

Tristate

Unified Fieldbus Controller UFC100-L2 –Basic mode operation Page 3

Rev. 1.0 Proprietary and confidential information of Aniotek Inc. 21 May 2018

Table 1: UFC100-L2 Pin out

no. Name Type Reset

value

Description

ICH

CPU Address bus

RDn/EDSn

ICH

Read Strobe (Intel mode),

E or DSn (Freescale mode)

WRn/RWn ICH Write Strobe (Intel mode), RWn –Read or Write select (Freescale

mode)

CSn

ICH

Chip Select

–

active state enables Read or Write access.

CLKIN

ICH

Clock input

–

the frequency has to be one of 1, 2, 4 or 8 Mhz.

Vss

Power negative side

RESETn

ICH

Reset

–

active (low).

ICH

This pin can be connected to CPU address A5, or to Vdd or Vss.

ICH

This pin can be connected

to CPU address A6, or to Vdd or Vss.

MS2

ICH

Reserved for test use; connect it to Vss.

INTn

Interrupt request to the CPU

RES0

Reserved

RES1

Reserved

RES2

Reserved

TxA

It is used as TxA output, which is high whil

e transmitter is active.

TxRn

Low pulse of 8 µs duration whenever TxS changes.

Vdd

Power plus side

Vss

Power negative side

TxS

Transmit signal to medium attachment unit

TxEn

Transmit control to medium attachment unit

RxS

ICH

Receive Signal from medium attachment unit

RxA

ICH

Receive activity (carrier detect) from medium attachment unit

TST0

ICH

Test input; connect to Vss in normal operation.

FLT1n

ICH

Not used

–

this pin can be connected either Vss o

r Vdd.

DMA request output, one pulse per byte to be transferred

FLT0n

ICH

Not used

–

this pin can be connected either Vss or Vdd.

RDY

DACKn

O H

ATYP high: low value indicates that the data is ready or accepted.

ATYP low: high value in

dicates that the data is ready or accepted.

Vss

Power negative side

BCH

CPU Data bus

BCH

CPU Data bus

BCH

CPU Data bus

BCH

CPU Data bus

BCH

CPU Data bus

BCH

CPU Data bus

BCH

CPU D

ata bus

BCH

CPU Data bus

CTYP

ICH

Type of CPU

–

Low: Intel,

High: Freescale

ATYP

ICH

Type of bus access

–

Low: RDY output,

High: DACKn output

Vdd

Power plus side

Vss

Power negative side

ICH

CPU Address bus

ICH

CPU Address bus

ICH

CPU Address bus

ICH

CPU Address bus

Unified Fieldbus Controller UFC100-L2 –Basic mode operation Page 4

Rev. 1.0 Proprietary and confidential information of Aniotek Inc. 21 May 2018

2 B

ASIC MODE OPERATION

2.1 Operation

2.1.1 Transmit Machine

It has 128 byte Transmit FIFO. For most of the frame types, the CPU can write the entire frame to this memory. The

automatic FCS can be disabled for test purpose. The Transmission starts only when the gap from the immediately prior

reception or transmission is more than or equal to the programmed minimum Gap. Transmission starts by sending a

programmed number of Preamble bytes followed by the Start Delimiter. The transmission ends by sending any remaining

bytes of the frame, followed by two FCS bytes, followed by End Delimiter. DMA can be used to transfer bytes to be

transmitted from the memory to the FIFO.

If there is a transmission error or if the CPU aborts the transmission; it ends by sending the current byte, followed by wrong

(inverted) FCS followed by End Delimiter; and the CPU or DMA attempt to write to the FIFO is ignored until the CPU resets

transmission error flags. If the error or abort is detected while transmitting Preamble, then it ends after sending the full byte

of Preamble. If the error or abort is detected while transmitting Start Delimiter, then it ends after sending Start Delimiter

followed by End Delimiter. If the error or abort by the CPU occurs after the transmitter has read the last byte from the FIFO –

only possible for FIFO overflow error or length mismatch error, then the error flag is set, but transmission is not aborted. The

error flags are set when Transmitter has finished transmitting the last bit, unless it is FIFO overflow error and it is detected

before TRON is set to ‘1’.

2.1.2 Receive Machine

The received frame is stored in the 128 byte Receive FIFO. The signal polarity of the received signal is automatically

corrected. For most frames, an interrupt is generated only after the entire frame has been stored in this memory. The CPU can

cancel the current reception. The current reception is also cancelled if any error is detected, but the Receive FIFO is not

cleared. The receiver does not write any more bytes to this FIFO. The error flag is set when the error is detected, but further

errors are not registered. DMA can be used to transfer received bytes from the FIFO to the memory.

2.1.3 Data Link Timers

The Node Time counter keeps the value of Node time with a resolution of 1/4 ms or 1/32 ms depending upon another setting.

Watch-time counter is used to monitor Maximum-Response-Delay, Immediate-Response-Recovery-Delay and Token-

Recovery-Delay. Whenever there is no receive or transmit activity, it counts once every byte-time. Whenever there is receive

activity or there is active transmission, this counter is reset to zero. There is a filter on bus activity, so that noise does not

reset this counter.

Gap counter is used to provide the minimum gap between two frames –it runs whenever there is no receive or transmit

activity.

Jabber Counter is used to check the length of transmit frame or receive frame –it runs whenever there is transmit activity and

jabber is enabled or there is receive activity and jabber is enabled.

Token Counter is used as Remaining Token Duration timer. It is always loaded from the PT frame. It can be reloaded by the

CPU any time. The internal clock has to be active to load Token counter. Token timer is always enabled. It counts down

whenever it is non-zero.

2.1.4 MAU Interface

It converts the internal transmit signals to TxE and TxS. The Transmit driver can be setup for Transmit Enable or ADD

mode. The input RxA and RxS signals are converted to internal receive signals. The loopback modes can be setup for testing.

Physical layer parameters such as Preamble extension and minimum Gap can be setup.

2.1.5 CPU Bus Interface

The UFC100-L2 can be connected to any synchronous or asynchronous bus. The type of CPU can be Intel or Freescale. The

selection is done by two input pins. The data interface is 8-bit wide; the address bus is 5-bit wide.

Unified Fieldbus Controller UFC100-L2 –Basic mode operation Page 5

Rev. 1.0 Proprietary and confidential information of Aniotek Inc. 21 May 2018

2.2 Basic mode registers

2.2.1 Register list

Table 2: Basic mode registers

Address

HEX

Name Access

Read/

Write

Reset

value

Description

Reset, Version

R/W

0x3

Software reset

, UFC100-L2 Version

Mode

R/W

0x00

Selection of operating modes

Control

R/W

0x00

Control functions

Status

0x82

Shows status

Interrupt

tatus

0x00

Shows reason of interrupts

Error

tatus

0x00

Shows reason of communication errors

Interrupt

ask

R/W

0xFE

Mask for interrupts

Error

ask

R/W

0xFB

Mast for error interrupts

ength (LOW)

R/W

0x00

Length of transmitted frame (Lower byte)

ength (HIGH)

R/W

Length of transmitted frame (Higher 2 bits)

eserved

(

)

Not used

FIFO

ontrol

R/W

0x00

Control register of FIFO

FIFO

tatus

0x11

Shows status of FIFO

DATA

R/W

0x00

Transmit/Receive data to/from FIFO

eserved

(

)

Not

used

Reserved

(

)

Not used

Clock

ode

R/W

0x00

ode, Timer

nables

Timer

tatus

0x00

Node

timer status

Node

ime (LOW)

R/W

0x00

Timer to hold DL NODE time (Lower byte)

Node

ime (HIGH)

R/W

0x00

Timer to hold DL NODE time (Hig

her byte)

Gap time

0xFF

Value to generate minimum inter

PDU delay

eserved

(

)

Not used

Watch

ime (LOW)

0xFF

Value to detect no

activity of bus (Lower byte)

Watch

ime (HIGH)

0xFF

Value to detect no

activity of bus (Highe

r byte)

Token

counter

(LOW)

R/W

0x00

Remaining token holding time (Lower byte)

Token

counter

(HIGH)

R/W

0x00

Remaining token holding time (Higher byte)

Timer

ontrol

R/W

0x00

Control DL timers

Reserved

(

)

Not used

Reserved

(

)

Not used

Reserve

(

)

Not used

Reserve

(

)

Not used

Reserve

(

)

Not used

(1): Unused registers read as 0x00.

2.2.2 Performance Improvement

Even with existing software, UFC100-L2 reduces the number of the interrupts to the CPU and thus provides performance

improvement. There is filter on bus activity to make it less sensitive to noise.

Unified Fieldbus Controller UFC100-L2 –Basic mode operation Page 6

Rev. 1.0 Proprietary and confidential information of Aniotek Inc. 21 May 2018

2.2.3 Reset, version

Address: 0x00

Reset value: 0x30

Table 3: UFC Reset, Version register

Reset, Version

Bit no.

Name

RST

Not used

–

Ver[5..0]

RST Soft Reset

Writing ‘1’to this field applies reset to all parts of the UFC100-L2. It may take up to 4 cycles of input clock to complete

the reset operation. If the CPU does not use RDY signal, then it should check ARDY field in Status register –see 2.2.6,

before starting the next Read or Write cycle from the CPU. This field is always read as ‘0’.

Ver[5..0] UFC Version

This read only field shows the UFC version number. Its value is 0b010000.

2.2.4 Mode

Address: 0x01

Reset value: 0x00

This registers sets up clock and other modes. The internal clock is enabled only after the CPU writes any value to Mode

register even if the value to be written is 0x00, so that the internal clock does not start at a higher than the desired frequency.

Table 4: UFC Mode register

Mode

Bit no.

Name

7, 6

CLOCK

FDP

3,2

PRE

TFCS

TMD

CLOCK Clock divider

This field is used to select divide factor of prescaler to generate internal clock of 500 kHz frequency.

Table 5: Clock divider

Input clock Divider CLOCK[7,6]

MHz

LB Loop back

If this field is set to ‘1’then internal loopback from the transmitter to the receiver is enabled. In this loopback mode, the

transmitted signal is fed to the receive circuit and the signals from the external MAU are ignored. TxS and TxEn stay

inactive in the internal loopback.

FDP Full duplex

If this field is set to ‘0’then the receiver is disabled while transmitting, else receiver is always enabled. It is necessary to

set FDP to ‘1’to receive the transmitted frame in the internal loopback mode. The value of this field does not affect the

current consumption.

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