Aniotek UFC100-L2 User manual

Aniotek Inc.
UNIFIED FIELDBUS CONTROLLER
UFC100-L2
BASIC MODE
USER’S MANUAL

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Rev. 1.0 Proprietary and confidential information of Aniotek Inc. 21 May 2018
COPYRIGHT NOTICE
Copyright © 2018 Aniotek Inc., ALL RIGHTS RESERVED.
This document may be printed or copied only for the purpose of evaluating the product described in this document for the purpose of
including it as a part of another product or for developing and testing another product that uses the product described in this document as a
part. This document can not be used for any other purpose.
The product described in this document is meant for commercial and industrial applications and it is not meant for military, space, medical
or life-sustaining equipment. Aniotek Inc. does not make any warranty of fitness or suitability of this product for any purpose. Aniotek Inc.
reserves the right to make any changes to this document or the specifications of the product or discontinue the production of the product
described in this document at any time and without notice.
For further information contact:
Aniotek Inc.
10 April Drive
Dayton, NJ 08810
[phone]
[e-mail]
Revision History
Rev. no. Reason for change
1.0 Released UFC100-L2, the second source from another foundry, technical changes are documented in 1.5
Changes between UFC100-L1 and UFC100-L2.
The Version number read from register 0x00 has changed –see Table 2: Basic mode registers and 2.2.3
Reset, version

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Rev. 1.0 Proprietary and confidential information of Aniotek Inc. 21 May 2018
TABLE OF CONTENTS
1 INTRODUCTION........................................................................................................................................ 1
1.1 OVERVIEW .............................................................................................................................................. 1
1.2 FEATURES ............................................................................................................................................... 1
1.3 APPLICATIONS......................................................................................................................................... 2
1.4 ORDERING INFORMATION ........................................................................................................................ 2
1.5 CHANGES BETWEEN UFC100-L1 AND UFC100-L2................................................................................... 2
1.6 PIN DESCRIPTION.................................................................................................................................... 2
2 BASIC MODE OPERATION...................................................................................................................... 4
2.1 OPERATION ............................................................................................................................................. 4
2.1.1 Transmit Machine ........................................................................................................................... 4
2.1.2 Receive Machine............................................................................................................................. 4
2.1.3 Data Link Timers............................................................................................................................ 4
2.1.4 MAU Interface................................................................................................................................ 4
2.1.5 CPU Bus Interface........................................................................................................................... 4
2.2 BASIC MODE REGISTERS........................................................................................................................... 5
2.2.1 Register list..................................................................................................................................... 5
2.2.2 Performance Improvement............................................................................................................... 5
2.2.3 Reset, version.................................................................................................................................. 6
2.2.4 Mode .............................................................................................................................................. 6
2.2.5 Control............................................................................................................................................ 7
2.2.6 Status.............................................................................................................................................. 8
2.2.7 Interrupt status................................................................................................................................ 8
2.2.8 Error status...................................................................................................................................... 9
2.2.9 Interrupt mask................................................................................................................................10
2.2.10 Error mask.....................................................................................................................................11
2.2.11 Transmit frame length....................................................................................................................11
2.2.12 FIFO control Register.....................................................................................................................12
2.2.13 FIFO status ....................................................................................................................................13
2.2.14 FIFO data.......................................................................................................................................13
2.2.15 Clock mode....................................................................................................................................14
2.2.16 Timer status...................................................................................................................................14
2.2.17 Node time ......................................................................................................................................14
2.2.18 GAP time.......................................................................................................................................15
2.2.19 Watch time.....................................................................................................................................15
2.2.20 Token counter................................................................................................................................15
2.2.21 Timer control .................................................................................................................................15
3 EXTERNAL INTERFACES.......................................................................................................................17
3.1 CLOCK INPUT .........................................................................................................................................17
3.2 CPU BUS INTERFACE..............................................................................................................................17
3.2.1 Renesas CPU with RDY.................................................................................................................18
3.2.2 Intel X86 Type CPU with /READY................................................................................................20
3.2.3 Freescale Type CPU with /DTACK, Existing Design......................................................................21
3.2.4 Freescale Type CPU with /DTACK, New Design ...........................................................................22
3.2.5 Power PC.......................................................................................................................................22
3.3 MAU INTERFACE ...................................................................................................................................23
3.3.1 Transmitter Interface......................................................................................................................23
3.3.2 Receiver Interface ..........................................................................................................................23
3.4 OTHER INTERFACES................................................................................................................................25
3.4.1 Reset and Interrupt Signals.............................................................................................................25
4 ELECTRICAL AND TEMPERATURE SPECIFICATIONS....................................................................26

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4.1 ABSOLUTE MAXIMUM RATINGS ..............................................................................................................26
4.2 OPERATING CONDITIONS ........................................................................................................................26
4.2.1 Current Consumption.....................................................................................................................27
4.3 CLOCK INPUT TIMINGS ...........................................................................................................................28
4.4 CPU BUS ACCESS TIMINGS.....................................................................................................................29
4.4.1 Intel Type CPU..............................................................................................................................29
4.4.2 Freescale Type CPU.......................................................................................................................31
4.4.3 DMA Request Timings...................................................................................................................32
4.5 MAU INTERFACE TIMINGS .....................................................................................................................33
4.5.1 MAU Interface Timings.................................................................................................................33
4.6 OTHER TIMINGS .....................................................................................................................................34
4.6.1 Reset Timings................................................................................................................................34
4.6.2 Interrupt Timings...........................................................................................................................34
1 PACKAGE.............................................................................FEHLER! TEXTMARKE NICHT DEFINIERT.
2 TEST PROCEDURES.................................................................................................................................37
2.1 REGISTER ACCESS...................................................................................................................................37
2.2 INITIALIZATION ......................................................................................................................................37
2.3 FRAME TRANSMISSION............................................................................................................................37
2.3.1 Using non-DMA Write to the Transmit FIFO..................................................................................37
2.3.2 Using DMA Write to the Transmit FIFO.........................................................................................38
2.4 FRAME RECEPTION..................................................................................................................................38
2.4.1 Using non-DMA access to the FIFO...............................................................................................38
2.4.2 Using DMA access to the FIFO......................................................................................................39
2.5 WATCH TIMER........................................................................................................................................39
2.6 TOKEN TIMER.........................................................................................................................................39

Unified Fieldbus Controller UFC100-L2 –Basic mode operation Page 1
Rev. 1.0 Proprietary and confidential information of Aniotek Inc. 21 May 2018
1 I NTRODUCTION
The UFC100-L2 (Unified Fieldbus Controller) is a peripheral that that can be used in a Fieldbus Device or Host to provide a
complete solution for implementing Fieldbus equipment. The UFC100-L2 includes all of time-critical functions in the
hardware. It implements part of Physical and Data Link Layers for the Foundation Fieldbus H1 and Profibus-PA. This
document describes the mode of operation that is compatible with existing Fieldbus controllers. It shows the pin signals, the
internal registers that can be accessed by a software program, electrical specifications and package dimensions. It also
includes procedures for software device drivers and hardware test.
1.1 Overview
Figure 1: UFC100-L2 Block Diagram
1.2 Features
It is:
·Compliant to IEC 61158-2 Physical layer at 31.25 Kbit/s,
·Compliant to IEC 61158-4 Data Link layer,
·RoHS certified 44 pin LQFP package,
·Operating voltage 2.7 to 3.6 V,
·Low current consumption suitable for Field devices,
·Flexible 8-bit CPU bus interface suitable for all types of processors,
·128 byte Transmit and Receive FIFO to reduce the number of the interrupts to the CPU.
CPU Bus
Interface
Interrupt Encoder
Jabber Control and Data Link Timers
(Bus Inactivity, GAP, Token, Node Time)
MAU
Interface
Clock
Generator
Data Link State Machine
Clock
Synchronizer
Serial to
Parallel FCS Checker
Manchester
Decoder
Delimiter
Detector
FC
Decoder
FIFO
(128)
Data Link Address Filter
Receive
Machine
Control
Receive Machine
INTn
11
CSn4
RDn2
WRn3
RDY
27
RQ
25
D7-D036-
29
RSTn 7
ATYP 38
CTYP 37
A6, A5
9, 8
FIFO
(128) Parallel
to Serial FCS
Generator
Manchester
Encoder
Delimiter
Generator
Transmit
Machine
Control
Transmit Machine
TxS 19
TxEn 20
RxS 21
RxA 22
RES1 13
RES2 14
Tx
Rn
16
CLKIN
N
5
12
RES0
FLT1n
24
FLT0n
26
Shade indicates
Enhanced
Functions
A4-A0
1, 44-
41
TxA 15

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1.3 Applications
The UFC100-L2 can be used for:
·FF-H1 Fieldbus Device,
·PROFIBUS-PA Fieldbus Device,
·H1 Host Interface,
·HSE Linking Device.
1.4 Ordering Information
UFC100-L2 Unified Fieldbus Controller in LQFP package
Order number of UFC100-L2: IFL-KK-02091
1.5 Changes between UFC100-L1 and UFC100-L2
The UFC100-L2 has function, package and pins same as UFC100-L1, except in L2 the following pins are not 5 V tolerant.
Pin Signal
7
RESETn
21
RxS
22
RxA
26
FLT0n
37
CTYP
38
ATYP
The UFC100-L2 draws lower current for its operation –see Current Consumption.
1.6 PIN Description
The following conventions are used.
Name If the name ends in ‘n’then that signal is active low.
Type It specifies the type of input or output.
P Power
ICH Input –CMOS with hysteresis
O Output –always active
BCH
Input / Output CMOS with hysteresis
Reset value For output signals, it specifies the value when external (hardware) reset is applied.
H High
L Low
TS
Tristate

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Table 1: UFC100-L2 Pin out
Pin
no. Name Type Reset value
Description
1
A4
ICH
CPU Address bus
2
RDn/EDSn
ICH
Read Strobe (Intel mode),
E or DSn (Freescale mode)
3 WRn/RWn ICH Write Strobe (Intel mode), RWn –Read or Write select (Freescale
mode)
4
CSn
ICH
Chip Select
–
active state enables Read or Write access.
5
CLKIN
ICH
Clock input
–
the frequency has to be one of 1, 2, 4 or 8 Mhz.
6
Vss
P
Power negative side
7
RESETn
ICH
Reset
–
active (low).
8
A5
ICH
This pin can be connected to CPU address A5, or to Vdd or Vss.
9
A6
ICH
This pin can be connected
to CPU address A6, or to Vdd or Vss.
10
MS2
ICH
Reserved for test use; connect it to Vss.
11
INTn
O
H
Interrupt request to the CPU
12
RES0
O
L
Reserved
13
RES1
O
L
Reserved
14
RES2
O
L
Reserved
15
TxA
O
L
It is used as TxA output, which is high whil
e transmitter is active.
16
TxRn
O
H
Low pulse of 8 µs duration whenever TxS changes.
17
Vdd
P
Power plus side
18
Vss
P
Power negative side
19
TxS
O
L
Transmit signal to medium attachment unit
20
TxEn
O
H
Transmit control to medium attachment unit
21
RxS
ICH
Receive Signal from medium attachment unit
22
RxA
ICH
Receive activity (carrier detect) from medium attachment unit
23
TST0
ICH
Test input; connect to Vss in normal operation.
24
FLT1n
ICH
Not used
–
this pin can be connected either Vss o
r Vdd.
25
RQ
O
L
DMA request output, one pulse per byte to be transferred
26
FLT0n
ICH
Not used
–
this pin can be connected either Vss or Vdd.
27 RDY
DACKn
O H
H
ATYP high: low value indicates that the data is ready or accepted.
ATYP low: high value in
dicates that the data is ready or accepted.
28
Vss
P
Power negative side
29
D0
BCH
TS
CPU Data bus
30
D1
BCH
TS
CPU Data bus
31
D2
BCH
TS
CPU Data bus
32
D3
BCH
TS
CPU Data bus
33
D4
BCH
TS
CPU Data bus
34
D5
BCH
TS
CPU Data bus
35
D6
BCH
TS
CPU D
ata bus
36
D7
BCH
TS
CPU Data bus
37
CTYP
ICH
Type of CPU
–
Low: Intel,
High: Freescale
38
ATYP
ICH
Type of bus access
–
Low: RDY output,
High: DACKn output
39
Vdd
P
Power plus side
40
Vss
P
Power negative side
41
A0
ICH
CPU Address bus
42
A1
ICH
CPU Address bus
43
A2
ICH
CPU Address bus
44
A3
ICH
CPU Address bus

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2 B ASIC MODE OPERATION
2.1 Operation
2.1.1 Transmit Machine
It has 128 byte Transmit FIFO. For most of the frame types, the CPU can write the entire frame to this memory. The
automatic FCS can be disabled for test purpose. The Transmission starts only when the gap from the immediately prior
reception or transmission is more than or equal to the programmed minimum Gap. Transmission starts by sending a
programmed number of Preamble bytes followed by the Start Delimiter. The transmission ends by sending any remaining
bytes of the frame, followed by two FCS bytes, followed by End Delimiter. DMA can be used to transfer bytes to be
transmitted from the memory to the FIFO.
If there is a transmission error or if the CPU aborts the transmission; it ends by sending the current byte, followed by wrong
(inverted) FCS followed by End Delimiter; and the CPU or DMA attempt to write to the FIFO is ignored until the CPU resets
transmission error flags. If the error or abort is detected while transmitting Preamble, then it ends after sending the full byte
of Preamble. If the error or abort is detected while transmitting Start Delimiter, then it ends after sending Start Delimiter
followed by End Delimiter. If the error or abort by the CPU occurs after the transmitter has read the last byte from the FIFO –
only possible for FIFO overflow error or length mismatch error, then the error flag is set, but transmission is not aborted. The
error flags are set when Transmitter has finished transmitting the last bit, unless it is FIFO overflow error and it is detected
before TRON is set to ‘1’.
2.1.2 Receive Machine
The received frame is stored in the 128 byte Receive FIFO. The signal polarity of the received signal is automatically
corrected. For most frames, an interrupt is generated only after the entire frame has been stored in this memory. The CPU can
cancel the current reception. The current reception is also cancelled if any error is detected, but the Receive FIFO is not
cleared. The receiver does not write any more bytes to this FIFO. The error flag is set when the error is detected, but further
errors are not registered. DMA can be used to transfer received bytes from the FIFO to the memory.
2.1.3 Data Link Timers
The Node Time counter keeps the value of Node time with a resolution of 1/4 ms or 1/32 ms depending upon another setting.
Watch-time counter is used to monitor Maximum-Response-Delay, Immediate-Response-Recovery-Delay and Token-
Recovery-Delay. Whenever there is no receive or transmit activity, it counts once every byte-time. Whenever there is receive
activity or there is active transmission, this counter is reset to zero. There is a filter on bus activity, so that noise does not
reset this counter.
Gap counter is used to provide the minimum gap between two frames –it runs whenever there is no receive or transmit
activity.
Jabber Counter is used to check the length of transmit frame or receive frame –it runs whenever there is transmit activity and
jabber is enabled or there is receive activity and jabber is enabled.
Token Counter is used as Remaining Token Duration timer. It is always loaded from the PT frame. It can be reloaded by the
CPU any time. The internal clock has to be active to load Token counter. Token timer is always enabled. It counts down
whenever it is non-zero.
2.1.4 MAU Interface
It converts the internal transmit signals to TxE and TxS. The Transmit driver can be setup for Transmit Enable or ADD
mode. The input RxA and RxS signals are converted to internal receive signals. The loopback modes can be setup for testing.
Physical layer parameters such as Preamble extension and minimum Gap can be setup.
2.1.5 CPU Bus Interface
The UFC100-L2 can be connected to any synchronous or asynchronous bus. The type of CPU can be Intel or Freescale. The
selection is done by two input pins. The data interface is 8-bit wide; the address bus is 5-bit wide.

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2.2 Basic mode registers
2.2.1 Register list
Table 2: Basic mode registers
Address
HEX Name Access Read/
Write
Reset
value Description
00
Reset, Version
R/W
0x3
0
Software reset
, UFC100-L2 Version
01
Mode
R/W
0x00
Selection of operating modes
02
Control
R/W
0x00
Control functions
03
Status
R/
-
0x82
Shows status
04
Interrupt
s
tatus
R/
-
0x00
Shows reason of interrupts
0
5
Error
s
tatus
R/
-
0x00
Shows reason of communication errors
06
Interrupt
m
ask
R/W
0xFE
Mask for interrupts
07
Error
m
ask
R/W
0xFB
Mast for error interrupts
08
Tx
l
ength (LOW)
R/W
0x00
Length of transmitted frame (Lower byte)
09
Tx
l
ength (HIGH)
R/W
0x
00
Length of transmitted frame (Higher 2 bits)
0A
R
eserved
-
/
-
--
(
1
)
Not used
0B
FIFO
c
ontrol
R/W
0x00
Control register of FIFO
0C
FIFO
s
tatus
R/
-
0x11
Shows status of FIFO
0D
DATA
R/W
0x00
Transmit/Receive data to/from FIFO
0E
R
eserved
-
/
-
--
(
1
)
Not
used
0F
Reserved
-
/
-
--
(
1
)
Not used
10
Clock
m
ode
R/W
0x00
DL
m
ode, Timer
e
nables
11
Timer
s
tatus
R
0x00
Node
-
timer status
12
Node
t
ime (LOW)
R/W
0x00
Timer to hold DL NODE time (Lower byte)
13
Node
t
ime (HIGH)
R/W
0x00
Timer to hold DL NODE time (Hig
her byte)
14
Gap time
-
/W
0xFF
Value to generate minimum inter
-
PDU delay
15
R
eserved
-
/
-
--
(
3
)
Not used
16
Watch
t
ime (LOW)
-
/W
0xFF
Value to detect no
-
activity of bus (Lower byte)
17
Watch
t
ime (HIGH)
-
/W
0xFF
Value to detect no
-
activity of bus (Highe
r byte)
18
Token
counter
(LOW)
R/W
0x00
Remaining token holding time (Lower byte)
19
Token
counter
(HIGH)
R/W
0x00
Remaining token holding time (Higher byte)
1A
Timer
c
ontrol
R/W
0x00
Control DL timers
1B
Reserved
-
/
-
--
(
1
)
Not used
1C
Reserved
-
/
-
--
(
1
)
Not used
1D
Reserve
d
-
/
-
--
(
1
)
Not used
1E
Reserve
d
-
/
-
--
(
1
)
Not used
1F
Reserve
d
-
/
-
--
(
1
)
Not used
(1): Unused registers read as 0x00.
2.2.2 Performance Improvement
Even with existing software, UFC100-L2 reduces the number of the interrupts to the CPU and thus provides performance
improvement. There is filter on bus activity to make it less sensitive to noise.

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2.2.3 Reset, version
Address: 0x00
Reset value: 0x30
Table 3: UFC Reset, Version register
Reset, Version
Bit no.
Name
7
RST
6
Not used
5
–
0
Ver[5..0]
RST Soft Reset
Writing ‘1’to this field applies reset to all parts of the UFC100-L2. It may take up to 4 cycles of input clock to complete
the reset operation. If the CPU does not use RDY signal, then it should check ARDY field in Status register –see 2.2.6,
before starting the next Read or Write cycle from the CPU. This field is always read as ‘0’.
Ver[5..0] UFC Version
This read only field shows the UFC version number. Its value is 0b010000.
2.2.4 Mode
Address: 0x01
Reset value: 0x00
This registers sets up clock and other modes. The internal clock is enabled only after the CPU writes any value to Mode
register even if the value to be written is 0x00, so that the internal clock does not start at a higher than the desired frequency.
Table 4: UFC Mode register
Mode
Bit no.
Name
7, 6
CLOCK
5
LB
4
FDP
3,2
PRE
1
TFCS
0
TMD
CLOCK Clock divider
This field is used to select divide factor of prescaler to generate internal clock of 500 kHz frequency.
Table 5: Clock divider
Input clock Divider CLOCK[7,6]
1
MHz
2
00
2
MHz
4
01
4
MHz
8
10
8
MHz
16
11
LB Loop back
If this field is set to ‘1’then internal loopback from the transmitter to the receiver is enabled. In this loopback mode, the
transmitted signal is fed to the receive circuit and the signals from the external MAU are ignored. TxS and TxEn stay
inactive in the internal loopback.
FDP Full duplex
If this field is set to ‘0’then the receiver is disabled while transmitting, else receiver is always enabled. It is necessary to
set FDP to ‘1’to receive the transmitted frame in the internal loopback mode. The value of this field does not affect the
current consumption.

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PRE Preamble extension
It specifies extension of preamble bytes for each transmission.
PRE Preamble count
00 1 byte,
01 2 bytes,
10 3 bytes,
11 4 bytes.
TFCS Through pass of FCS
If this field is set to ‘1’then the two bytes of the FCS are not appended during transmission and the last two bytes of the
received frame are stored in the Receive FIFO. The FCS is always checked during reception and if incorrect then the
FCSE field in the Error status register (see 2.2.8) is set to ‘1’.
TMD Transmission mode
This field controls transmission mode.
0 Enable mode,
1 ADD mode.
2.2.5 Control
Address: 0x02
Reset value: 0x00
Table 6: UFC Control register
Control
Bit no. Name
7
DMA
6
RE
5
RCL
4
Not used
3
JIE
2
TRON
1
Not used
0
IE
DMA DMA enable
If this field is set to ‘1’then the data transfer between the FIFO and the memory is done using DMA and RQ output is
enabled. The TRON field controls the direction of the data transfer. If TRON is ‘1’, then data is transferred from the
memory to the Transmit FIFO, else the data is transferred from the Receive FIFO to the memory.
For transmission, the DMA transfer starts when ‘TRON’and ‘DMA’both are set to ‘1’. The Transmit length register is
decremented by ‘1’for every byte written to the Transmit FIFO. The DMA transfer continues until either the Transmit
length register becomes zero or the Transmit FIFO becomes full. If the Transmit FIFO becomes full then DMA starts
again when there is space in that FIFO and continues until the Transmit length register becomes zero. When the
Transmit length register becomes zero, the ‘DMA’field is reset to ‘0’. ‘DMA’field is also reset to ‘0’when
transmission is aborted.
For reception, if the DMA is enabled then all data is transferred from the Receive FIFO to the memory before disabling
DMA. If a reception error occurs then the reception is cancelled but DMA is not disabled and the error flag is set only
after the Receive FIFO becomes empty.
RE Receiver enable
If this field is set to ‘1’then the Receiver is enabled, else the UFC100-L2 ignores the receive activity. If ‘RE’is reset to
‘0’while a reception is active, then it cancels that reception and resets the Receiver.
RCL Receive cancel
If this field is set to ‘1’then the current reception is cancelled. It also clears error status and the receiver FIFO even if the
entire frame had been received in the FIFO. If the CPU sets RCL to ‘1’while Receiver is inactive, then the attempt to
write to this field is ignored. The read back of this field always returns ‘0’.

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JIE Jabber detection enable
If this field is set to ‘1’then jabber detection function is enabled. Jabber timer starts when RxA signal becomes active.
If this signal stays active for 4096 bit time (131 ms at 31.25kbps), jabber timer detects this and sets JI field in the Error
status register –see 2.2.8.
TRON Transmitter ON
Writing ‘1’to this field starts a transmission, which ends after sending the End Delimiter. This field is reset to ‘0’by the
UFC100-L2 at the end of the transmission. If the CPU resets this field to ‘0’during an active transmission, then the
transmission is aborted by sending the current byte, followed by wrong (inverted) FCS followed by End Delimiter and
the CPU attempt to write to the FIFO is ignored until the CPU resets transmission error status or TED status field. If the
CPU initiates the abort and no other error occurs then the completion is indicated by TED status.
IE Interrupt enable
If this field is set to ‘1’then all unmasked interrupts are used to activate INTn hardware signal.
2.2.6 Status
Address: 0x03
Reset value: 0x82 or 0x83
Table 7: UFC Status register
Status
Bit no. Name
7
ARDY
6
–
3
Not used
2
RFRY
1
TFRY
0
CD
ARDY Access ready
If this field is ‘1’, then the CPU can access the internal registers. If RDY hardware signal is used to control the access
cycle, then it is not necessary to check this status field.
RFRY Receive FIFO ready
If this field is ‘1’, then it indicates that there is at least one byte stored in the Receive FIFO.
TFRY Transmit FIFO ready
If this field is ‘1’, then it indicates that there is space for at least one more byte in the Transmit FIFO.
CD Carrier detect
If this field reflects the status of RxA input –‘1’indicates active carrier. In loopback, it shows the status of internal
RxA.
2.2.7 Interrupt status
Address: 0x04
Reset value: 0x00
This register shows the reason(s) for the interrupt. A ‘1’in a field indicates that the condition for that interrupt is active. If an
interrupt status is ‘1’and the corresponding condition is not masked (2.2.9) and IE field of Control register (see 2.2.5) is ‘1’,
then INTn hardware signal becomes low. Bits 1 through 6 of this register are automatically cleared when this register is read.
Bit 7 of this register (ERS) is cleared when Error status register is read.

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Table 8: UFC Interrupt status register
Interrupt status
Bit no.
Name
7
ERS
6
RTI
5
TED
4
RED
3
TFI
2
RFI
1
LCD
0
Not used
ERS Error condition
This field is inclusive OR of all unmasked fields in the Error status register.
RTI Watch-timer interrupt
This field is set to ‘1’when the Watch time counter reaches the value set in Watch time register. This field is not set to
‘1’if this field is masked in the Interrupt mask register. This interrupt can be used to find out if the bus is inactive for
more than the set duration.
TED Transmission end
This field is set to ‘1’when a frame transmission is successfully terminated or completed. If there is any error in the
transmission then this field is not set, but the corresponding error status is set to ‘1’.
RED Reception end
This field is set to ‘1’when a complete frame is received without any error and RE field of Control register is ‘1’. If the
frame is received with error then this field is not set, but the corresponding error status is set to ‘1’.
TFI Transmit FIFO indication
This field is set to ‘1’when the byte count in the Transmit FIFO decreases to reach the threshold value specified by
TCTRL field of FIFO control register (see 2.2.12). The ‘TFI’status becomes ‘1’only if the last byte of the current
transmission has not been read out of the FIFO. ‘TFI’is reset to ‘0’when Transmitter has read all bytes of the frame
from the FIFO and before it has transmitted FCS and End Delimiter. It is also reset when the CPU resets Transmit FIFO
using CTF command (see 2.2.12).
RFI Receive FIFO indication
This field is set to ‘1’when the byte count in the Receive FIFO increases to reach the threshold value specified by
RCTRL field of FIFO control register (see 2.2.12).
LCD Loss of carrier detect
This field is set to ‘1’when the RxA signal changes from HIGH to LOW and if this condition is not masked. This field
is not set if this condition is masked or if the internal loopback is enabled.
2.2.8 Error status
Address: 0x05
Reset value: 0x00
This register shows the reason(s) for the error interrupt. A ‘1’in a field indicates that the condition for that interrupt is active.
An inclusive OR of all unmasked conditions (see 0) is shown in the ERS field of the Interrupt status register. The error status
bits are automatically cleared when this register is read.
If at least one of FFER, RFR and NEPT fields is ‘1’, UFC cancels reception of the frame causing the error, in the same
manner as setting of RCL field of Control register to ‘1’, except that the Receive FIFO is not cleared. The error flag is set
when the error is detected, but further errors are not registered and the Receiver does not write any more bytes to the Receive
FIFO.

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Table 9: UFC Error status register
Error status
Bit no.
Name
7
FFER
6
JI
5
TLM
4
CNS
3
FCSE
2
Not used
1
RFR
0
NEPT
FFER FIFO error
This field is ‘1’when any error field in FIFO (RFOR, RFUR, TFOR or TFUR fields in FIFO Status register) is ‘1’.
JI Jabber
This field is set to ‘1’when the jabber timer reaches to 4096 bit time.
TLM Transmit length mismatch
This field is set to ‘1’when the CPU tries to write more bytes than the length of the frame set in the Transmit frame
length register –see 0.
CNS Carrier not seen
This field is set to ‘1’when UFC finishes transmission of Start Delimiter and RxA is not active at that moment. This
implies problem in driver/receiver circuit of the attached MAU.
FCSE FCS error
This field is set to ‘1’when FCS in the received frame is not equal to the calculated value.
RFR Receive framing error
This field is set to ‘1’when reception is enabled and any of the following error is detected during the reception:
·detection of N+ or N- code which is not a part of Start or End Delimiter, or
·End Delimiter is not on the byte boundary, or
·RxA is negated before End Delimiter is detected, or
·Start Delimiter is not detected and the receive activity ends after being active for more than 24 bit duration.
NOTE receive activity of 24 bit or smaller duration is considered as noise and ignored.
NEPT FIFO is not ready for a new frame
This error flag is set to ‘1’when the FC byte of the next frame is received and either the Receive FIFO is not empty or
receiver interrupt and error flags for the previous reception have not been reset to ‘0’. This new frame is lost.
2.2.9 Interrupt mask
Address: 0x06
Reset value: 0xFE
This register controls interrupts specified in Interrupt status register in the same order of interrupt reasons. When a field of
this register is set to ‘1’, then the corresponding interrupt in Interrupt status register is masked (does not affect the INTn
signal). When the CPU needs to receive any interrupt, corresponding field of this register should be cleared to ‘0’prior to
waiting for that interrupt. The ERS field of this register masks all error interrupts.

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Table 10: UFC Interrupt mask register
Interrupt mask
Bit no.
Name
7
ERS
6
RTI
5
TED
4
RED
3
TFI
2
RFI
1
LCD
0
Not used
2.2.10 Error mask
Address: 0x07
Reset value: 0xFB
This register controls error interrupts specified in Error status register in the same order of error reasons. When a field of this
register is set to ‘1’, then the corresponding error in Error status register is masked (does not affect the ERS bit in the
Interrupt status register). When the CPU needs to receive any error interrupt, corresponding fields of this register should be
cleared to ‘0’prior to waiting for the error interrupt.
Table 11: UFC Error mask register
Error mask
Bit no. Name
7
FFER
6
JI
5
TLM
4
CNS
3
FCSE
2
Not used
1
RFR
0
NEPT
2.2.11 Transmit frame length
Address: 0x08, 0x09
Reset value: 0x0000
This 10-bit register stores the length of the frame as number of bytes to be transferred from memory to the Transmit FIFO.
This count does not include Preamble, Start Delimiter and End Delimiter. The FCS is not included in this count, unless
transmission of FCS is disabled by TFCS. It is necessary to write a non-zero value to this register before transferring data to
the Transmit FIFO.
This register decrements by one when the CPU writes one byte into Transmit FIFO. If the CPU tries to write more bytes than
the value of Transmit length register then the extra bytes are not written to the Transmit FIFO. If the CPU does so after
TRON has been set to ‘1’, then the transmission is aborted and ‘TLM’is set to ‘1’. If the CPU does so before TRON has
been set to ‘1’, then the transmission is aborted when the CPU tries to set TRON to ‘1’and ‘TLM’is set to ‘1’at that time.
The CPU can read and write this register. When the CPU reads the lower byte of this register, the current value of the register
is not latched. If a transmission is active, then the reading of this register may not return correct value. The address 0x08
accesses the lower 8-bits of the frame length. The upper 6-bits at address 0x09 are read as zeros.

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2.2.12 FIFO control Register
Address: 0x0B
Reset value: 0x00
Table 12: UFC FIFO control register
FIFO control
Bit no.
Name
7
Not
used
6
CRF
5, 4
RCTRL
3
Not used
2
CTF
1, 0
TCTRL
CRF Clear Receive FIFO
Writing ‘1’to this field clears the Receive FIFO, its error status and the FIFO becomes empty. This field is
automatically reset to ‘0’by the UFC100-L2.
RCTRL Receive FIFO threshold
The value of this field sets the FIFO threshold that is used to set RFI field –see 2.2.7.
RCTRL Threshold
00 8 bytes,
01 16 bytes,
10 24 bytes,
11 32 bytes.
CTF Clear Transmit FIFO
Writing ‘1’to this field clears the Transmit FIFO, its error status and the FIFO becomes empty. It also resets Transmit
length register to zero. This field is automatically reset to ‘0’by the UFC100-L2.
TCTRL Transmit FIFO threshold
The value of this field sets the FIFO threshold that is used to set TFI field –see 2.2.7. The threshold value depends upon
TRON.
RCTRL Threshold
TRON = ‘0’TRON = ‘1’
00 4 bytes, 8 bytes,
01 8 bytes, 16 bytes,
10 16 bytes, 32 bytes,
11 24 bytes, 64 bytes.
Some of the software programs try to fill the Transmit FIFO before turning on the transmission by setting TRON to ‘1’.
The FIFO threshold is lower during this time, so that there is less delay in turning on the transmission.

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2.2.13 FIFO status
Address: 0x0C
Reset value: 0x11
This read only register shows the full, empty and error status of the FIFOs.
Table 13: UFC FIFO status register
FIFO status
Bit no. Name
7
RFOR
6
RFUR
5
RFF
4
RFE
3
TFOR
2
TFUR
1
TFF
0
TFE
RFOR Receive FIFO overrun
This field is set to ‘1’when Receive FIFO is full and another byte is received in the current reception. This field is reset
to ‘0’when the CPU writes ‘1’to CRF in FIFO control register.
RFUR Receive FIFO underrun
This field is set to ‘1’when Receive FIFO is empty and the CPU or DMA tries to read another byte from the Receive
FIFO. This field is reset to ‘0’when the CPU writes ‘1’to CRF in FIFO control register.
RFF Receive FIFO full
This field is ‘1’when Receive FIFO is full and ‘0’whenever there is at least one byte space in the FIFO.
RFE Receive FIFO empty
This field is ‘1’when Receive FIFO is empty and ‘0’whenever there is at least one byte in the FIFO.
TFOR Transmit FIFO overrun
This field is set to ‘1’when the Transmit FIFO is full and the CPU or DMA tries to write another byte to Transmit
FIFO. This field is reset to ‘0’when the CPU writes ‘1’to CTF in FIFO control register.
TFUR Transmit FIFO underrun
This field is set to ‘1’when the Transmit FIFO is empty and the UFC100-L2 tries to read another byte from the
Transmit FIFO to transmit the frame, or if the transmission is started and Transmit length register is zero. This field is
reset to ‘0’when the CPU writes ‘1’to CTF in FIFO control register.
TFF Transmit FIFO full
This field is ‘1’when the Transmit FIFO is full and ‘0’whenever there is at least one byte space in the FIFO.
TFE Transmit FIFO empty
This field is ‘1’when the Transmit FIFO is empty and ‘0’whenever there is at least one byte in the FIFO.
2.2.14 FIFO data
Address: 0x0D
Reset value: undefined, reads as 0x00
Write to this register appends one byte to Transmit FIFO. This FIFO is 8-bit wide and 128 bytes deep.
Read from this register removes one byte, if available, from Receive FIFO. This FIFO is 8-bit wide and 128 bytes deep.
The two FIFOs are separate, but share one address in the CPU address space.

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2.2.15 Clock mode
Address: 0x10
Reset value: 0x00
This register can be written and read.
Table 14: Clock mode register
Clock mode
Bit no. Name
7
–
3
Not used
2
NDE
1
GPE
0
Not used
NDE Node-timer enable
If this value is set to ‘1’, then the internal Node-time counter uses 32 kHz clock. Else, it uses 4 kHz clock.
GPE GAP-time enable
This sets the unit of the GAP-time register. If this value is set to ‘1’, then the unit is eight (8) bit time. Else, then the unit
is four (4) bit time.
2.2.16 Timer status
Address: 0x11
Reset value: 0x00
This read only register shows the Node-timer status.
Table 15: UFC Timer status register
Timer status
Bit no. Name
7
–
5
Not used
4
NTOF
3
–
0
Not used
NTOF Node-timer overflow
When Node-timer rolls over from the maximum value to zero, an internal overflow bit is set to ‘1’. Its value is latched
to this register at the same time when sixteen (16) bit Node-time register is latched by setting LTN bit of Timer control
register –see 2.2.21. This bit is automatically cleared to ‘0’when this register is read.
NOTE Multiple overflows cannot be detected by this register.
2.2.17 Node time
Address: 0x12, 0x13
Reset value 0x0000
This is a holding register that is used to read from and write to the internal Node-timer. Node-timer is an internal 16-bit up
counter which is reset to zeros by Reset. After Reset, it starts to count up and after reaching the maximum count, it rolls over
to zero.
The CPU has to write the lowest address byte (least significant value) first and then the highest address byte (most significant
value) to the Node-time register. If the CPU writes to the high address byte first then that write is ignored. If the CPU writes
low address byte and does not write high address byte, then holding register continues to wait. The value in the holding
register is written to the internal Node-timer immediately after the CPU has written the high address byte after the low
address byte.
Read of the internal Node-timer requires that the CPU first snap its value into Node-time register by writing ‘1’to LTN field
of the Timer control register (see 2.2.21). If snap command is received after the CPU has written the low address byte, but
before it has written the high address byte to the Node-time register, then the snap command is ignored.

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The counting frequency of this register depends upon the setting of ‘NDE’in Clock mode register - 2.2.15.
2.2.18 GAP time
Address: 0x14
Reset value 0xFF
This register stores the time to guarantee minimum gap between successive frames on the bus. It is used only when
transmitting a frame. The internal GAP timer starts whenever the bus becomes inactive and stops when it becomes equal to
the value set in GAP time register. When transmission is started by setting TRON bit of Control register, the transmission is
started only if the internal GAP timer has stopped. The unit of this register depends upon the setting of ‘GPE’in Clock mode
register - 2.2.15. The CPU can read back this register. The internal GAP timer itself cannot be read.
2.2.19 Watch time
Address: 0x16, 0x17
Reset value 0xFFFF
These registers hold threshold to detect “no activity”on the bus. UFC100-L2 has an internal Watch-time counter that is a
monotonously increasing counter and is reset by detecting Start Delimiter or End Delimiter in the RxS signal. When the
content of Watch-time counter reaches the value set in Watch time register and if RTI is not masked, RTI interrupt status is
set to ‘1’. The Watch-time counter is reset whenever the bus is active. This counter is also reset by setting CT bit of Timer
control register (see 2.2.21). The unit of this register is eight (8) bit time.
The address 0x16 accesses the lower 8-bits of the Watch time threshold.
The CPU can read back these registers. The internal Watch-time counter itself cannot be read.
2.2.20 Token counter
Address: 0x18, 0x19
Reset value 0x0000
These registers are used to read the value from or write the value to the internal Token-time counter. The internal counter is a
16-bit down counter. It is reset to zero at the start of UFC100-L2 operation. Whenever it has non-zero value, it counts down
once every byte time –transmission duration of one byte. It stops count down at zero value.
The content of the internal Token-time counter is latched to these registers when LTR bit of Timer control register (see
2.2.21) is set.
The content of these registers are loaded to the internal Token-time counter when any data is written to higher byte register
($19). This implies lower byte ($18) should be written first. It is also loaded from the received PT frame.
2.2.21 Timer control
Address: 0x1A
Reset value 0x00
This write-only register is used to control various internal timers and counters. Read of this register returns 0x00.
Table 16: UFC Timer control register
Timer control
Bit no.
Name
7
Not used
6
LTN
5
LTR
4
–
2
Not used
1
CT
0
Not used
LTN Latch Node-timer
Writing ‘1’to this field snaps the value of the internal Node-time counter into Node-time register –address 0x12, 0x13.

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LTR Latch Token-timer
Writing ‘1’to this field snaps the value of the internal Token-time counter into Token counter register –address 0x18,
0x19.
CT Clear Watch-timer
Writing ‘1’to this field clears the internal Watch-time counter to zero.