Arnewsh SBC5204 User manual

SBC5204 USER'S MANUAL
REVISION 1.1
Copyright 1996, 1997 Arnewsh Inc.
Arnewsh Inc.
P.O. Box 270352
Fort Collins, CO 80527-0352
Phone: [phone]
Fax: [phone]

iii
COPYRIGHT
Copyright 1996, 1997 by Arnewsh Inc.
All rights reserved. No part of this manual and the dBUG software provided in Flash ROM’s/EPROM’s
may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic,
mechanical, photocopying, recording, or otherwise. Use of the program or any part thereof, for any
purpose other than single end user by the purchaser is prohibited.
DISCLAIMER
The information in this manual has been carefully examined and is believed to be entirely reliable.
However, no responsibility is assumed for inaccuracies. Furthermore, Arnewsh reserves the right to make
changes to any product(s) herein to improve reliability, function, or design. The SBC306 board is not
intended for use in life and/or property critical applications. Here, such applications are defined to be any
situation in which any failure, malfunction, or unintended operation of the board could, directly, or
indirectly, threaten life, result in personal injury, or cause damage to property. Although every effort has
been made to make the supplied software and its documentation as accurate and functional as possible,
Arnewsh Inc. will not assume responsibility for any damages incurred or generated by this product.
Arnewsh does not assume any liability arising out of the application or use of any product or circuit
described herein, neither does it convey any license under its patent rights, if any, or the rights of others.
WARNING
THIS BOARD GENERATES, USES, AND CAN RADIATE
RADIO FREQUENCY ENERGY AND, IF NOT INSTALLED
PROPERLY, MAY CAUSE INTERFERENCE TO RADIO
COMMUNICATIONS. AS TEMPORARILY PERMITTED
BY REGULATION, IT HAS NOT BEEN TESTED FOR
COMPLIANCE WITH THE LIMITS FOR CLASS A
COMPUTING DEVICES PURSUANT TO SUBPART J OF
PART 15 OF FCC RULES, WHICH ARE DESIGNED TO
PROVIDE REASONABLE PROTECTION AGAINST SUCH
INTERFERENCE. OPERATION OF THIS PRODUCT IN A
RESIDENTIAL AREA IS LIKELY TO CAUSE
INTERFERENCE, IN WHICH CASE THE USER, AT
HIS/HER OWN EXPENSE, WILL BE REQUIRED TO
CORRECT THE INTERFERENCE.

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LIMITED WARRANTY
Arnewsh Inc. warrants this product against defects in material and workmanship for a period of
sixty (60) days from the original date of purchase. This warranty extends to the original
customer only and is in lieu of all other warrants, including implied warranties of
merchantability and fitness. In no event will the seller be liable for any incidental or
consequential damages. During the warranty period, Arnewsh will replace, at no charge,
components that fail, provided the product is returned (properly packed and shipped prepaid) to
Arnewsh at address below. Dated proof of purchase (such as a copy of the invoice) must be
enclosed with the shipment. We will return the shipment prepaid via UPS.
This warranty does not apply if, in the opinion of Arnewsh Inc., the product has been damaged by
accident, misuse, neglect, misapplication, or as a result of service or modification (other than
specified in the manual) by others.
Please send the board and cables with a complete description of the problem to:
Arnewsh Inc.
P.O. Box 270352
Fort Collins, CO 80527-0352
Phone: [phone]
Fax : [phone]
Motorola is a registered trademark of Motorola Inc.
IBM PC and IBM AT are registered trademark of IBM Corp.
All other trademark names mentioned in this manual are the registered trade mark repective
owners.

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TABLE OF CONTENTS
Page
CHAPTER 1 INTRODUCTION TO THE SBC5204 BOARD ................ 1-1
1.1 INTRODUCTION ...................................... 1-1
1.2 GENERAL HARDWARE DESCRIPTION ...................... 1-1
1.3 SYSTEM MEMORY ..................................... 1-3
1.4 SERIAL COMMUNICATION CHANNELS ..................... 1-3
1.5 PARALLEL I/O PORTS ................................ 1-3
1.6 PROGRAMMABLE TIMERS/COUNTERS ...................... 1-3
1.7 ISA BUS CONNECTOR.................................. 1-3
1.8 SYSTEM CONFIGURATION .............................. 1-4
1.9 INSTALLATION AND SETUP ............................ 1-4
1.9.1 Unpacking ..................................... 1-4
1.9.2 Preparing the Board for Use ................... 1-4
1.9.3 Providing Power to the Board .................. 1-4
1.9.4 Selecting Terminal Baud Rate .................. 1-5
1.9.5 The Terminal Character Format ................. 1-5
1.9.6 Connecting the Terminal ....................... 1-5
1.9.7 Using Personal Computer as a Terminal ......... 1-5
1.10 SYSTEM POWER-UP AND INITIAL OPERATION ............. 1-9
1.11 SBC5204 JUMPER SETUP............................... 1-9
1.12 USING THE BDM ..................................... 1-10
CHAPTER 2 USING THE MONITOR/DEBUG FIRMWARE ............... 2-1
2.1 WHAT IS dBUG....................................... 2-1
2.2 OPERATIONAL PROCEDURE ............................. 2-3
2.2.1 System Power-up ............................... 2-3
2.2.2 System Initialization ......................... 2-3
2.2.2.1 RESET Button ............................. 2-4
2.2.2.2 ABORT Button ............................. 2-4
2.2.2.3 Software Reset Command ................... 2-4
2.2.2.4 User Program ............................. 2-4
2.2.3 System Operation .............................. 2-4
2.3 TERMINAL CONTROL CHARACTERS ....................... 2-5
2.4 dBUG COMMAND SET .................................. 2-5
2.4.1 BF - Block Memory Fill ........................ 2-7
2.4.2 BM - Block Move ............................... 2-8
2.4.3 BR - Breakpoint ............................... 2-9
2.4.4 BS - Block Search ...... ...................... 2-10
2.4.5 DATA - Data Conversion ........................ 2-11
2.4.6 DI - Disassemble .............................. 2-12
2.4.7 DL - Download Serial .......................... 2-13
2.4.8 DN - Download Network.......................... 2-14
2.4.9 Go - Execute .................................. 2-15
2.4.10 GT - Execute Till a Temporary Breakpoint ...... 2-16
2.4.11 Help - Help ................................... 2-17
2.4.12 IRD - Internal Registers Display .............. 2-18
2.4.13 IRM - Internal Registers Modify ............... 2-19
2.4.14 MD - Memory Display ........................... 2-20
2.4.15 MM - Memory Modify ............................ 2-21

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2.4.16 RD - Register Display ......................... 2-22
2.4.17 RM - Register Modify .......................... 2-23
2.4.18 RESET - Reset the board and dBUG .............. 2-24
2.4.19 SET - Set Configuration ....................... 2-25
2.4.20 SHOW - Show Configuration ..................... 2-27
2.4.21 STEP - Step Over .............................. 2-28
2.4.22 SYMBOL - Symbol Name Management ............... 2-29
2.4.23 TRACE - Trace Into ............................ 2-30
2.4.24 UPDBUG - Update the dBUG Image ................ 2-31
2.4.25 UPUSER - Update User Code In Flash ............ 2-32
2.4.26 VERSION - Display dBUG Version ................ 2-33
2.5 TRAP #15 Functions ................................ 2-34
2.5.1 OUT_CHAR ...................................... 2-34
2.5.2 IN_CHAR ....................................... 2-34
2.5.3 CHAR_PRESENT .................................. 2-35
2.5.4 EXIT_TO_dBUG .................................. 2-35
CHAPTER 3 HARDWARE DESCRIPTION AND RECONFIGURATION ....... 3-1
3.1 THE PROCESSOR AND SUPPORT LOGIC ................... 3-1
3.1.1 The Processor ................................. 3-1
3.1.2 The Reset Logic ............................... 3-1
3.1.2.1 The ATS/BUSW Line ......................... 3-2
3.1.3 The Clock Circuitry ........................... 3-2
3.1.4 Watchdog Timer (BUS MONITOR) .................. 3-2
3.1.5 Interrupt Sources ............................. 3-2
3.1.6 Internal SRAM ................................. 3-3
3.1.7 The MCF5204 Registers and Memory Map .......... 3-3
3.1.8 Reset Vector Mapping .......................... 3-4
3.1.9 DTACK Generation .............................. 3-4
3.1.10 Wait State Generator .......................... 3-5
3.2 THE EXTERNAL SRAM ................................. 3-5
3.3 THE EPROM/FLASH ROM ............................... 3-5
3.4 THE UART LOGIC .................................... 3-7
3.4.1 MC68HC901 ..................................... 3-7
3.5 THE PARALLEL I/O PORT.............................. 3-7
3.6 THE ISA BUS LOGIC ................................. 3-7
3.7 THE CONNECTORS AND THE EXPANSION BUS .............. 3-8
3.7.1 The Terminal Connector J1 ..................... 3-8
3.7.2 The ISA Bus Auxiliary Connector J2 ............ 3-8
3.7.3 The Power Supply Connector J3 and J4 .......... 3-9
3.7.4 The Programming Connector J5 .................. 3-9
3.7.5 The Auxiliary Communication Connector J6 ...... 3-10
3.7.6 The Debug Connector J7 ........................ 3-10
3.7.7 The Processor Expansion Bus J8 and J9 ......... 3-10
3.7.8 The ISA Bus Connector P1 ...................... 3-13
3.8 THE SBC5204 JUMPERS ................................ 3-15
APPENDIX A NETWORK DOWNLOAD .............................. A-1
A.1 Configuring dBUG for Network Downloads ............. A-1

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A.1.1 Required Network Parameters ................... A-1
A.1.2 Configuring dBUG Network Parameters ........... A-2
A.1.3 Troubleshooting Network Problems .............. A-2

1
CHAPTER 1
INTRODUCTION TO THE SBC5204 BOARD
1.1 INTRODUCTION
The SBC5204 is a versatile single board computer based on MCF5204 ColdFire Processor. It may be used
as a powerful microprocessor based controller in a variety of applications. With the addition of a terminal,
it serves as a complete microcomputer for development/evaluation, training and educational use. The user
must only connect an RS-232 compatible terminal (or a personal computer with terminal emulation
software) and a power supply to have a fully functional system.
Provisions have been made to connect this board to additional user supplied boards, via the Microprocessor
Expansion Bus connectors, to expand memory and I/O capabilities. Additional boards may require bus
buffers to permit additional bus loading.
Furthermore, provisions have been made in the PC-board to permit configuration of the board in a way
which best suits an application. Options available are: 1M of SRAM, Timer, I/O, ISA bus interface, and
up to 1M bytes of Flash or 2M bytes of EPROM. In addition, all of the I/O functions of the MCF5204 are
available for the user.
1.2 GENERAL HARDWARE DESCRIPTION
The SBC5204 board provides the RAM, Flash ROM, optional Ethernet interface (ISA bus), RS232, and
all the built-in I/O functions of the MCF5204 for learning and evaluating the attributes of the MCF5204.
The MCF5204 is a member of the ColdFire family of processors. It is a 32-bit processor with 32 bits of
addressing and 32 lines of data. The processor has eight 32-bit data registers, 8 32-bit address registers, a
32-bit program counter, and a 16-bit status register.
The MCF5204 has a System Integration Module referred to as SIM. The module incorporate many of the
functions needed for system design. These include programmable chip-select logic, System Protection
logic, General purpose I/O, and Interrupt controller logic. The chip-select logic can select up to six
memory banks or peripherals. The chip-select logic also allows programmable number of wait-state to
allow the use of slower memory (refer to MCF5204 User's Manual by Motorola for detail information
about the SIM.) The SBC5204 dBUG monitor only uses five of the chip selects to access the Flash
ROM’s, one bank of SRAM’s, MC68HC901, and ISA bus interface. All other functions of the SIM are
available to the user.
A hardware watchdog timer (Bus Monitor) circuit is included in the SIM which monitors the bus activities.
If a bus cycle is not terminated within a programmable time, the watchdog timer will assert an internal
transfer error signal to terminate the bus cycle. A block diagram of the board is shown in Figure 1.1.

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XCEIVERS
MC68HC901
Flash ROM/
EPROM
SRAM
Data and
Address
Xceivers
LSI2032
MCF5204
ISA
BUS
RS232
Figure 1.1
P1
U13,U14
U8
U11, U12
U7
I/O PORTS
ADDRESS BUS
DATA BUS
CONTROL BUS

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1.3 SYSTEM MEMORY
There are two 32-pin sockets on the board for EPROM’s or Flash ROM’s (U13, U14), U13 is the most
significant byte and the U14 is the least significant byte. The EPROM sockets can be set up via jumpers
(JP2, JP3, and JP4) to accept 27C256, 27C512, 27C010, 27C020, 27C040, and 27C080 EPROM’s. or
29F010, and 29F040. The SBC5204 comes with two 29F010 Flash ROM’s which are programmed with
a debugger/monitor firmware. The dBUG driver only supports 29F010 Flash ROM.
There are two 32-pin sockets for SRAM’s which can accept 128Kx8 and 512Kx8 SRAM’s. JP2 is used to
make the selection.
1.4 SERIAL COMMUNICATION CHANNELS
The MCF5204 has one built-in Serial Communication Channel with baud rate generator. This signals of
this channel are passed through external Driver/Receivers to make the channel compatible with RS-232.
This channel is not used by the debugger and is available to user. The SBC5204, however, has one
MC68HC901 which has four timers and a serial communication port. One timer channel is used as baud
rate generator for the serial channel. The RXD and TXD lines are passed through external Driver/Receiver
to make this channel compatible with RS-232C level (Note: only 2 main signals are available, RXD and
TXD signals). This channel is the “TERMINAL” channel used by the debugger for communication with
external terminal/PC.
1.5 PARALLEL I/O PORTS
Some of the multifunction pins of the MCF5204 can be used as Port A general purpose I/O pins. These
pins are available to user except A20/PA0 which may be used for EPROM selection when using 8M
EPROM’s.
1.6 PROGRAMMABLE TIMER/COUNTER
The MCF5204 has two built in general purpose timer/counters. These timers are not used by the debugger
and are available to the user. The signals for the timer share the pins with Port A and are available on the
connector J9. There are also three timers in MC68HC901 which are available to user.
1.7 ISA BUS CONNECTOR
The SBC5204 has one ISA bus connector to allow the use of off-the-shelf ISA I/O cards. The main reason
for this connector is to install an Ethernet card to support down-load via network.
1.8 SYSTEM CONFIGURATION
The SBC5204 board requires only the following items for minimum system configuration (Fig. 1.2):
a. The SBC5204 board (provided).
b. Power supply ( +5 Vdc regulated or 7.5V to 12V DC), about 0.5 Amp.
c. RS-232C compatible terminal or a PC with terminal emulation software.

4
d. Communication cable (provided).
Refer to next sections for initial setup.
1.9 INSTALLATION AND SETUP
The following sections describe all the steps needed to prepare the board for operation. Please read the
following sections carefully before using the board. When you are preparing the board for the first time, do
not use the optional features (Ethernet, ISA BUS). The minimum configuration does not require any
modifications. After the board is functional in its minimal configuration, you may use other features by
following the instructions provided in the following sections.
1.9.1 Unpacking
Unpack the computer board from its shipping box. Save the box for storing or reshipping. Refer to the
following list and verify that all the items are present. You should have received:
a. SBC5204 Single Board Computer.
b. SBC5204 User's Manual, this documentation.
c. One communication cable.
WARNING
AVOID TOUCHING THE MOS DEVICES. STATIC DISCHARGE
CAN AND WILL DAMAGE THESE DEVICES.
Once you verified that all the items are present, remove the board from its protective jacket. Check the
board for any visible damage. Ensure that there are no broken, damaged, or missing parts. If you have not
received all the items listed above or they are damaged, please contact Arnewsh Inc. immediately in order
to correct the problem.
1.9.2 Preparing the Board for Use
The board as shipped is ready to be connected to a terminal and the power supply without any need for
modification. However, follow the steps below to insure proper operation from the first time you apply the
power. Figure 1.3 shows the placement of the jumpers and the connectors which you need to refer to in the
following sections. The steps to be taken are:
a. Connecting the power supply.
b. Connecting the terminal.
1.9.3 Providing Power to the Board
The board accepts two means of power supply connections. Connector J3 is a 2.1mm power jack and J4
lever actuated connector. The board accepts either +5V regulated supply or +7.5V to 12V DC (regulated
or unregulated), less than one Amp via either connectors. Jumper JP1 selects between +5 and +7.5-12V

5
options. Make sure the jumper JP1 is in proper location for your option. Connect power supply as
marked on the board and shown below (do not turn the power supply on yet):
Contact NO. Voltage
1 +5 Vdc or +7.5-12V
2 Ground
Jumper JP1.
Jumper Pin Function
1 and 2 +5V regulated
2 and 3 +7.5-12V DC, regulated or unregulated (default)
1.9.4 Selecting Terminal Baud Rate
The serial channel of MC68HC901 which is used for serial communication channel has a built in software
programmable baud rate generator (timer). It can be programmed to a number of baud rates. After the
power-up or a manual RESET, the dBUG firmware configures the channel for 19200 baud. After the
dBUG is running, you may issue the SET command to choose any baud rate supported by the dBUG.
Refer to Chapter 2 for the discussion of this command.
1.9.5 The Terminal Character Format
The character format of the communication channel is fixed at the power-up or RESET. The character
format is 8 bits per character, no parity, and one stop bit. You need to insure that your terminal or PC is
set to this format.
1.9.6 Connecting the Terminal
The board is now ready to be connected to a terminal. Use the communication cable provided to connect
the terminal to the SBC5204. The cable has a 9-pin female D-sub connector at one end and a 9-pin male
D-sub connector at the other end. Attach the 9-pin male connector to J1 connector on the board. Attach
the 9-pin female connector to a 9-pin-to-25-pin adapter, if necessary, to make it compatible with the
connector on the back of the terminal.
1.9.7 Using a Personal Computer as a Terminal
You may use your personal computer as a terminal provided you also have a terminal emulation software
such as PROCOMM, KERMIT, QMODEM, or similar packages. Use the communication cable provided
to connect the PC to the SBC5204. The cable has a 9-pin female D-sub connector at one end and a 9-pin
male D-sub connector at the other end. Connect the 9-pin male connector to J1 connector on SBC5204.
Connect the 9-pin female connector to one of the available serial communication channels normally referred
to as COM1 (COM2, etc.) on the IBM PC’s or compatible. Depending on the kind of serial connector on
the back of your PC, the connector on your PC may be a male 25-pin or 9-pin. You may need to obtain a
9-pin-to-25-pin adapter to make the connection. If you need to build an adapter, refer to Figure 1.4 which
shows the pin assignment for the 9-pin connector on the board.

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ISA BUS
SBC5204
+5, GND
Power Supply
MICROPROCESSOR
EXPANSION BUS
BACKGROUND DEBUG
P1
J1
J6
J7 J8
J9
RS232 TERMINAL
or PC
dBUG>
Figure 1.2. System Configuration
J3
J4

7
Once the connection to the PC is made, you are ready to power-up the PC and run the terminal emulation
software. When you are in the terminal mode, you need to select the baud rate and the character format for
the channel. Most terminal emulation software packages provide a command known as "Alt-p" (press the p
key while pressing the Alt key) to choose the baud rate and character format. Make sure you select 8 bits,
no parity, one stop bit (see Section 1.9.5). Then, select the baud rate as 19200. Now you are ready to
apply power to the board.
1.Data Carrier Detect, Output (shorted to pins 6 and 8).
2. Receive Data, Output from board (receive refers to terminal side).
3. Transmit Data, Input to board (transmit refers to terminal side).
4. Data Terminal Ready, input (not used).
5. Signal Ground.
6. Data Set Ready, Output (shorted to pins 1 and 8).
7. Request to Send, input.
8. Clear to send, output (shorted to pins 1 and 6).
9. Not connected.
Figure 1.4. Pin assignment for the J1 (Terminal) connector.

8
P1
J1
J1
J6
J7 J8
J9
JP3
JP2
JP1
J4
J3
J2
JP4
Figure 1.3. Jumper and connector placement.

9
1.10 SYSTEM POWER-UP AND INITIAL OPERATION
Now that you have connected all the cables, you may apply power to the board. After power is applied, the
dBUG initializes the board then displays the power-up message on the terminal which includes the amount
of the memory present.
Hard Reset
Installed SRAM: 256K
Copyright 1995-1996 Motorola, Inc. All Rights Reserved.
ColdFire MCF5204 EVS Debugger V2.1 (Aug xx 1996 xx:xx:xx:)
Enter ‘help’ for help.
dBUG>
The board is now ready for operation under the control of the debugger as described in Chapters 2. If you
do not get the above response, perform the following checks:
1. Make sure that the power supply is properly set and connected to the board.
2. Check that the terminal and board are set for the same character format and baud.
3. Press the red RESET (red switch) button to insure that the board has been initialized
properly.
If you still are not receiving the proper response, your board may have been damaged in shipping. Contact
Arnewsh for further instructions.
1.11 SBC5204 JUMPER SETUP
The jumpers on the board are discussed in Chapter 3. However, a brief discussion of the jumper settings
are as follows:
1. Jumper JP1. This jumper selects the power supply selection.
Jumper Pin Function
1 and 2 +5V regulated.
2 and 3 +7.5-12V DC regulated or unregulated (default)

10
2. Jumper JP2. This jumper selects the SRAM size and EPROM Size.
Jumper Pin Function
2 to 4 Selects 128Kx8 SRAM (default)
1 to 3 Selects 128Kx8 Flash Memory (default)
3. Jumper JP3. This jumper selects between Flash and EPROM.
Jumper Pin Function
3 to 5
and
4 to 6
Select Flash (default)
4. Jumper JP4. This jumper selects the size of EPROM or Flash.
Jumper Pin Function
7 to 9
and
8 to 10
Selects 128Kx8 EPROM/Flash
1.12 USING THE BDM
The MCF5204 has a built in debug mechanism referred to as BDM. The SBC5204 has the necessary
connector, J7, to facilitate this connection.
In order to use the BDM, simply connect the 26-pin IDC header at the end of the BDM cable provided by
the BDM development tool (third party tool) to the J7 connector. No special setting is needed. Refer to the
BDM User's Manual for additional instructions.

1
CHAPTER 2
USING THE MONITOR/DEBUG FIRMWARE
The SBC5204 Computer Board has a resident firmware package that provides a self-contained
programming and operating environment. The firmware, named dBUG, provides the user with
monitor/debug, disassembly, program download, and I/O control functions. This Chapter is a how-to-use
description of the dBUG package, including the user interface and command structure.
2.1 WHAT IS dBUG?
dBUG is a resident firmware package for the ColdFire family Computer Boards. The firmware (stored in
two 128Kx8 Flash ROM devices) provides a self-contained programming and operating environment.
dBUG interacts with the user through pre-defined commands that are entered via the terminal.
The user interface to dBUG is the command line. A number of features have been implemented to achieve
an easy and intuitive command line interface.
dBUG assumes that an 80x24 character dumb-terminal is utilized to connect to the debugger. For serial
communications, dBUG requires eight data bits, no parity, and one stop bit, 8N1. The baud rate is 19200
but can be changed after the power-up.
The command line prompt is “dBUG> “. Any dBUG command may be entered from this prompt. dBUG
does not allow command lines to exceed 80 characters. Wherever possible, dBUG displays data in 80
columns or less. dBUG echoes each character as it is typed, eliminating the need for any “local echo” on
the terminal side.
In general, dBUG is not case sensitive. Commands may be entered either in upper or lower case, depending
upon the user’s equipment and preference. Only symbol names require that the exact case be used.
Most commands can be recognized by using an abbreviated name. For instance, entering “h” is the same
as entering “help”. Thus, it is not necessary to type the entire command name.
The commands DI, GO, MD, STEP and TRACE are used repeatedly when debugging. dBUG recognizes
this and allows for repeated execution of these commands with minimal typing. After a command is
entered, simply press <RETURN> or <ENTER> to invoke the command again. The command is executed
as if no command line parameters were provided.
An additional function called the "TRAP 15 handler" allows the user program to utilize various routines
within dBUG. The TRAP 15 handler is discussed at the end of this chapter.
The operational mode of dBUG is demonstrated in Figure 2-1. After the system initialization, the board
waits for a command line input from the user terminal. When a proper command is entered, the operation
continues in one of the two basic modes. If the command causes execution of the user program, the dBUG
firmware may or may not be re-entered, depending on the discretion of the user. For the alternate case, the
command will be executed under control of the dBUG firmware, and after command completion, the system
returns to command entry mode.

2
Figure 2-1. Flow Diagram of dBUG Operational Mode.

3
During command execution, additional user input may be required depending on the command function.
For commands that accept an optional <width> to modify the memory access size, the valid values are:
.B 8-bit (byte) access
.W 16-bit (word) access
.L 32-bit (long) access
When no <width> option is provided, the default width is .W, 16-bit.
The core ColdFire register set is maintained by dBUG. These are listed below:
A0-A7
D0-D7
PC
SR
All control registers on ColdFire are not readable by the supervisor programming model, and thus not
accessible via dBUG. User code may change these registers, but caution must be exercised as changes may
render dBUG useless.
A reference to “SP” actually refers to “A7”.
2.2 OPERATIONAL PROCEDURE
System power-up and initial operation are described in detail in Chapter 1. This information is repeated
here for convenience and to prevent possible damage.
2.2.1 System Power-up
a. Be sure the power supply is connected properly prior to power-up.
b. Make sure the terminal is connected to TERMINAL (J1) connector.
c. Turn power on to the board.
2.2.2 System Initialization
The act of powering up the board will initialize the system. The processor is reset and dBUG is invoked.
dBUG performs the following configurations of internal resources during the initialization. The instruction
cache is invalidated and disabled. The Vector Base Register, VBR, points to the Flash. However, a copy
of the exception table is made at address $00000000 in SRAM. To take over an exception vector, the user
places the address of the exception handler in the appropriate vector in the vector table located at
0x00000000, and then points the VBR to 0x00000000.
The Software Watchdog Timer is disabled, Bus Monitor enabled, and internal timers are placed in a stop
condition. Interrupt controller registers initialized with unique interrupt level/priority pairs. The Port A
general purpose I/O pins are configured for dedicated peripheral functions, i.e. the UART.

4
After initialization, the terminal will display:
Hard Reset
Installed SRAM: 256K
Copyright 1995-1996 Motorola, Inc. All Rights Reserved.
ColdFire MCF5204 EVS Debugger V2.1 (Aug xx 1996 xx:xx:xx:)
Enter ‘help’ for help.
dBUG>
If you did not get this response check the setup. Refer to Section 1.10. Note, the date
‘Aug xx 1996 xx:xx:xx’ may vary in different revisions.
Other means can be used to re-initialize the SBC5204 Computer Board firmware. These means are
discussed in the following paragraphs.
2.2.2.1 RESET Button.RESET is the red button located in the middle side of the board. Depressing this
button causes all processes to terminate, resets the MCF5204 processor and board logic’s and restarts the
dBUG firmware. Pressing the RESET button would be the appropriate action if all else fails.
2.2.2.2 ABORT Button.ABORT is the black button located next to RESET button in the middle side of
the board. The abort function causes an interrupt of the present processing (a level 7 interrupt on
MCF5204) and gives control to the dBUG firmware. This action differs from RESET in that no processor
register or memory contents are changed, the processor and peripherals are not reset, and dBUG is not
restarted. Also, in response to depressing the ABORT button, the contents of the MCF5204 core internal
registers are displayed.
The abort function is most appropriate when software is being debugged. The user can interrupt the
processor without destroying the present state of the system.
2.2.2.3 Software Reset Command. dBUG does have a command that causes the dBUG to restart as if a
hardware reset was invoked. The command is "RESET".
2.2.2.4 USER Program.The user can return control of the system to the firmware by recalling dBUG via
his/her program. Instructions can be inserted into the user program to call dBUG via the TRAP 15
handler.
2.2.3 System Operation
After system initialization, the terminal will display:
Hard Reset
Installed SRAM: 256K
Copyright 1995-1996 Motorola, Inc. All Rights Reserved.
ColdFire MCF5204 EVS Debugger V2.1 (Aug xx 1996 xx:xx:xx:)
Enter ‘help’ for help.
dBUG>