Arnewsh SBC5307 User manual

SBC5307 USER'S MANUAL
REVISION 2.0
Copyright 1998 Arnewsh Inc.
Arnewsh Inc.
P.O. Box 270352
Fort Collins, CO 80527-0352
Phone: [phone]
Fax: [phone]

iii
COPYRIGHT
Copyright 1998 by Arnewsh Inc.
All rights reserved. No part of this manual and the dBUG software provided in Flash ROM’s/EPROM’s
may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic,
mechanical, photocopying, recording, or otherwise. Use of the program or any part thereof, for any
purpose other than single end user by the purchaser is prohibited.
DISCLAIMER
The information in this manual has been carefully examined and is believed to be entirely reliable.
However, no responsibility is assumed for inaccuracies. Furthermore, Motorola reserves the right to make
changes to any product(s) herein to improve reliability, function, or design. The LAB5307rev2 board is
not intended for use in life and/or property critical applications. Here, such applications are defined to be
any situation in which any failure, malfunction, or unintended operation of the board could, directly, or
indirectly, threaten life, result in personal injury, or cause damage to property. Although every effort has
been made to make the supplied software and its documentation as accurate and functional as possible,
Motorola Inc. will not assume responsibility for any damages incurred or generated by this product.
Motorola does not assume any liability arising out of the application or use of any product or circuit
described herein, neither does it convey any license under its patent rights, if any, or the rights of others.
WARNING
THIS BOARD GENERATES, USES, AND CAN RADIATE
RADIO FREQUENCY ENERGY AND, IF NOT INSTALLED
PROPERLY, MAY CAUSE INTERFERENCE TO RADIO
COMMUNICATIONS. AS TEMPORARILY PERMITTED
BY REGULATION, IT HAS NOT BEEN TESTED FOR
COMPLIANCE WITH THE LIMITS FOR CLASS A
COMPUTING DEVICES PURSUANT TO SUBPART J OF
PART 15 OF FCC RULES, WHICH ARE DESIGNED TO
PROVIDE REASONABLE PROTECTION AGAINST SUCH
INTERFERENCE. OPERATION OF THIS PRODUCT IN A
RESIDENTIAL AREA IS LIKELY TO CAUSE
INTERFERENCE, IN WHICH CASE THE USER, AT
HIS/HER OWN EXPENSE, WILL BE REQUIRED TO
CORRECT THE INTERFERENCE.
LIMITED WARRANTY

iv
Arnewsh Inc. warrants this product against defects in material and workmanship for a period of
sixty (60) days from the original date of purchase. This warranty extends to the original
customer only and is in lieu of all other warrants, including implied warranties of
merchantability and fitness. In no event will the seller be liable for any incidental or
consequential damages. During the warranty period, Arnewsh will replace, at no charge,
components that fail, provided the product is returned (properly packed and shipped prepaid) to
Arnewsh at address below. Dated proof of purchase (such as a copy of the invoice) must be
enclosed with the shipment. We will return the shipment prepaid via UPS.
This warranty does not apply if, in the opinion of Arnewsh Inc., the product has been damaged by
accident, misuse, neglect, misapplication, or as a result of service or modification (other than
specified in the manual) by others.
Please send the board and cables with a complete description of the problem to:
Arnewsh Inc.
P.O. Box 270352
Fort Collins, CO 80527-0352
Phone: [phone]
Fax : [phone]
Motorola is a registered trademark of Motorola Inc.
IBM PC and IBM AT are registered trademark of IBM Corp.
ALL OTHER TRADEMARK NAMES MENTIONED IN THIS MANUAL ARE THE
REGISTERED TRADE MARK OF RESPECTIVE OWNERS.

v
................................................... TABLE OF CONTENTS
CHAPTER 1......................................................................................................................................................1-1
1.1 INTRODUCTION ............................................................................................................................... 1-1
1.2 GENERAL HARDWARE DESCRIPTION.......................................................................................... 1-1
1.3 SYSTEM MEMORY........................................................................................................................... 1-3
1.4 SERIAL COMMUNICATION CHANNELS........................................................................................ 1-3
1.5 PARALLEL I/O PORTS...................................................................................................................... 1-3
1.6 PROGRAMMABLE TIMER/COUNTER ............................................................................................ 1-3
1.7 ON BOARD ETHERNET.................................................................................................................... 1-4
1.8 SYSTEM CONFIGURATION............................................................................................................. 1-4
1.9 INSTALLATION AND SETUP........................................................................................................... 1-4
1.9.1. Unpacking ................................................................................................................................... 1-4
1.9.2. Preparing the Board for Use........................................................................................................ 1-5
1.9.3. Providing Power to the Board...................................................................................................... 1-5
1.9.4. Selecting Terminal Baud Rate...................................................................................................... 1-5
1.9.5. The Terminal Character Format .................................................................................................. 1-5
1.9.6. Connecting the Terminal.............................................................................................................. 1-5
1.9.7. Using a Personal Computer as a Terminal................................................................................... 1-6
1.10 SYSTEM POWER-UP AND INITIAL OPERATION.......................................................................... 1-9
1.11 SBC5307 JUMPER SETUP ...................................................................................................................... 1-9
1.11.1. Jumper JP1- Flash Upper Half/Lower Half Boot.......................................................................... 1-9
1.11.2. Jumper JP2 - This jumper selects between /CS0 to Flash or a header......................................... 1-10
1.12 USING THE BDM ............................................................................................................................ 1-10
CHAPTER 2......................................................................................................................................................2-1
2.1 WHAT IS DBUG?................................................................................................................................ 2-1
2.2 OPERATIONAL PROCEDURE.......................................................................................................... 2-2
2.2.1. System Power-up.......................................................................................................................... 2-2
2.2.2. System Initialization..................................................................................................................... 2-4
2.2.2.1. Hard RESET Button. ...........................................................................................................................2-4
2.2.2.2. ABORT Button....................................................................................................................................2-4
2.2.2.3. Software Reset Command....................................................................................................................2-4
2.2.2.4. USER Program....................................................................................................................................2-5
2.2.3. System Operation......................................................................................................................... 2-5
2.3 TERMINAL CONTROL CHARACTERS............................................................................................ 2-5
2.4 DBUG COMMAND SET..................................................................................................................... 2-6
2.4.1. AS - Assemble AS...................................................................................................... 2-8
2.4.2. BC - Compare Blocks of Memory BC................................................. 2-10
2.4.3. BF - Block of Memory Fill BF............................................................................................. 2-11
2.4.4. BM - Block Move BM ........................................................................................................ 2-12
2.4.5. BR - Breakpoint BR ........................................................................................................... 2-13
2.4.6. BS - Block Search BS......................................................................................................... 2-14
2.4.7. DATA - Data Conversion DATA......................................................................................... 2-15
2.4.8. DI - Disassemble DI........................................................................................................... 2-16
2.4.9. DL - Download Serial DL .................................................................................................. 2-17
2.4.10. DN - Download Network DN............................................................................................... 2-18
2.4.11. Go - Execute GO............................................................................................................... 2-19
2.4.12. GT - Execute Till a Temporary Breakpoint GT...................................................................... 2-20
2.4.13. HELP - Help HE............................................................................................................... 2-21
2.4.14. IRD - Internal Registers Display IRD................................................................................... 2-22
2.4.15. IRM - Internal Registers MODIFY IRM............................................................................... 2-23
2.4.16. MD - Memory Display MD ................................................................................................ 2-24
2.4.17. MM - Memory Modify MM ............................................................................................... 2-25
2.4.18. RD - Register Display RD................................................................................................. 2-26
2.4.19. RM - Register Modify RM................................................................................................. 2-27
2.4.20. RESET - Reset the board and dBUG RESET........................................................................ 2-28

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2.4.21. SET - Set Configuration SET .............................................................................................. 2-29
2.4.22. SHOW - Show Configuration SHOW.................................................................................... 2-31
2.4.23. STEP - Step Over ST.......................................................................................................... 2-32
2.4.24. SYMBOL - Symbol Name Management SYMBOL.................................................................. 2-33
2.4.25. TRACE - Trace Into TR ..................................................................................................... 2-34
2.4.26. UPDBUG - Update the dBUG Image UPDBUG.................................................................... 2-35
2.4.27. UPUSER - Update User Code In Flash UPUSER.................................................................. 2-36
2.5 TRAP #15 FUNCTIONS ....................................................................................................................... 2-38
2.5.1. OUT_CHAR............................................................................................................................... 2-38
2.5.2. IN_CHAR................................................................................................................................... 2-38
2.5.3. CHAR_PRESENT ...................................................................................................................... 2-39
2.5.4. EXIT_TO_dBUG........................................................................................................................ 2-39
CHAPTER 3......................................................................................................................................................3-1
3.1 THE PROCESSOR AND SUPPORT LOGIC....................................................................................... 3-1
3.1.1. The Processor.............................................................................................................................. 3-1
3.1.2. The Reset Logic ........................................................................................................................... 3-1
3.1.3. The -HIZ Signal ........................................................................................................................... 3-2
3.1.4. The Clock Circuitry ..................................................................................................................... 3-2
3.1.5. Watchdog Timer (BUS MONITOR) .............................................................................................. 3-2
3.1.6. Interrupt Sources ......................................................................................................................... 3-2
3.1.7. Internal SRAM............................................................................................................................. 3-3
3.1.8. The MCF5307 Registers and Memory Map.................................................................................. 3-3
3.1.9. Reset Vector Mapping.................................................................................................................. 3-4
3.1.10. /TA Generation ............................................................................................................................ 3-4
3.1.11. Wait State Generator ................................................................................................................... 3-4
3.2 THE SDRAM DIMM .......................................................................................................................... 3-5
3.3 FLASH ROM ...................................................................................................................................... 3-5
3.3.1. JP1 Jumper and User’s Program ................................................................................................. 3-5
3.4 THE SERIAL COMMUNICATION CHANNELS............................................................................... 3-5
3.4.1. The MCF5307 DUART................................................................................................................. 3-6
3.4.2. Motorola Bus (M-Bus) Module..................................................................................................... 3-6
3.5 THE PARALLEL I/O PORT................................................................................................................. 3-6
3.6 ON BOARD ETHERNET LOGIC....................................................................................................... 3-7
3.7 THE CONNECTORS AND THE EXPANSION BUS.......................................................................... 3-9
3.7.1. The Terminal Connector J4.......................................................................................................... 3-9
3.7.2. The Auxiliary Serial Communication Connector J7...................................................................... 3-9
3.7.3. Logical Analyzer connectors LA1-5 and Processor Expansion Bus J8 & J9 ............................... 3-10
3.7.4. The Debug Connector J1............................................................................................................ 3-15
APPENDIX A (CONFIGURING DBUG FOR NETWORK DOWNLOADS)............................................. 1
A.1 REQUIRED NETWORK PARAMETERS .......................................................................................................... 1
A.2 CONFIGURING DBUG NETWORK PARAMETERS.......................................................................................... 1
A.3 TROUBLESHOOTING NETWORK PROBLEMS................................................................................................ 2
APPENDIX B (FPLA CODE) ....................................................................................................................... 5
APPENDIX C (SCHEMATICS).................................................................................................................... 9
APPENDIX D (PIN ARRAY LAYOUT)......................................................................................................18

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.............................................................TABLES
TABLE 1 – JP1, UPPER/LOWER HALF BOOT....................................................................................................... 1-10
TABLE 2 – JP2, /CS0 SELECT ............................................................................................................................. 1-10
TABLE 3 - DBUG COMMANDS.............................................................................................................................. 2-7
TABLE 4 - THE LAB5307REV2 MEMORY MAP ....................................................................................................... 3-4
TABLE 5 - THE J4 (TERMINAL) CONNECTOR PIN ASSIGNMENT................................................................................ 3-9
TABLE 6 - THE J7 CONNECTOR PIN ASSIGNMENT................................................................................................. 3-10
TABLE 7 - THE J8 CONNECTOR PIN ASSIGNMENT................................................................................................. 3-10
TABLE 8- THE J9 CONNECTOR PIN ASSIGNMENT ................................................................................................. 3-11
TABLE 9 - THE LA2 CONNECTOR PIN ASSIGNMENT ............................................................................................. 3-12
TABLE 10 - THE LA1 CONNECTOR PIN ASSIGNMENT............................................................................................ 3-13
TABLE 11 - THE LA3 CONNECTOR PIN ASSIGNMENT............................................................................................ 3-13
TABLE 12 - THE LA4 CONNECTOR PIN ASSIGNMENT............................................................................................ 3-14
TABLE 13 - THE LA5 CONNECTOR PIN ASSIGNMENT............................................................................................ 3-14
TABLE 14 - THE J1 CONNECTOR PIN ASSIGNMENT............................................................................................... 3-15

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............................................................ FIGURES
FIGURE 1 BLOCK DIAGRAM OF THE BOARD............................................................................................................ 1-2
FIGURE 2 PIN ASSIGNMENT FOR J4 (TERMINAL) CONNECTOR. ................................................................................ 1-6
FIGURE 3 SYSTEM CONFIGURATION...................................................................................................................... 1-7
FIGURE 4 JUMPER AND CONNECTOR PLACEMENT.................................................................................................... 1-8
FIGURE 5 FLOW DIAGRAM OF DBUG OPERATIONAL MODE.................................................................................... 2-3

1-1
CHAPTER 1
INTRODUCTION TO THE SBC5307 BOARD
1.1 INTRODUCTION
The SBC5307 is a versatile single board computer based on MCF5307 ColdFire® Processor. It may be
used as a powerful microprocessor based controller in a variety of applications. With the addition of a
terminal, it serves as a complete microcomputer for development/evaluation, training and educational use.
The user must only connect an RS-232 compatible terminal (or a personal computer with terminal
emulation software) and a power supply to have a fully functional system.
Provisions have been made to connect this board to additional user supplied boards, via the Microprocessor
Expansion Bus connectors, to expand memory and I/O capabilities. Additional boards may require bus
buffers to permit additional bus loading.
Furthermore, provisions have been made in the PC-board to permit configuration of the board in a way,
which best suits, an application. Options available are: up to 8M SDRAM, SRAM, Timer, I/O, Ethernet,
and 1M bytes of Flash. In addition, all of the signals are easily accessible to any logical analyzer with
mictor probes to assist in debugging. Most of the processor’s signals are also available via connectors J8
and J9 for expansion purposes.
1.2 GENERAL HARDWARE DESCRIPTION
The SBC5307 board provides the RAM, Flash ROM, on board NE2000 compatible Ethernet interface
(10M bit/sec), RS232, and all the built-in I/O functions of the MCF5307 for learning and evaluating the
attributes of the MCF5307. The MCF5307 is a member of the ColdFire® family of processors. It is a 32-
bit processor with 32 bits of addressing and 32 lines of data. The processor has eight 32-bit data registers,
eight 32-bit address registers, a 32-bit program counter, and a 16-bit status register.
The MCF5307 has a System Integration Module referred to as SIM. The module incorporates many of the
functions needed for system design. These include programmable chip-select logic, System Protection
logic, General purpose I/O, and Interrupt controller logic. The chip-select logic can select up to eight
memory banks or peripherals in addition to two banks of DRAM’s. The chip-select logic also allows
programmable number of wait-state to allow the use of slower memory (refer to MCF5307 User's Manual
by Motorola for detail information about the SIM.) The SBC5307 only uses three of the chip selects to
access the Flash ROM’s, SRAM (which is not populated on board, may be added by the user) and the
Ethernet. The DRAM controller is used to control one SIMM or one DIMM module 8M bytes of DRAM,
both -RAS lines and all four –CAS lines are used. All other functions of the SIM are available to the user.
A hardware watchdog timer (Bus Monitor) circuit is included in the SIM that monitors the bus activities.
If a bus cycle is not terminated within a programmable time, the watchdog timer will assert an internal
transfer error signal to terminate the bus cycle. A block diagram of the board is shown in Figure 1.

1-2
Addr
Buffer
U10,,U11
ispLSI
2032LV
U9
XCEIVERS
Flash 1Mbit
DRAM
DIMM
Data
Buffers
U16
MCF5307
RJ45
Ethernet U12
J3
U20,U21
U23
I/O PORTS ADDR BUS
DATA BUS
CONTROL BUS
Mictor and Expansion Connectors
Figure 1Block Diagram of the board

1-3
1.3 SYSTEM MEMORY
There are two on board Flash ROM’s (U20, U21), U20 is the most significant byte and the U21 is the least
significant byte. The SBC5307 comes with two 29LV004 Flash ROM’s programmed with a
debugger/monitor firmware. Both AM29LV004DT Flash are 4Mbits each giving a total of 1Mbyte of
Flash memory. The dBUG only supports 29LV004 flash ROM.
There is one 168-pin DIMM socket for SDRAM. It currently supports 1M x 4 Bank x 16-Bits SDRAM
totaling 8M of RAM.
The MCF5307 has 4K bytes organized as 1024x32 bits of internal SRAM.
The internal cache of the MCF5307 is a non-blocking, 8kbyte, 4-way set-associative, unified (instruction
and data cache with a 16-byte line size. The ROM Monitor currently does not utilize the cache, but
programs downloaded with the ROM Monitor can use the cache.
1.4 SERIAL COMMUNICATION CHANNELS
The MCF5307 has 2 built-in UART’s with independent baud rate generators. The signals of channel one
are passed through external Driver/Receivers to make the channel compatible with RS-232. UART1 is
used by the debugger for the user to access with a terminal. In addition, the signals of both channels are
available on the mictor connectors LA1 and LA3 to be viewed by a logic analyzer. UART1 channel is the
“TERMINAL” channel used by the debugger for communication with external terminal/PC. The
“TERMINAL’ baud rate is set at 19200. The MCF5307 also incorporate the M-Bus, which is compatible
with I2C Bus standard. The I2C bus is connected to the DIMM socket with an ID# = 0, however, the
debugger does not use this feature.
1.5 PARALLEL I/O PORTS
MCF5307 offers one 16-bit general-purpose parallel I/O port. Each pin can be individually programmed
as input or output. The parallel port bits PP (7:0) is multiplexed with TT (1:0), TM (2:0), DREQ (1:0),
and XTIP. The second set of parallel port bits PP (15:8) is multiplexed with address bus bits A (31:24).
Both bytes of the parallel port are controlled by the Pin Assignment Register (PAR). The pins are
programmable on a pin by pin basis. The setting of the multiplex pins are determined by the configuration
byte during reset. After reset, all pins are configured as general-purpose parallel I/O.
1.6 PROGRAMMABLE TIMER/COUNTER
The MCF5307 has two built in general purpose timer/counters. These timers are available to the user.
The signals for the timer are available on the LA4 to be viewed by a logic analyzer.