ART Technology Development PCI8303 User manual

PCI8303
User’s Manual
BeijingART Technology Development Co., Ltd.

PCI8303DataAcquisition V6.011
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Contents
Contents................................................................................................................................................................................2
Chapter 1 Overview..............................................................................................................................................................3
Chapter 2 Components Layout Diagram and a Brief Description .......................................................................................6
2.1 The Main Component Layout Diagram ..................................................................................................................6
2.2 The Function Description for the Main Component ...............................................................................................6
2.2.1 Signal Input and Output Connectors ............................................................................................................6
2.2.2 Potentiometer ...............................................................................................................................................6
2.2.3 Status Indicator.............................................................................................................................................7
2.2.4 Physical ID of DIP Switch ...........................................................................................................................7
Chapter 3 Signal Connectors................................................................................................................................................9
3.1 The Definition of Signal Input and Output Connectors ..........................................................................................9
Chapter 4 Connection Ways for Each Signal......................................................................................................................11
4.1 Analog signal single-ended input connection........................................................................................................11
4.2 Analog differential inputs......................................................................................................................................11
43 Analog output connection ......................................................................................................................................12
4.4 Digital input connection........................................................................................................................................12
4.5 Digital output connection......................................................................................................................................12
4.5 Clock input/output and trigger signal connection .................................................................................................13
4.6 Methods of Realizing the Multi-card Synchronization .........................................................................................13
Chapter 5 The Instruction of the A/D Trigger Function......................................................................................................15
5.1 A/D Internal Trigger Mode....................................................................................................................................15
5.2 A/D External Trigger Mode ..................................................................................................................................15
Chapter 6 Methods of using A/D Internal and External Clock Function............................................................................18
6.1 Internal Clock Function of A/D.............................................................................................................................18
6.2 External Clock Function of A/D ...........................................................................................................................18
6.3 Methods of Using A/D Continuum and Grouping Sampling Function.................................................................18
6.3.1 A/D Continuum Sampling Function...........................................................................................................18
6.3.2 A/D Grouping Sampling Function .............................................................................................................19
Chapter7 Notes, Calibration and Warranty Policy.............................................................................................................23
71 Notes ......................................................................................................................................................................23
7.2 Analog Signal Input Calibration............................................................................................................................23
7.3 Analog Signal Output Calibration.........................................................................................................................23
7.4 DA use...................................................................................................................................................................24
7.5 Warranty Policy.....................................................................................................................................................24
Products Rapid Installation and Self-check ........................................................................................................................25
Rapid Installation ........................................................................................................................................................25
Self-check ...................................................................................................................................................................25
Delete Wrong Installation ...........................................................................................................................................25

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Chapter 1 Overview
In the fields of Real-time Signal Processing, Digital Image Processing and others, high-speed and high-precision data
acquisition modules are demanded. ART PCI8303 data acquisition module, which brings in advantages of similar
products that produced in china and other countries, is convenient for use, high cost and stable performance.
ART PCI8303 is a data acquisition module based on PCI bus. It can be directly inserted into IBM-PC/AT or a computer
which is compatible with PCI8303 to constitute the laboratory, product quality testing center and systems for different
areas of data acquisition, waveform analysis and processing. It may also constitute the monitoring system for industrial
production process.
Software
Analysis Software
ART PCI8303 module is well-suited for precision data acquisition analysis applications, which you can specifically
address with the ART Data Acquisition Measurement Suite. The suite has two components –digital and graphics mode
analysis (functions) for voltage (any signal can be transformed into the voltage signal), frequency response and other
analysis.
Unpacking Checklist
Check the shipping carton for any damage. If the shipping carton and contents are damaged, notify the local dealer or
sales for a replacement. Retain the shipping carton and packing material for inspection by the dealer.
Check for the following items in the package. If there are any missing items, contact your local dealer or sales.
¾PCI8303 Data Acquisition Board
¾ART Disk
1) user’s manual (pdf)
2) drive
3) catalog
¾Warranty Card

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FEATURES
Analog Input
¾Converter Type: AD7321
¾Input Range: ±10V, ±5V (default), ±2.5, 0~10V
¾13-bit resolution, the 13-th bit is sign bit
¾Sampling Rate: 31S/s ~ 180KS/s
Note: each channel actual sampling rate = sampling rate/the number of sampling channels
¾Input Channels: 16SE/8DI
¾Data Read Mode: non-empty and half-full mode, interrupt mode
¾FIFO Size: 16K word
¾Memory Sign: non-empty, half-full, full (overflow)
¾Sample mode: continuous sample and group sample
¾Group Interval: software-configurable, minimum value is sampling period, maximum value is 419430us
¾Loops of Group: software-configurable, minimum value is one time , maximum value is 65535 times
¾Clock Source: internal clock and external clock
¾Trigger Mode: software trigger and hardware trigger (external trigger)
¾Trigger Type: edge trigger and level trigger
¾Trigger Dir: negative, positive, either positive or negative trigger
¾Trigger Source: DTR
¾DTR range: TTL
¾A/D Conversion Time: ≤1.6us
¾Isolation Voltage: 2500 Vrms(1min.)
¾Programmable amplifier: AD8251(default), AD8250, AD8253
¾Programmable Gain: 1, 2, 4, 8 (AD8251 default ) or 1, 2, 5, 10 (AD8250) or 1, 10, 100, 1000 (AD8253)
¾Analog Input Impedance: 10MΩ
¾Non-linear error: ±1LSB(Maximum)
¾System Measurement Accuracy: 0.1%
¾Operating Temperature Range: 0℃~50℃
¾Storage Temperature Range: -20℃~70℃
Analog Output
¾Converter Type: AD5724
¾Output Range: 0~5V, 0~10V, 0~10.8V, ±5V, ±10V, ±10.8V
¾12-bit resolution
¾Set-up Time: 10μs (0.01%)
¾Output Channels: 4
¾Isolation Voltage: 2500 Vrms(1min.
¾Non-linear error: ±1LSB (Max)
¾Output error (full-scale): ±1LSB
¾Operating Temperature Range: 0℃~50℃
¾Storage Temperature Range: -20℃~70℃
Digital Input
¾Channel No.: 8-channel
¾Electric Standard: TTL compatible
¾High Voltage: ≧2V
¾Low Voltage: ≦0.8V

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Digital Output
¾Channel No.: 8-channel
¾Electrical Standard: CMOS compatible
¾High Voltage: ≧4.45V
¾Low Voltage: ≦0.5V
¾Power-on Reset
Other Features
Board Clock Oscillation: 40MHz
Dimension: 144mm (L)*98mm (W)*16mm (H)

PCI8303DataAcquisition V6.011
Chapter 2 Components Layout Diagram and a Brief Description
2.1 The Main Component Layout Diagram
2.2 The Function Description for the Main Component
2.2.1 Signal Input and Output Connectors
CN1: Signal input and output connectors
2.2.2 Potentiometer
RP1: AD analog signal input zero-point adjustment potentiometer
RP2: AD analog signal input full-scale adjustment potentiometer
RP4: AO0 zero-point adjustment potentiometer
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RP7: AO1 zero-point adjustment potentiometer
RP3: AO2 zero-point adjustment potentiometer
RP8: AO3 zero-point adjustment potentiometer
RP6: AO0 full-scale adjustment potentiometer
RP9: AO1 full-scale adjustment potentiometer
RP5: AO2 full-scale adjustment potentiometer
RP10: AO3 full-scale adjustment potentiometer
2.2.3 Status Indicator
EF: FIFO non-empty status indicator
HF: FIFO half-full status indicator
FF: FIFO overflow status indicator
2.2.4 Physical ID of DIP Switch
DID1: Set physical ID number. When the PC is installed more than one PCI8303 , you can use the DIP switch to set a
physical ID number for each board, which makes it very convenient for users to distinguish and visit each board in the
progress of the hardware configuration and software programming. The following 4-bit numbers are expressed by the
binary system: When DIP switch points to "ON", that means "1", and when it points to the other side, that means "0." As
they are shown in the following diagrams: "ID3" is the high bit. "ID0" is the low bit, and the black part in the diagram
represents the location of the switch. (Test softwares of the company often use the logic ID management equipments and
at this moment the physical ID DIP switch is invalid. If you want to use more than one kind of the equipments in one and
the same system at the same time, please use the physical ID as much as possible.).
ON
1
ID0ID1ID2ID3
234
ON
DID1
The above chart shows"1111", so it means that the physical ID is 15.
ON
1
ID0ID1ID2ID3
234
ON
DID1
The above chart shows"0111", so it means that the physical ID is 7.
ON
1
ID0ID1ID2ID3
234
ON
DID1
The above chart shows"0101", so it means that the physical ID is 5.
ID3 ID2 ID1 ID0 Physical ID（Hex）Physical ID（Dec）
OFF（0）OFF（0）OFF（0）OFF（0）0 0
OFF（0）OFF（0）OFF（0）ON（1）1 1
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OFF（0）OFF（0）ON（1）OFF（0）2 2
OFF（0）OFF（0）ON（1）ON（1）3 3
OFF（0）ON（1）OFF（0）OFF（0）4 4
OFF（0）ON（1）OFF（0）ON（1）5 5
OFF（0）ON（1）ON（1）OFF（0）6 6
OFF（0）ON（1）ON（1）ON（1）7 7
ON（1）OFF（0）OFF（0）OFF（0）8 8
ON（1）OFF（0）OFF（0）ON（1）9 9
ON（1）OFF（0）ON（1）OFF（0）A 10
ON（1）OFF（0）ON（1）ON（1）B 11
ON（1）ON（1）OFF（0）OFF（0）C 12
ON（1）ON（1）OFF（0）ON（1）D 13
ON（1）ON（1）ON（1）OFF（0）E 14
ON（1）ON（1）ON（1）ON（1）F 15

PCI8303DataAcquisition V6.011
Chapter 3 Signal Connectors
3.1 The Definition of Signal Input and Output Connectors
62 core plug on the CN1 pin definition
42
1
22
24
23
2
3
25
4
26
5
27
6
28
7
29
8
30
9
31
10
32
11
33
12
34
13
35
14
36
15
37
16
38
17
39
18
40
19
41
20
21
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
DO5
DO7
DO6
DO4
DO3
DO2
DO1
DTR
DO0
DI7
DGND
DI6
DI5
DI4
DI3
DI2
DI1
DI0
AO3
AO2
AO0
AGND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AI15
AI13
AI12
AI10
AI9
AI7
AI6
AI4
AI3
AI1
AI0
AI2
AI5
AI8
AI11
AI14
NC
NC
NC
NC
NC
AGND
AO1
NC
AGND
+5V
DGND
CLKOUT
CLKIN
Pin definition about CN1:
Pin name Pin feature Pin function definition
AI0~AI15 Input Analog input, reference ground is AGND.
AO0~AO3 Output Analog output, reference ground is AGND.
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AGND GND Analog ground. This AGND pin should be connected to the
system’s AGND plane.
DGND GND Digital ground.
This DGND pin should be connected to the
system’s DGND plane.
DI0~DI7 Input Digital inputs
DO0~DO7 Output Digital outputs
CLKIN Input External clock input.
CLKOUT Output Internal clock output.
DTR Input Digital trigger input.
+5V Output 5V power supply output.
NC -- Not connected.

PCI8303DataAcquisition V6.011
Chapter 4 Connection Ways for Each Signal
4.1 Analog signal single-ended input connection
Single-ended mode can achieve a signal input by one channel, and several signals use the common reference ground.
This mode is widely applied in occasions of the small interference and relatively many channels.
Figure 4.1 single-ended input connection
4.2 Analog differential inputs
Double-ended input mode, which was also called differential input mode, uses positive and negative channels to input a
signal. This mode is mostly used when biggish interference happens and the channel numbers are few. SE/DI mode can
be set by the software, please refer to PCI8303 software manual.
According to the diagram below, PCI8303 board can be connected as analog voltage double-ended input mode, which
can effectively suppress common-mode interference signal to improve the accuracy of acquisition. Positive side of the
16-channel analog input signal is connected to AI0~AI15, the negative side of the analog input signal is connected to
AI16~AI31, equipments in industrial sites share the AGND with PCI8303 board.
Figure 4.2 double-ended input connection
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43 Analog output connection
Figure 4.3 analog signal output connection
4.4 Digital input connection
Figure 4.4 digital signal input connection
4.5 Digital output connection
switch signal
DO0
DO7
DO1
DO2
DGND
switch device
switch device
Figure 4.5 digital signal output connection
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4.5 Clock input/output and trigger signal connection
Figure 4.6 Clock Input/Output and Trigger Signal Connection
4.6 Methods of Realizing the Multi-card Synchronization
Three methods can realize the synchronization for the PC8303, the first method is using the cascade master-slave card,
the second one is using the common external trigger, and the last one is using the common external clock.
When using master-slave cascade card programs, the master card generally uses the internal clock source model, while
the slave card uses the external clock source mode. After the master card and the slave card are initialized according to
the corresponding clock source mode. At first, start all the slave cards, as the main card has not been activated and there
is no output clock signal, so the slave card enters the wait state until the main card was activated. At this moment, the
multi-card synchronization has been realized. When you need to sample more than channels of a card, you could
consider using the multi-card cascaded model to expand the number of channels.
Slave Card 2
CLKOUT
CLKIN
CLKIN Slave Card 1
Master Card
When using the common external trigger, please make sure all parameters of different PCI8303 are the same. At first,
configure hardware parameters, and use digital signal triggering (DTR), then connect the sampled signal, input
triggering signal from DTR pin, then click “Start” button, at this time, PCI8303 does not sample any signal but waits
for external trigger signal. When each module is waiting for external trigger signal, use the common external trigger
signal to startup modules, at last, we can realize synchronization data acquisition in this way. See the following figure:
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PCI8303DataAcquisition V6.011
PCI 8303
External Trigger Signal
DTR
DTR
DTR PCI 8303
PCI 8303
Note: when using the DTR, select the internal clock mode
When using the common external clock trigger, please make sure all parameters of different PCI8303 are the same. At
first, configure hardware parameters, and use external clock, then connect the sampled signal, then click “Start” button,
at this time, PCI8303 does not sample any signal, but wait for external clock signal. When each module is waiting for
external clock signal, use the common external clock signal to startup modules, at last, we realize synchronization data
acquisition in this way. See the following figure:
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PCI8303DataAcquisition V6.011
Chapter 5 The Instruction of the A/D Trigger Function
5.1 A/D Internal Trigger Mode
When A/D is in the initialization, if the A/D hardware parameter ADPara.TriggerMode = PCI8303_TRIGMODE_SOFT,
we can achieve the internal trigger acquisition. In this function, when calling the StartDeviceProAD function, it will
generate A/D start pulse, A/D immediately access to the conversion process and not wait for the conditions of any other
external hardware. It also can be interpreted as the software trigger.
As for the specific process, please see the figure below, the cycle of the A/D work pulse is decided by the sampling
frequency.
F
igure 5.1 Internal Trigger Mode
The first working
pulse after the A/D
start pulse
Start Enable
Convert Pulse
5.2 A/D External Trigger Mode
When A/D is in the initialization, if the A/D hardware parameter ADPara.TriggerMode = PCI8303_TRIGMODE_POST,
we can achieve the external trigger acquisition. In this function, when calling the StartDeviceProAD function, A/D will
not immediately access to the conversion process but wait for the external trigger source signals accord with the
condition, then start converting the data. It also can be interpreted as the hardware trigger. Trigger source is DTR
(Digital Trigger Source).
(1) Edge trigger function
Edge trigger is to capture the characteristics of the changes between the trigger source signal and the trigger level signal
to trigger A/D conversion.
When ADPara.TriggerDir = PCI8303_TRIGDIR_NEGATIVE, choose the trigger mode as the falling edge trigger. That
is, when the DTR trigger signal is on the falling edge, A/D will immediately access to the conversion process, and its
follow-up changes have no effect on A/D acquisition.
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Digital Trigger Signal
The waiting time
The falling edge before
the A/D started is
invalid
The first falling edge after the
A/D started is valid
Figure 5.2.1 Falling edge Trigger
The first working
pulse after triggered
A/D Start Pulse
A/D Working Pulse
When ADPara.TriggerDir = PCI8303_TRIGDIR_POSITIVE, choose the trigger mode as rising edge trigger. That is,
when the DTR trigger signal is on the rising edge, A/D will immediately access to the conversion process, and its
follow-up changes have no effect on A/D acquisition.
When ADPara.TriggerDir = PCI8303_TRIGDIR_POSIT_NEGAT, choose the trigger mode as rising or falling edge
trigger. That is, when the DTR trigger signal is on the rising or falling edge, A/D will immediately access to the
conversion process, and its follow-up changes have no effect on A/D acquisition. This function can be used in the case
that the acquisition will occur if the exoteric signal changes.
（2）Level trigger function
Level trigger is to capture the condition that trigger signal is higher or lower than the trigger level to trigger A/D
conversion.
When ADPara.TriggerDir = PCI8303_TRIGDIR_NEGATIVE, it means the trigger level is low. When DTR trigger
signal is in low level, A/D is in the conversion process, once the trigger signal is in the high level, A/D conversion will
automatically stop, when the trigger signal is in the low level again, A/D will re-access to the conversion process, that
is, only converting the data when the trigger signal is in the low level.
A/D Working Pulse
A/D Start Pulse
The waiting time
The high level before
the A/D started is
Figure 5.2.4 High Level Trigger
The first
p
ulse after the
A/D triggered
Digital Trigger Signal
Pause
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When ADPara.TriggerDir = PCI8303_TRIGDIR_POSITIVE, it means the trigger level is high. When DTR trigger
signal is in high level, A/D is in the conversion process, once the trigger signal is in the low level, A/D conversion will
automatically stop, when the trigger signal is in the high level again, A/D will re-access to the conversion process, that
is, only converting the data when the trigger signal is in the high level.
When ADPara.TriggerDir = PCI8303_TRIGDIR_POSIT_NEGAT, it means the trigger level is low or high. The effect
is the same as the internal software trigger.
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Chapter 6 Methods of using A/D Internal and External Clock
Function
6.1 Internal Clock Function of A/D
Internal Clock Function refers to the use of on-board clock oscillator and the clock signals which are produced by the
user-specified frequency to trigger the A/D conversion regularly. To use the clock function, the hardware parameters
ADPara.ClockSource = PCI8303 _CLOCKSRC_IN should be installed in the software. The frequency of the clock in
the software depends on the hardware parameters ADPara.Frequency. For example, if Frequency = 100000, that means
A/D work frequency is 100000Hz (that is, 100 KHz, 10μs / point).
6.2 External Clock Function of A/D
External Clock Function refers to the use of the outside clock signals to trigger the A/D conversion regularly. The clock
signals are provide by the CLKIN pin of the CN1 connector. The outside clock can be provided by PCI8303 clock
output (CLKOUT of CN1), as well as other equipments, for example clock frequency generators. To use the external
clock function, the hardware parameters ADPara.ClockSource = PCI8303_CLOCKSRC_OUT should be installed in
the software. The clock frequency depends on the frequency of the external clock, and the clock frequency on-board
(that is, the frequency depends on the hardware parameters ADPara.Frequency) only functions in the packet acquisition
mode and its sampling frequency of the A/D is fully controlled by the external clock frequency.
6.3 Methods of Using A/D Continuum and Grouping Sampling Function
6.3.1 A/D Continuum Sampling Function
The continuous acquisition function means the sampling periods for every two data points are completely equal in the
sampling process of A/D, that is, completely uniform speed acquisition, without any pause, so we call that continuous
acquisition.
To use the continuous acquisition function, the hardware parameters ADPara.ADMode = PCI8303
_ADMODE_SEQUENCE should be installed in the software. For example, in the internal clock mode, hardware
parameters ADPara.Frequency = 100000 (100KHz) should be installed, and 10 microseconds after the A/D converts the
first data point, the second data point conversion starts, and then 10 microseconds later the third data point begins to
convert, and so on.
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6.3.2 A/D Grouping Sampling Function
Grouping acquisition (pseudo-synchronous acquisition) function refers to the sampling clock frequency conversion
among the channels of the group in the AD sampling process, and also a certain waiting time exists between every two
groups, this period of time is known as the Group Interval. Loops of group refer to numbers of the cycle acquisition for
each channel in the same group. In the internal clock mode and the fixed-frequency external clock mode, the time
between the groups is known as group cycle. The conversion process of this acquisition mode as follows: a short time
stop after the channels conversion in the group (that is, Group Interval), and then converting the next group, followed
by repeated operations in order, so we call it grouping acquisition.
The purpose of the application of the grouping acquisition is that: at a relatively slow frequency, to ensure that all of the
time difference between channels to become smaller in order to make the phase difference become smaller, thus to
ensure the synchronization of the channels, so we also say it is the pseudo-synchronous acquisition function. In a group,
the higher the sampling frequency is, the longer Group Interval is, and the better the relative synchronization signal is.
The sampling frequency in a group depends on ADPara. Frequency, Loops of group depends on
ADPara.LoopsOfGroup, the Group Interval depend on ADPara. Group Interval.
Based on the grouping function, it can be divided into the internal clock mode and the external clock mode. Under the
internal clock mode, the group cycle is decided by the internal clock sampling period, the total number of sampling
channels, Loops of group and Group Interval together. In each cycle of a group, AD only collects a set of data. Under
the external clock mode, external clock cycle ≥internal clock sampling cycle ×the total number of sampling
channels ×Loops of group + AD chip conversion time, AD data acquisition is controlled and triggered by external
clock. The external clock mode is divided into fixed frequency external clock mode and unfixed frequency external
clock mode. Under the fixed frequency external clock mode, the group cycle is the sampling period of the external
clock.
The formula for calculating the external signal frequency is as follows:
Under the internal clock mode:
Group Cycle = the internal clock sampling period ×the total number of sample channels ×Loops of group + AD chips
conversion time + Group Interval
External signal cycle = (cycle signal points / Loops of group) ×Group Cycle
External signal frequency = 1 / external signal cycle
Under the external clock mode: (a fixed-frequency external clock)
Group Cycle = external clock cycle
External signal cycle = (cycle signal points / Loops of group) ×Group Cycle
External signal frequency = 1 / external signal cycle
Formula Notes:
The internal sampling clock cycle = 1 / (AD Para. Frequency)
The total number of sampling channels = AD Para. Last Channel – AD Para. First Channel + 1
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PCI8303DataAcquisition V6.011
Loops of group == ADPara.LoopsOfGroup
AD Chips conversion time = see "AD Analog Input Function" parameter
Group Interval = AD Para. Group Interval
Signal Cycle Points = with the display of the waveform signal in test procedures, we can use the mouse to measure the
signal cycle points.
Under the internal clock mode, for example, sample two-channel 0, 1, and then 0 and 1 become a group. Sampling
frequency (Frequency) = 100000Hz (cycle is 10μs), Loops of group is 1, Group Interval = 50μs, then the acquisition
process is to collect a set of data first, including a data of channel 0 and a data of channel 1. We need 10μs to sample
the two data, 20μs to convert the data from the two channels. After the conversion time of an AD chip, AD will
automatically cut-off to enter into the waiting state until the 50μs group interval ends. We start the next group, begin to
convert the data of channel 0 and 1, and then enter into the waiting state again, and the conversion is going on in this
way, as the diagram following shows:
Start Enabled
Convert Pulse
Figure 6.1 Grouping Sampling which grouping cycle No is 1 under the Internal Clock Mode
d
a c
ba
Note: a―internal clock sample cycle
b―AD chips conversion time
c―Group Interval
d―group cycle
Change the loops of group into 2, then the acquisition process is to collect the first set of data, including two data of
channel 0 and two data of channel 1, the conversion order is 0,1,0,1. We need 10μs to sample each of the four data.
After the conversion time of an AD chip, AD will automatically stop to enter into the waiting state until the 50μs Group
Interval ends. We start the next group, begin to convert the data of channel 0 and 1, and then enter into the waiting state
again, and the conversion is going on in this way, as the diagram following shows:
Start Enabled
Convert Pulse
Figure 6.2 Grouping Sampling which grouping cycle No is 2 under the Internal Clock Mode
d
a c
ba
Notes: a―internal clock sample cycle
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