Asahi KASEI AK4458 Operating and maintenance instructions

[AK4458]
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1. General Description
The AK4458 is a 32-bit 8ch Premium DAC, which achieves industry’s best low distortion characteristics by a
newly developed low distortion technology. It corresponds to a 768kHz PCM input and an 11.2MHz DSD
input at maximum, suitable for play backing high resolution audio sources that are becoming widespread in
network audios, USB-DACs and Car Audio Systems. In addition, “OSR-Doubler”technology is newly
adopted, making the AK4458 capable of supporting wide range signals and achieving low out-of-band noise
while realizing low power consumption. Moreover, the AK4458 has five types of 32-bit digital filters,
realizing simple and flexible sound making in wide range of applications.
Application: AV Receivers, CD/SACD Players, Network Audios, USB DACs, USB Headphones, Sound
Plate/Bars, Car Audios, Automotive External Amplifiers, Measuring Instruments and Control
Systems.
2. Features
(1) DR, S/N: 115dB
(2) THD+N: -107dB
(3) 256x Over sampling (OSR - Doubler)
(4) Sampling Rate: 8kHz 768kHz
(5) 32Bit 8x Digital Filter
- Ripple: 0.0032dB, Attenuation: 80dB (Sharp Roll-Off Filter Setting)
- Five Types of High Quality Sound Filter Option
- Sharp Roll-Off Filter
- Slow Roll-Off Filter
- Short Delay Sharp Roll-Off Filter (GD=5.8/fs)
- Short Delay Slow Roll-Off Filter (GD=4.8/fs)
- Super Slow Roll-Off Filter
(6) High Tolerance to Clock Jitter
(7) Low Distortion Differential Output
(8) DSD data input
(9) Daisy Chain
(10) Digital De-emphasis for 32, 44.1, 48kHz sampling
(11) Soft Mute
(12) Digital Attenuator (255 levels and 0.5dB step)
(13) I/F Format:
- 24/32bit MSB justified
- 16/20/24/32bit
- LSB justified
- I2S
- DSD
- TDM
(14) 3-wire Serial and I2C μP I/F
(15) Master Clock:
- 30kHz ~ 32kHz: 1152fs
- 30kHz ~ 54kHz: 512fs or 768fs
- 30kHz ~ 108kHz: 256fs or 384fs
- 108kHz ~ 216kHz: 128fs or 192fs
~ 384kHz: 64fs or 128fs
~ 768kHz: 64fs
AK4458
115dB 768kHz 32-bit 8ch Premium DAC

[AK4458]
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(16) Digital Input Level: CMOS
(17) Power Supply:
- TVDD= 1.7 3.6V
- AVDD=3.0 5.5V
(18) Supporting 105°C Temperature (Exposed pad is connected to ground)
(19) Package: 48-pin QFN

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3.Table of Contents
1. General Description...............................................................................................................................- 1 -
2. Features..................................................................................................................................................- 1 -
3. Table of Contents...................................................................................................................................- 3 -
4. Block Diagram and Functions ...............................................................................................................- 5 -
■Functions ..............................................................................................................................................- 6 -
5. Pin Configurations and Functions..........................................................................................................- 7 -
■Ordering Guide.....................................................................................................................................- 7 -
■Pin Configurations................................................................................................................................- 7 -
■Pin Functions........................................................................................................................................- 8 -
■Handling of Unused Pin .......................................................................................................................- 9 -
6. Absolute Maximum Ratings ................................................................................................................- 10 -
7. Recommended Operation Conditions..................................................................................................- 10 -
8. Electrical Characteristics .....................................................................................................................- 11 -
■Analog Characteristics........................................................................................................................- 11 -
■Sharp Roll-Off Filter Characteristics..................................................................................................- 13 -
■Slow Roll-Off Filter Characteristics...................................................................................................- 14 -
■Short Delay Sharp Roll-Off Filter Characteristics..............................................................................- 15 -
■Short Delay Slow Roll-Off Filter Characteristics...............................................................................- 16 -
■DSD Mode Characteristics.................................................................................................................- 17 -
■DC Characteristics..............................................................................................................................- 17 -
■Switching Characteristics...................................................................................................................- 18 -
■Timing Diagram .................................................................................................................................- 22 -
9. Functional Descriptions.......................................................................................................................- 26 -
■D/A Conversion Mode (PCM mode, DSD mode)..............................................................................- 26 -
■System Clock......................................................................................................................................- 26 -
■Audio Interface Format ......................................................................................................................- 30 -
■D/A Conversion Mode (PCM Mode, DSD Mode) Switching Timing...............................................- 43 -
■Digital Filter (PCM mode) .................................................................................................................- 44 -
■De-emphasis Filter (PCM mode)........................................................................................................- 44 -
■Output Volume (PCM mode, DSD mode) .........................................................................................- 45 -
■Out of Band Noise Reduction Filter (PCM mode, DSD mode).........................................................- 46 -
■Zero Detection (PCM mode, DSD mode) ..........................................................................................- 52 -
■LR Channel Output Signal Select (PCM mode, DSD mode).............................................................- 52 -
■Sound Quality Adjustment (PCM Mode, DSD Mode).......................................................................- 54 -
■DSD Full Scale (FS) Signal Detection Function................................................................................- 55 -
■Soft Mute Operation (PCM mode, DSD mode) .................................................................................- 56 -
■Error Detection...................................................................................................................................- 57 -
■System Reset ......................................................................................................................................- 57 -
■Power Down Function........................................................................................................................- 58 -
■Power Off and Reset Functions..........................................................................................................- 59 -
■Synchronization Function (PCM Mode) ............................................................................................- 62 -
■Parallel Mode......................................................................................................................................- 63 -
■Serial Control Interface ......................................................................................................................- 63 -
■Function List.......................................................................................................................................- 68 -
■Register Map ......................................................................................................................................- 69 -
■Register Definitions............................................................................................................................- 70 -
10. Recommended External Circuits......................................................................................................- 78 -
■Typical Connection Diagram..............................................................................................................- 78 -

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11. Package ............................................................................................................................................- 82 -
■Outline Dimensions............................................................................................................................- 82 -
■Material & Lead finish .......................................................................................................................- 82 -
■Marking ..............................................................................................................................................- 83 -
12. Revision History ..............................................................................................................................- 83 -
IMPORTANT NOTICE............................................................................................................................- 84 -

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4.Block Diagram and Functions
MCLK
SDTI1/DSDR1
LRCK/DSDL1
CAD0_I2C/CSN/DIF
BICK/DCLK
SCL/CCLK/TDM1
SDA/CDTI/TDM0
PDN
AVDD
Clock
Divider
DVSS
TVDD
PS/CAD0_SPI
AOUTR1N
VREFH1
VREFL1
AVSS
AOUTL1P
AOUTR1P
PCM
Data
Interface
De-empha
sis
DSD
Data
Interface
8X
Interpolator
Control
Register
SCF
SCF
AOUTR2N
VREFH2
VREFL2
AOUTL2P
AOUTL2N
AOUTR2P
Vref
SDTI2/DSDL2
8X
Interpolator
SCF
SCF
Vref
Bias
I2C
AOUTR3N
VREFH3
VREFL3
AOUTL3P
AOUTL3N
AOUTR3P
8X
Interpolator
SCF
SCF
AOUTR4N
VREFH4
VREFL4
AOUTL4P
AOUTL4N
AOUTR4P
Vref
8X
Interpolator
SCF
SCF
Vref
SDTI3/DSDR2/TDMO1
SDTI4/DSDL3/TDMO2
DSDR3
DSDL4
DSDR4
VDD18
LDO
DZF/SMUTE
CAD1/DCHAIN
LDOE
DATT
Soft Mute
DSD Filter
DATT
Soft Mute
DATT
Soft Mute
DSD Filter
DATT
Soft Mute
DATT
Soft Mute
DSD Filter
DATT
Soft Mute
DATT
Soft Mute
DSD Filter
DATT
Soft Mute

Modulator
Noise
Rejection
Filter

Modulator
Noise
Rejection
Filter

Modulator
Noise
Rejection
Filter

Modulator
Noise
Rejection
Filter
AOUTL1N
Figure 1. Block Diagram

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■Functions
Block
Functions
PCM Data Interface
This block executes serial/parallel conversion of SDTI input 32bit data by
synchronizing with LRCK and BICK.
DSD Data Interface
1-bit data that is input from DSDL1-4 and DSDR1-4 pins is received by
synchronizing with DCLK.
DATT、Soft Mute
Apply DATT and Soft Mute process to input data.
De-emphasis
Apply De-emphasis process to input data.
8x Interpolator
FIR filters that over sample 1fs rate data to 8fs rate.
ΔΣ Modulator
Output multi-bit data to SCF. This block consists of a third-order digital delta-sigma
modulator.
Noise Rejection Filter
Attenuate out of band noise to prevent degradation of analog characteristics.
SCF
A primary switched capacitor filter that converts a multi-bit output of delta-sigma
modulator to an analog signal.
LDO
Generate power for internal digital circuit (1.8V typ.).
Control Register
Keep register settings for each mode.
Clock Divider
Divide Master Clock
In PCM mode, master clock is divided automatically by fs rate auto detection
function. In DSD mode, the master clock frequency is set by DCKS bit.

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5.Pin Configurations and Functions
■Ordering Guide
AK4458VN 40 +105C (Exposed pad is connected to ground)
40 +85C (Exposed pad is open)
48-pin QFN (0.5mm pitch)
AKD4458 Evaluation Board for AK4458
■Pin Configurations
37
AOUTR4P
38
39
40
AOUTL4N
41
VREFH4
42
43
VREFL4
44
AOUTR4N
LDOE
36
35
34
33
32
31
30
29
1
2
MCLK
3
LRCK/DSDL1
4
SDTI1/DSDR1
5
SDTI2/DSDL2
6
SDTI3/DSDR2/TDMO1
7
SDTI4/DSDL3/TDMO2
8
DSDR3
20
19
18
17
16
15
14
13
SCL/CCLK/TDM1
CAD0_I2C/CSN/ DIF
I2C
PS/CAD0_SPI
AOUTL1N
AOUTL1P
AOUTR3N
VREFL3
VREFH3
AOUTL3N
AVSS
AOUTR2P
SDA/CDTI/TDM0
BICK/DCLK
Top View
AOUTR3P
AOUTL4P
AOUTL3P
AVDD
VREFL1
DVSS
45
46
47
TVDD
VDD18
9
DSDL4
10
DSDR4
11
DZF /SMUTE
48
PDN
24
23
22
21
VREFH1
AOUTR1P
AOUTR1N
AOUTL2P
12
CAD1/DCHAIN
28
27
26
25
VREFL2
AOUTL2N
AOUTR2N
VREFH2
Back Pad: Note 1
Note 1. The exposed pad at back face of the package must be open or connected to the ground of the board.

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■Pin Functions
No.
Pin Name
I/O
Function
PD State
1
MCLK
I
External Master Clock Input Pin
Hi-Z
2
BICK
I
Audio Serial Data Clock Pin in PCM mode
Hi-z
DCLK
I
DSD Clock Pin in DSD mode
3
LRCK
I
Input Channel Clock Pin in PCM mode
Hi-Z
DSDL1
I
Audio Serial Data Input in DSD mode
4
SDTI1
I
Audio Serial Data Input in PCM mode
Hi-Z
DSDR1
I
Audio Serial Data Input in DSD mode
5
SDTI2
I
Audio Serial Data Input in PCM mode
Hi-Z
DSDL2
I
Audio Serial Data Input in DSD mode
6
SDTI3
I
Audio Serial Data Input in PCM mode
100kΩ
Pull down
DSDR2
I
Audio Serial Data Input in DSD mode
TDMO1
O
Audio Serial Data Output in Daisy Chain mode
7
SDTI4
I
Audio Serial Data Input in PCM mode
100kΩ
Pull down
DSDL3
I
Audio Serial Data Input in DSD mode
TDMO2
O
Audio Serial Data Output in Daisy Chain mode
8
DSDR3
I
Audio Serial Data Input in DSD mode
Hi-Z
9
DSDL4
I
Audio Serial Data Input in DSD mode
Hi-Z
10
DSDR4
I
Audio Serial Data Input in DSD mode
Hi-Z
11
DZF
O
Zero Input Detect in I2C Bus or 3-wire serial control mode
100kΩ
Pull down
SMUTE
I
Soft Mute Pin in Parallel control mode.
When this pin is changed to “H”, soft mute cycle is initiated.
When it is returning to “L”, the output mute is released.
12
CAD1
I
Chip Address 0 Pin in I2C Bus or 3-wire serial control mode
Hi-Z
DCHAIN
I
Daisy Chain Mode select pin in Parallel control mode.
13
SDA
I/O
Control Data Pin in I2C Bus serial control mode
Hi-Z
CDTI
I
Control Data Input Pin in 3-wire serial control mode
TDM0
I
TDM Mode select pin in Parallel control mode.
14
SCL
I
Control Data Clock Pin in I2C Bus serial control mode
Hi-Z
CCLK
I
Control Data Clock Pin in 3-wire serial control mode
TDM1
I
TDM Mode select pin in Parallel control mode.
15
CAD0_I2C
I
Chip Address 0 Pin in I2C Bus serial control mode
Hi-Z
CSN
I
Chip Select Pin in 3-wire serial control mode
DIF
I
Audio Data Format Select in Parallel control mode.
“L”: 32-bit MSB, “H”: 32-bit I2S
16
PS
I
(I2C pin = “H”)
Control Mode Select Pin
“L”: I2C Bus serial control mode, “H”: Parallel control mode.
Hi-Z
CAD0_SPI
I
(I2C pin = “L”)
Chip Address 0 Pin in 3-wire serial control mode
17
I2C
I
Control Mode Select Pin
“L”: 3-wire serial control mode
“H”: I2C Bus serial control mode or Parallel control mode.
Hi-Z
18
AOUTL1P
O
Lch Positive Analog Output 1 Pin
Hi-Z
19
AOUTL1N
O
Lch Negative Analog Output 1 Pin
Hi-Z
20
VREFL1
I
Negative Voltage Reference Input Pin, AVSS
Hi-Z
21
VREFH1
I
Positive Voltage Reference Input Pin, AVDD
Hi-Z

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No.
Pin Name
I/O
Function
PD State
22
AOUTR1N
O
Rch Negative Analog Output 1 Pin
Hi-Z
23
AOUTR1P
O
Rch Positive Analog Output 1 Pin
Hi-Z
24
AOUTL2P
O
Lch Positive Analog Output 2 Pin
Hi-Z
25
AOUTL2N
O
Lch Negative Analog Output 2 Pin
Hi-Z
26
VREFL2
I
Negative Voltage Reference Input Pin, AVSS
Hi-Z
27
VREFH2
I
Positive Voltage Reference Input Pin, AVDD
Hi-Z
28
AOUTR2N
O
Rch Negative Analog Output 2 Pin
Hi-Z
29
AOUTR2P
O
Rch Positive Analog Output 2 Pin
Hi-Z
30
AVSS
-
Analog Ground Pin
－
31
AVDD
-
Analog Power Supply Pin, 3.0V5.5V
－
32
AOUTL3P
O
Lch Positive Analog Output 3 Pin
Hi-Z
33
AOUTL3N
O
Lch Negative Analog Output 3 Pin
Hi-Z
34
VREFH3
I
Positive Voltage Reference Input Pin, AVDD
Hi-Z
35
VREFL3
I
Negative Voltage Reference Input Pin, AVSS
Hi-Z
36
AOUTR3N
O
Rch Negative Analog Output 3 Pin
Hi-Z
37
AOUTR3P
O
Rch Positive Analog Output 3Pin
Hi-Z
38
AOUTL4P
O
Lch Positive Analog Output 4 Pin
Hi-Z
39
AOUTL4N
O
Lch Negative Analog Output 4 Pin
Hi-Z
40
VREFH4
I
Positive Voltage Reference Input Pin, AVDD
Hi-Z
41
VREFL4
I
Negative Voltage Reference Input Pin, AVSS
Hi-Z
42
AOUTR4N
O
Rch Negative Analog Output 4 Pin
Hi-Z
43
AOUTR4P
O
Rch Positive Analog Output 4 Pin
Hi-Z
44
LDOE
I
Internal LDO Enable Pin.
“L”: Disable, “H”: Enable
Hi-Z
45
TVDD
-
Digital Power Supply Pin, 3.0V3.6V
－
46
DVSS
-
Digital Ground Pin
－
47
VDD18
O
LDO Output Pin (LDOE pin = “H”)
This pin should be connected to DVSS with 1.0µF.
(Note 4)
I
1.8V Power Input Pin (LDOE pin = “L”)
48
PDN
I
Power-Down & Reset Pin
When this pin is “L”, the AK4458 is powered-down and the
control registers are reset to default state.
Hi-Z
Note 2. All input pins except internal pull-up/down pins should not be left floating.
Note 3. PCM mode and DSD mode are controlled by registers. Daisy Chain mode is controlled by both
registers and pins.
Note 4. This pin outputs DVSS when the LDOE pin = “H”and Hi-z when the LDOE pin = “L”.
■Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Pin Name
Setting
Analog
AOUTL1P/N, AOUTR1P/N
AOUTL2P/N, AOUTR2P/N
AOUTL3P/N, AOUTR3P/N
AOUTL4P/N, AOUTR4P/N
These pins must be open.
Digital
DZF
This pin must be open.
SDTI1-4, DSDR3, DSDL4, DSDR4
These pins must be connected to DVSS

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6.Absolute Maximum Ratings
(AVSS =DVSS =0V; Note 5)
Parameter
Symbol
Min.
Max.
Unit
Power Supplies:
Analog
Digital I/O
Digital Core
|AVSS DVSS|
AVDD
TVDD
VDD18
GND
0.3
0.3
0.3
-
6.0
4.0
2.5
0.3
V
V
V
V
Input Current, Any Pin Except Supplies
IIN
-
10
mA
Digital Input Voltage
VIND
0.3
TVDD+0.3
V
Ambient Temperature (Power applied)
When the back pad is connected to ground
When the back pad is open
Ta
Ta
40
40
105
85
C
C
Storage Temperature
Tstg
65
150
C
Note 5. All voltages with respect to ground.
Note 6. AVSS and DVSS must be connected to the same potential.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7.Recommended Operation Conditions
(AVSS =DVSS =0V; Note 5)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power Supplies
Analog
(LDOE pin= “L”) (Note 7)
Digital I/O
Digital Core
(LDOE pin = “H”)(Note 8)
Digital I/O
AVDD
TVDD
VDD18
TVDD
3.0
VDD18
1.7
3.0
5.0
1.8
1.8
3.3
5.5
3.6
1.98
3.6
V
V
V
V
Voltage Reference
“H”voltage reference “L”
voltage reference
VREFH1-4
VREFL1-4
AVDD0.5
-
-
AVSS
AVDD
-
V
V
Note 7. TVDD must be powered up before VDD18 when the LDOE pin = “L”. The power up sequence
between AVDD and TVDD or AVDD and VDD18 is not critical.
Note 8. When LDOE pin = “H”, the internal LDO supplies 1.8V (typ). The power up sequences between
AVDD and TVDD, AVDD and VDD18 are not critical.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.

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8.Electrical Characteristics
■Analog Characteristics
(1) AVDD = 5.0V
(Ta=25C: TVDD=3.3V, AVDD=5.0V: AVSS= DVSS=0V: VREFH1/2/3/4=AVDD, VREFL1/2/3/4=
AVSS: fs=44.1kHz: BICK=64fs: Signal Frequency=1kHz: 24-bit Input Data: RL 2k: measurement
bandwidth = 20Hz ~ 20kHz: External Circuit: (Figure 75), unless otherwise specified.)
Parameter
Min.
Typ.
Max.
Unit
Resolution
-
-
32
bit
Dynamic Characteristics (Note 9)
THD+N
fs=44.1kHz
BW=20kHz
0dBFS
60dBFS
-
-
-107
-52
-100
-
dB
dB
fs=96kHz
BW=40kHz
0dBFS
60dBFS
-
-
-104
-48
-
-
dB
dB
fs=192kHz
BW=40kHz
BW=80kHz
0dBFS
60dBFS
60dBFS
-104
-48
-44
-
-
-
dB
dB
dB
Dynamic Range (60dBFS with A-weighted) (Note 10)
110
115
-
dB
S/N (A-weighted) (Note 11)
110
115
-
dB
Interchannel Isolation (1kHz)
100
110
-
dB
DC Accuracy
Interchannel Gain Mismatch
-
0
0.3
dB
Gain Drift (Note 12)
-
20
-
ppm/C
Output Voltage (Note 13)
2.65
2.8
2.95
Vpp
Load Resistance (Note 14)
2
-
-
k
Load Capacitance (Note 14)
-
-
30
pF
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
AVDD
TVDD (fs = 44.1kHz)
TVDD (fs = 96kHz)
TVDD (fs = 192kHz)
-
-
-
-
31
8
13
20
41
11
17
26
mA
mA
mA
mA
Power down (PDN pin = “L”) (Note 15)
AVDD+TVDD
-
1
100
A

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(2) AVDD = 3.3V
(Ta=25°C: TVDD=3.3V, AVDD=3.3V: AVSS= DVSS=0V: VREFH1/2/3/4=AVDD, VREFL1/2/3/4=
AVSS: fs=44.1kHz: BICK=64fs: Signal Frequency=1kHz: 24-bit Input Data: RL 2k: measurement
bandwidth = 20Hz ~ 20kHz: External Circuit: (Figure 75), unless otherwise specified.)
Parameter
Min.
Typ.
Max.
Unit
Resolution
32
bit
Dynamic Characteristics (Note 9)
THD+N
fs=44.1kHz
BW=20kHz
0dBFS
60dBFS
-
-
-93
-48
-86
-
dB
dB
fs=96kHz
BW=40kHz
0dBFS
60dBFS
-
-
-92
-45
-
-
dB
dB
fs=192kHz
BW=40kHz
BW=80kHz
0dBFS
60dBFS
60dBFS
-92
-45
-41
-
-
-
dB
dB
dB
Dynamic Range(60dBFS with A-weighted) (Note 10)
106
111
-
dB
S/N (A-weighted) (Note 11)
106
111
-
dB
Inter channel Isolation (1kHz)
100
110
-
dB
DCAccuracy
Inter channel Gain Mismatch
0
0.3
dB
Gain Drift (Note 12)
-
20
-
ppm/°C
Output Voltage (Note 13)
1.66
1.85
2.04
Vpp
Load Resistance (Note 14)
2
-
-
k
Load Capacitance (Note 14)
-
-
30
pF
Power Supplies
Power Supply Current
Normal operation
(PDN pin = “H”, input opposite phase to each Lch and Rch)
AVDD
TVDD (fs = 44.1kHz)
TVDD (fs = 96kHz)
TVDD (fs = 192kHz)
-
-
-
-
24
8
13
20
-
-
-
-
mA
mA
mA
mA
Power down (PDN pin = “L”) (Note 15)
AVDD+TVDD
1
100
A
Note 9. Measured by Audio Precision, System Two. Averaging mode.
Note 10. Figure 75 External LPF Circuit Example 1. 100dB for 16-bit data.
Note 11. Figure 75 External LPF Circuit Example 1. S/N does not depend on input data size.
Note 12. The voltage on (VREFH1/2/3/4 VREFL1/2/3/4) is held +5V externally.
Note 13. The full scale voltage when applying a 1kHz sine wave (0dB) in PCM mode, or when applying a
1kHz sine wave (25~75% duty) in DSD mode. Output voltage scales with the voltage of
(VREFH1/2/3/4 VREFL1/2/3/4).
DAC1: AOUT (typ.@0dB) = (AOUT+) (AOUT) = 2.8Vpp (VREFH1 VREFL1)/5
DAC2: AOUT (typ.@0dB) = (AOUT+) (AOUT) = 2.8Vpp (VREFH2 VREFL2)/5
DAC3: AOUT (typ.@0dB) = (AOUT+) (AOUT) = 2.8Vpp (VREFH3 VREFL3)/5
DAC4: AOUT (typ.@0dB) = (AOUT+) (AOUT) = 2.8Vpp (VREFH4 VREFL4)/5
Note 14. Regarding Load Resistance, AC load is 2k(min) with a DC cut capacitor (Figure 75). DC load is
3.5k(min) without a DC cut capacitor (Figure 75). The load resistance value is with respect to
ground. Analog characteristics are sensitive to capacitive load that is connected to the output pin.
Therefore the capacitive load must be minimized.
Note 15. In the power down mode. All other digital input pins including clock pins (MCLK, BICK and LRCK)
are held DVSS.

[AK4458]
014011794-E-01 2015/08
- 13 -
■Sharp Roll-Off Filter Characteristics
Sharp Roll-Off Filter Characteristics (fs= 44.1kHz)
(Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Normal Speed Mode; DEM=OFF;
SLOW bit = “0”, SD bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Pass band (Note 16)
0.05dB
PB
0
20.0
kHz
3.0dB
PB
21.5
kHz
Pass band Ripple (Note 17)
PR
-0.0032
0.0032
dB
Stop band (Note 16)
SB
24.1
kHz
Stop band Attenuation (Note 19)
SA
80
dB
Group Delay (Note 18)
GD
-
26.8
-
1/fs
Frequency Response (Note 19)
0.07dB
-
0
20.0
kHz
Digital Filter + SCF (Note 19)
Frequency Response: 0 20.0kHz
-0.2
0.1
dB
Sharp Roll-Off Filter Characteristics (fs= 96kHz)
(Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Double SpeedMode; DEM=OFF; SLOW bit = “0”,
SD bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Pass band (Note 16)
0.05dB
PB
0
43.5
kHz
3.0dB
PB
46.8
kHz
Pass band Ripple (Note 17)
PR
-0.0032
0.0032
dB
Stop band (Note 16)
SB
52.5
0
43.5
Stop band Attenuation (Note 19)
SA
80
dB
Group Delay (Note 18)
GD
-
26.8
-
1/fs
Frequency Response (Note 19)
0.07dB
-
0
43.5
kHz
Digital Filter + SCF (Note 19)
Frequency Response: 0 40.0kHz
-0.3
0.1
dB
Sharp Roll-Off Filter Characteristics (fs= 192kHz)
(Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit = “0”,
SD bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Pass band (Note 16)
0.05dB
PB
0
87.0
kHz
3.0dB
PB
93.6
kHz
Pass band Ripple (Note 17)
PR
-0.0032
0.0032
dB
Stop band (Note 16)
SB
105
kHz
Stop band Attenuation (Note 19)
SA
80
dB
Group Delay (Note 18)
GD
-
26.8
-
1/fs
Frequency Response (Note 19)
0.07dB
-
0
87.0
kHz
Digital Filter + SCF (Note 19)
Frequency Response: 0 80.0kHz
-1
0.1
dB
Note 16. The pass band and stop band frequencies scale with fs. For example, PB=0.4535×fs, SB=0.546×fs.
Note 17. It is the pass bandgain amplitude of the double over sampling filter at the first step of the Interpolator.
Note 18. The calculating delay time which occurred by digital filtering. This time is from setting the
16/20/24/32bit data of both channels to input register to the output of analog signal.
Note 19. The output level is assumed as 0dB when inputting a 1kHz 0dB sine wave.
*Digital filter characteristics are based on simulation results.

[AK4458]
014011794-E-01 2015/08
- 14 -
■Slow Roll-Off Filter Characteristics
Slow Roll-Off Filter Characteristics (fs = 44.1kHz)
(Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Normal Speed Mode; DEM=OFF;
SLOW bit = “1”, SD bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Pass band (Note 20)
0.05dB
PB
0
8.1
kHz
3.0dB
PB
18.2
kHz
Pass band Ripple (Note 17)
PR
-0.043
0.043
dB
Stop band (Note 20)
SB
39.2
Stop band Attenuation (Note 19)
SA
73
dB
Group Delay (Note 18)
GD
-
6.3
-
1/fs
Frequency Response (Note 19)
0.05dB
-
0
8.1
kHz
Digital Filter + SCF (Note 19)
Frequency Response: 0 20.0kHz
-5
0.1
dB
Slow Roll-Off Filter Characteristics (fs = 96kHz)
(Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Double SpeedMode; DEM=OFF; SLOW bit = “1”,
SD bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Pass band (Note 20)
0.05dB
PB
0
17.7
kHz
3.0dB
PB
39.5
kHz
Pass band Ripple (Note 17)
PR
-0.043
0.043
dB
Stop band (Note 20)
SB
85.3
Stop band Attenuation (Note 19)
SA
73
dB
Group Delay (Note 18)
GD
-
6.3
-
1/fs
Frequency Response (Note 19)
0.05dB
PB
0
17.7
kHz
Digital Filter + SCF (Note 19)
Frequency Response: 0 40.0kHz
-5
0.1
dB
Slow Roll-Off Filter Characteristics (fs = 192kHz)
(Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit = “1”,
SD bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Pass band (Note 20)
0.05dB
PB
0
35.5
kHz
3.0dB
PB
79.0
kHz
Pass band Ripple (Note 17)
PR
-0.043
0.043
dB
Stop band (Note 20)
SB
171
kHz
Stop band Attenuation (Note 19)
SA
73
dB
Group Delay (Note 18)
GD
-
6.3
-
1/fs
Frequency Response (Note 19)
0.05dB
PB
0
35.5
kHz
Digital Filter + SCF (Note 19)
Frequency Response: 0 80.0kHz
-5
0.1
dB
Note 20. The pass band and stop band frequencies scale with fs. For example, PB=0.185×fs, SB=0.888×fs.

[AK4458]
014011794-E-01 2015/08
- 15 -
■Short Delay Sharp Roll-Off Filter Characteristics
Short Delay Sharp Roll-Off Filter Characteristics (fs= 44.1kHz)
(Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Normal Speed Mode; DEM=OFF;
SLOW bit = “0”, SD bit=“1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Pass band (Note 16)
0.05dB
PB
0
20.0
kHz
3.0dB
PB
21.5
kHz
Pass band Ripple (Note 17)
PR
-0.0031
0.0031
dB
Stop band (Note 16)
SB
24.1
kHz
Stop band Attenuation (Note 19)
SA
80
dB
Group Delay (Note 18)
GD
-
5.8
-
1/fs
Frequency Response (Note 19)
0.07dB
-
0
20.0
kHz
Digital Filter + SCF (Note 19)
Frequency Response: 0 20.0kHz
-0.2
0.1
dB
Short Delay Sharp Roll-Off Filter Characteristics (fs= 96kHz)
(Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Double SpeedMode; DEM=OFF; SLOW bit = “0”,
SD bit=“1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Pass band (Note 16)
0.05dB
PB
0
43.5
kHz
3.0dB
PB
46.8
kHz
Pass band Ripple (Note 17)
PR
-0.0031
0.0031
dB
Stop band (Note 16)
SB
52.5
0
43.5
Stop band Attenuation (Note 19)
SA
80
dB
Group Delay (Note 18)
GD
-
5.8
-
1/fs
Frequency Response (Note 19)
0.07dB
-
0
43.5
kHz
Digital Filter + SCF (Note 19)
Frequency Response: 0 40.0kHz
-0.3
0.1
dB
Short Delay Sharp Roll-Off Filter Characteristics (fs= 192kHz)
(Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit = “0”,
SD bit=“1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Pass band (Note 16)
0.05dB
PB
0
87.0
kHz
3.0dB
PB
93.6
kHz
Pass band Ripple (Note 17)
PR
-0.0031
0.0031
dB
Stop band (Note 16)
SB
105
kHz
Stop band Attenuation (Note 19)
SA
80
dB
Group Delay (Note 18)
GD
-
5.8
-
1/fs
Frequency Response (Note 19)
0.07dB
-
0
87.0
kHz
Digital Filter + SCF (Note 19)
Frequency Response: 0 80.0kHz
-1
0.1
dB

[AK4458]
014011794-E-01 2015/08
- 16 -
■Short Delay Slow Roll-Off Filter Characteristics
Short Delay Slow Roll-Off Filter Characteristics (fs= 44.1kHz)
(Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Normal Speed Mode; DEM=OFF;
SLOW bit = “1”, SD bit=“1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Pass band (Note 21)
0.05dB
PB
0
11.1
kHz
3.0dB
PB
19.4
kHz
Pass band Ripple (Note 17)
PR
-0.05
0.05
dB
Stop band (Note 21)
SB
38.1
kHz
Stop band Attenuation (Note 19)
SA
82
dB
Group Delay (Note 18)
GD
-
4.8
-
1/fs
Frequency Response (Note 19)
0.05dB
-
0
11.1
kHz
Digital Filter + SCF (Note 19)
Frequency Response: 0 20.0kHz
-5
0.1
dB
Short Delay Slow Roll-Off Filter Characteristics (fs= 96kHz)
(Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Double SpeedMode; DEM=OFF; SLOW bit = “1”,
SD bit=“1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Pass band (Note 21)
0.05dB
PB
0
24.2
kHz
3.0dB
PB
42.1
kHz
Pass band Ripple (Note 17)
PR
-0.05
0.05
dB
Stop band (Note 21)
SB
83.0
43.5
Stop band Attenuation (Note 19)
SA
82
dB
Group Delay (Note 18)
GD
-
4.8
-
1/fs
Frequency Response (Note 19)
0.05dB
-
0
24.2
kHz
Digital Filter + SCF (Note 19)
Frequency Response: 0 40.0kHz
-5
0.1
dB
Short Delay Slow Roll-Off Filter Characteristics (fs= 192kHz)
(Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit = “1”,
SD bit=“1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Pass band (Note 21)
0.05dB
PB
0
48.4
kHz
3.0dB
PB
84.3
kHz
Pass band Ripple (Note 17)
PR
-0.05
0.05
dB
Stop band (Note 21)
SB
165.9
kHz
Stop band Attenuation (Note 19)
SA
82
dB
Group Delay (Note 18)
GD
-
4.8
-
1/fs
Frequency Response (Note 19)
0.05dB
-
0
48.4
kHz
Digital Filter + SCF (Note 19)
Frequency Response: 0 80.0kHz
-5
0.1
dB
Note 21. The pass band and stop band frequencies scale with fs. For example, PB=0.252×fs, SB=0.864×fs.

[AK4458]
014011794-E-01 2015/08
- 17 -
■DSD Mode Characteristics
(1) DSDF bit= “0”
(Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; fs=44.1kHz; D/P bit=“1”, DSDF bit=“0”)
Parameter
Min.
Typ.
Max.
Unit
Digital Filter Response
Frequency
Response
(Note 22)
DSDSEL[1:0]
“00”
20kHz
50kHz
100kHz
-0.8
-5.5
-19.9
dB
“01”
40kHz
200kHz
400kHz
-0.8
-5.5
-19.9
dB
“10”
80kHz
400kHz
800kHz
-0.8
-5.5
-19.9
dB
(2) DSDF bit= “1”
(Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V; fs=44.1kHz; D/P bit=“1”, DSDF bit=“1”)
Parameter
Min.
Typ.
Max.
Unit
Digital Filter Response
Frequency
Response
(Note 22)
DSDSEL[1:0]
“00”
20kHz
100kHz
200kHz
-0.2
-6.3
-23.7
dB
“01”
40kHz
200kHz
400kHz
-0.2
-6.3
-23.7
dB
“10”
80kHz
400kHz
800kHz
-0.2
-6.3
-23.7
dB
Note 22. In DSD mode, the signal level is ranging from25% to 75%. Peak levels of DSD signal above this duty
are not recommended by SACD format book (Scarlet Book).
Note 23. It is assumed that the output level is 0dB when the input signal is 1kHz and the duty range is between
25 ~ 75%.The output level is assumed as 0dB when applying a 1kHz sine wave in 25~ 75% duty.
*Digital filter characteristics are based on simulation results.
■DC Characteristics
(Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
TVDD=1.7 3.0V
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
80%TVDD
-
-
-
-
20%TVDD
V
V
TVDD=3.0V 3.6V
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
70%TVDD
-
-
-
-
30%TVDD
V
V
High-Level Output Voltage
(LRCK, BICK pins: Iout=-100µA)
Low-Level Output Voltage
(excpt SDA pin : Iout= 100µA)
(SDA pin, 2.0V TVDD 3.6V: Iout= 3mA)
(SDA pin, 1.7V TVDD 2.0V: Iout= 3mA)
VOH
VOL
VOL
VOL
TVDD0.5
-
-
-
-
-
-
-
0.5
0.4
20%TVDD
V
V
V
V
Input Leakage Current
Iin
-
-
10
A

[AK4458]
014011794-E-01 2015/08
- 18 -
■Switching Characteristics
(Ta=-40 105C; AVDD=3.0 5.5V, TVDD=1.7 3.6V, CL=20pF)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Master Clock Timing
Frequency
Duty Cycle
Minimum Pulse Width
fCLK
dCLK
tCLKH
tCLKL
2.048
40
9.155
9.155
49.152
60
MHz
%
ns
ns
LRCK Frequency (Note 24)
Normal Mode (TDM1-0 bits = “00”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct speed mode
Hex speed mode
Duty Cycle
fsn
fsd
fsq
fso
fsh
Duty
8
54
108
45
384
768
54
108
216
55
kHz
kHz
kHz
kHz
kHz
%
TDM128 mode (TDM1-0 bits = “01”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
High time
Low time
fsn
fsd
fsq
tLRH
tLRL
8
54
108
1/128fs
1/128fs
54
108
216
kHz
kHz
kHz
nsec
ns
TDM256 mode (TDM1-0 bits = “10”)
Normal Speed Mode High time
Double Speed Mode
High time
Low time
fsn
fsd
tLRH
tLRL
8
54
1/256fs
1/256fs
54
108
kHz
kHz
nsec
nsec
TDM512 mode (TDM1-0 bits = “11”)
Normal Speed Mode
High time
Low time
fsn
tLRH
tLRL
8
1/512fs
1/512fs
54
kHz
nsec
nsec
PCM Audio Interface Timing
Normal Mode (TDM1-0 bits = “00”)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct speed mode
Hex speed mode
BICK Pulse Width Low
BICK Pulse Width High
BICK “”to LRCK Edge (Note 25)
LRCK Edge to BICK “”(Note 25)
SDTI1/2/3/4 Hold Time
SDTI1/2/3/4 Setup Time
tBCK
tBCK
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/256fsn
1/128fsd
1/64fsq
1/64fso
1/64fsh
9
9
5
5
5
5
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec

[AK4458]
014011794-E-01 2015/08
- 19 -
Parameter
Symbol
Min.
Typ.
Max.
Unit
TDM128 mode (TDM1-0 bits = “01”)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
BICK Pulse Width High
BICK “”to LRCK Edge (Note 25)
LRCK Edge to BICK “”(Note 25)
SDTI1/2 Hold Time
SDTI1/2 Setup Time
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fsn
1/128fsd
1/128fsq
14
14
14
14
5
5
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
TDM256 mode (TDM1-0 bits = “10”)
BICK Period
Normal Speed Mode
Double Speed Mode (Note 26)
BICK Pulse Width Low
BICK Pulse Width High
BICK “”to LRCK Edge (Note 25)
LRCK Edge to BICK “”(Note 25)
TDMO1/2 Setup time BICK “”
TDMO1/2 Hold time BICK “”(Note 28)
SDTI1/2 Hold Time
SDTI1/2 Setup Time
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tBSS
tBSH
tSDH
tSDS
1/256fsn
1/256fsd
14
14
14
14
5
5
5
5
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
TDM512 mode (TDM1-0 bits = “11”)
BICK Period
Normal Speed Mode (Note 27)
BICK Pulse Width Low
BICK Pulse Width High
BICK “”to LRCK Edge (Note 25)
LRCK Edge to BICK “”(Note 25)
TDMO1 Setup time BICK “”
TDMO1 Hold time BICK “”(Note 28)
SDTI1 Hold Time
SDTI1 Setup Time
tBCK
tBCKL
tBCKH
tBLR
tLRB
tBSS
tBSH
tSDH
tSDS
1/512fsn
14
14
14
14
5
5
5
5
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec

[AK4458]
014011794-E-01 2015/08
- 20 -
Parameter
Symbol
Min.
Typ.
Max.
Unit
DSDAudio Interface Timing
(64 mode, DSDSEL 1-0 bits = “00”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R (Note 29)
tDCK
tDCKL
tDCKH
tDDD
144
144
20
1/64fs
20
nsec
nsec
nsec
nsec
(128 mode, DSDSEL1-0 bits = “01”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R (Note 29)
tDCK
tDCKL
tDCKH
tDDD
72
72
10
1/128fs
10
nsec
nsec
nsec
nsec
(256 mode, DSDSEL 1-0 bits = “10”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R (Note 29)
tDCK
tDCKL
tDCKH
tDDD
36
36
5
1/256fs
5
nsec
nsec
nsec
nsec
Note 24. When the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK4458 should be
reset by the PDN pin or RSTN bit.
Note 25. BICK rising edge must not occur at the same time as LRCK edge.
Note 26. fsd (max) = 96kHz when TVDD < 3.0V in Daisy Chain mode.
Note 27. fsd (max) = 48kHz when TVDD < 3.0V in Daisy Chain mode.
Note 28. tBSH (min) = 4 nsec when TVDD < 2.6V and the LDOE pin = “L”.
Note 29. DSD data transmitting device must meet this time.
tDDD is defined from a falling edge of DCLK “↓” to a DSDL/R edge when DCKB bit = “0” and it
is defined from a rising edge of DCLK “↑” to a DSDL/R edge when DCKB bit = “1”.