Asahi KASEI AP4470 User manual

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1. General Description
The AP4470 is an ultra-low consumption power management chip that integrates a step-up DC/DC
converter and hysteresis comparators. The AP4470 requires only 0.20V input to start boosting without
the need for an external transformer. The AP4470 has hysteresis operation switch that can control the
power supply for target devices (sensors, wireless modules, LEDs) while protecting external storage
(capacitors), and the target.
1μW DC input is enough to startup the AP4470. Converted output is stored to external storage device
and the AP4470 monitors the device. When the voltage of external storage reaches 3.3V, the AP4470
automatically starts supplying to the target device and stops supplying if the voltage drops down to
2.6V. Overvoltage protection function works at 3.55V.
2-types of power indicators offer reset function and trigger switch function with zero standby current.
The trigger(Startup FLAG) is achieved by a signal that is output when DC/DC converter becomes
active. The reset(Power Good) is a signal that indicates the AP4470 starts supplying, which means
external storage’s voltage reaches 3.3V.
The AP4470 is ideally suited for several W to several mW sources energy harvesting. This provides a
self-powered wireless sensor node with simple hardware design.
2. Features
Startup voltage : Cold start from 0.20V typical
DC/DC switching frequency : 60kHz typical at VIN=0.4V
Operation Voltage : up to 1.0V (VIN)
up to 5.5V (VDD1 / VDD2)
Operation temperature : -30 ~ +85ºC
Power Consumption
DC/DC converter is active : 7A typical at VIN=0.4V
DC/DC converter is off : 0.5A typical at VIN=0.4V
(The AP4470 supplies power including over charge
protection current)
DC/DC active indicator
Power Good indicator
DC/DC disable function
On-chip rectifier diode for DC/DC converting (using external diode is also available)
Support high impedance power sources up to tens of k
Package : 20-pin HWQFN (3.0mm×3.0mm×0.75mm 0.5mm pitch)
3. Applications
Energy Harvesting
➢Wireless Sensor Node
➢Wearable and Portable Device
Zero standby current trigger switch
Example of Energy Harvester (several W to several mW sources)
➢Ambient Light, Single cell solar battery
➢Vibration
➢Thermal
➢Microbial Fuel Cell
Ultra-Low Power Step-up DC/DC Converter
for Energy Harvesting Applications
AP4470

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4. Table of Contents
1. General Description ............................................................................................................................ 1
2. Features .............................................................................................................................................. 1
3. Applications......................................................................................................................................... 1
4. Table of Contents ................................................................................................................................ 2
5. Block Diagram..................................................................................................................................... 3
5.1. Block Diagram.............................................................................................................................. 3
5.2. Block Function ............................................................................................................................. 3
6. Pin Configuration and Function .......................................................................................................... 4
6.1. Pin Configuration ......................................................................................................................... 4
6.2. Pin Function ................................................................................................................................. 4
6.3. The connection of unused pins.................................................................................................... 5
7. Absolute Maximum Ratings ................................................................................................................ 6
8. Recommended Operating Conditions................................................................................................. 7
9. Digital DC Characteristics................................................................................................................... 7
10. Electrical Characteristics ................................................................................................................. 8
11. Description....................................................................................................................................... 9
11.1. Hysteresis comparator 1 (COMP1).......................................................................................... 9
11.1.1 When VDD1 voltage is increasing (Up phase) ........................................................................ 9
11.1.2 When VDD1 voltage is decreasing (Down phase) .................................................................. 9
11.2. Hysteresis comparator 2 (COMP2).......................................................................................... 9
11.3. Startup to DC/DC operation ................................................................................................... 10
11.3.1 Cold Startup ........................................................................................................................... 13
11.3.2 DC/DC .................................................................................................................................... 13
11.3.2.1 When (ISTRG > (IOUT + IVDD1 + IVDD2)).................................................................................... 13
11.3.2.2 When (ISTRG < (IOUT + IVDD1 + IVDD2)).................................................................................... 13
11.4. Power Good ........................................................................................................................... 14
11.5. Startup FLG............................................................................................................................ 15
12. Test Circuits................................................................................................................................... 16
12.1. External Circuit Example........................................................................................................ 16
12.2. PCB Guidline.......................................................................................................................... 17
13. Typical Characteristics .................................................................................................................. 18
13.1. Cold Startup ........................................................................................................................... 18
13.2. Switching Frequency.............................................................................................................. 18
13.3. Low side ON pulse width ....................................................................................................... 19
13.4. COMP1................................................................................................................................... 19
13.5. COMP2................................................................................................................................... 20
13.6. Current consumption.............................................................................................................. 20
13.7. Load curve.............................................................................................................................. 22
14. Recommended External Circuit .................................................................................................... 23
14.1. External Circuit Example........................................................................................................ 23
14.2. Reference PCB ...................................................................................................................... 24
15. Packages....................................................................................................................................... 25
15.1. Outline Dimensions................................................................................................................ 25
15.2. Marking................................................................................................................................... 25
16. Ordering Guide.............................................................................................................................. 26
17. Revision History............................................................................................................................. 26
IMPORTANT NOTICE.............................................................................................................................. 27

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5. Block Diagram
5.1. Block Diagram
Figure 5.1.1 AP4470 Block Diagram
5.2. Block Function
Block
Description
Cold Startup
The cold startup becomes active by DC voltage from VIN input. This block does
DC/DC converting to VBOOST and output converted input to the driver block.
Driver
The driver delivers converted input by the cold startup to the LSW and the
LSW2.
LSW
Following output from the driver, the LSW works as a current sink from SW pin.
LSW2
Triggered by a DC/DC converting active signal from the driver, and then output
“Low” to STUP_FLG pin.
HSW
The HSW rectifies input from ANODE pin to CATHODE pin.
(ANODE pin = anode, CATHODE pin= cathode for diode connection)
COMP1
The COMP1 is a hysteresis comparator circuit for VDD1 input voltage detection.
The reference voltages VDETH1 and VDETL1 are provided by an internal
circuit. The comparison result is output to OUT1.
COMP2
The COMP2 is a hysteresis comparator circuit for VDD2 input voltage detection.
The reference voltages VDETH2 and VDETL2 are provided by an internal
circuit. The comparison result is used to control on-chip HSW2 switch and an
open drain LSW3 switch.

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6. Pin Configuration and Function
6.1. Pin Configuration
Figure 6.1.1 Pin Configuration (Top view)
6.2. Pin Function
Table 6.2.1 Pin Function Description
Pin
#
Pin Name
I/O
Status when
PDH_STUP = ” High ”
Function
1
VSS
G
-
Ground
2
N.C.
-
No connect pin
3
VIN
P
-
Power supply input
4
VBOOST
AO
Hi-Z
This pin is not for current supply to an external
circuit.
5
TEST1
-
-
For test purposes.
This pin should be connected to VSS.
6
TEST2
-
-
For test purposes.
This pin should be connected to VSS.
7
TEST3
-
-
For test purposes.
This pin should be connected to VSS.
8
TEST4
-
-
For test purposes.
This pin should be connected to VSS.
9
TEST5
-
-
For test purposes.
This pin should be connected to VSS.
10
STUP_FLG
AO
Hi-Z
DC/DC converting start flag output pin.
Open drain output.
STUP_FLG pin outputs “Low” when DC/DC
converting is active.
11
RSTH_FLG
DI
10M
Pull-down
Disable pin for DC/DC converting start flag
function. (10M Pull-down)
Enable= “High”, Disable=”Low”
12
VDD1
P
-
Power supply for COMP1
13
OUT1
DO
-
COMP1 Output pin
14
PDH_STUP
DI
10M
Pull-down
Disable pin for the cold startup circuit.
(10M Pull-down)
Enable= “High” (Cold Startup circuit power down)

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15
VSYS
AO
-
HSW2 open drain output of COMP2
This pin is for system power supply
16
PGOOD
AO
-
LSW3 open drain output of COMP2
This pin is for Power Good indicator
17
VDD2
P
-
Power supply for COMP2
18
CATHODE
AO
Hi-Z
On-chip diode cathode pin
19
ANODE
AI
Hi-Z
On-chip diode anode pin
20
SW
AI
Hi-Z
LSW drain pin of DC/DC converter switch
-
TAB
-
-
Connecting the exposed pad (EPAD) that is
located on the bottom of the package to VSS is
recommended.
The pad can be left floating if needed.
AI: Analog input pin
AO: Analog output pin
DI: Digital input pin
DO: Digital output pin
P: Power supply pin
G: Ground pin
All digital input pins must NOT be left open.
6.3. The connection of unused pins
Please follow the tables below for unused AP4470 pins.
◼In the case of the on-chip diode (HSW) is not used
Table 6.3.1 On-chip diode is not used
Pin #
Name
I/O
Connection
Remarks
18
CATHODE
AO
Open or VSS
19
ANODE
AI
Open or VSS
◼In the case of the STUP_FLG is not used
Table 6.3.2 The STUP_FLG is not used
Pin #
Name
I/O
Connection
Remarks
10
STUP_FLG
AO
Open
Open drain output
11
RSTH_FLG
DI
VSS
◼In the case of the COMP1 is not used
Table 6.3.3 COMP1 is not used
Pin #
Name
I/O
Connection
Remarks
12
VDD1
P
Open
13
OUT1
DO
Open
◼In the case of the COMP2 is not used
Table 6.3.4 COMP2 is not used
Pin #
Name
I/O
Connection
Remarks
15
VSYS
AO
Open
16
PGOOD
AO
Open
17
VDD2
P
Open

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7. Absolute Maximum Ratings
Table 7.1 Absolute Maximum Ratings
(VSS=0V; *1)
Parameter
Symbol
Min.
Max.
Unit
Power Supply Volgtage
VIN pin
VDD1 pin
VDD2 pin
VIN
-0.3
6.5
V
Analog Pin Voltage
ANODE pin
SW pin
VAIN
-0.3
6.5
V
Digital Pin Voltage
RSTH_FLG pin
PDH_STUP pin
VDIN
-0.3
6.5
V
Input and output current
(*2)
IIN
-100
+100
mA
Power dissipation (*3)
Pd
-
2.33 (EPAD->VSS)
0.99 (EPAD->Float)
W
Storage Temperature
TSTG
-55
+150
ºC
Junction Temperature
TJ
-55
+125
ºC
Notes:
*1. All voltages are with reference to VSS = 0 V
*2. This specification is for all pins including VIN, VDD1, VDD2. Positive direction is input to pins.
*3. 74mm□-1.6t-4 layers FR-4 PCB using Sn-3.0Ag-0.5Cu solder.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal
operation is not guaranteed at these extremes.

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8. Recommended Operating Conditions
Table 8.1 Recommended Operating Conditions
(VSS=0V; *4)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Operation Temperature
Ta
-30
+85
ºC
Power Supply Volgtage
VIN
-
1.0
V
VDD1
1.2
5.5
V
VDD2
1.2
5.5
V
Note:
*4. All voltages are with reference to VSS = 0 V
WARNING: The specifications are applicable within operating range (supply voltage/operating temperature)
specified below.
9. Digital DC Characteristics
Table 9.1 Digital DC Characteristics
(VSS=0V; *5)
Parameter
Symbol
Min.
Typ.
Max.
Unit
High level input
voltage
(*6)
(*7)
VIH
2.0
-
-
V
Low level input
voltage
(*6)
(*7)
VIL
-
-
0.2×VIN
V
High level input
current
VIH= 2.0V
(*6)
(*7)
IIH
0.05
0.2
0.8
A
Low level input
current
VIL= 0V
(*6)
(*7)
IIL
-1
-
+1
A
High level output
Voltage
IOH=+100A
(*8)
VOH
0.8×VDD1
-
-
V
Low level output
voltage
IOL=-100A
(*9)
VOL
0.2×VDD1
V
Notes:
*5. All voltages are with reference to VSS = 0 V
*6. Digital Input pins: RSTH_FLG, PDH_STUP
*7. There is a protection diode to VDD1.
When higher input than VDD1 voltage is applied, the pin pulls current to the IC.
*8. Digital output pins: OUT1, VDD1 ≧(VDETH1 + 0.1V) = 3.65V
*9. Digital output pins:OUT1, VDD1 ≦(VDETL1 –0.1V) = 3.35V

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10. Electrical Characteristics
Unless otherwise noted, specifications apply for conditions of
Ta = -30 ~ +85ºC,
Load condition：Specified on Chapter 12 unless otherwise specified.
Table 10.1 Analog Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Unit
Description
Cold Startup
Minimum Input Voltage for Cold Start
(*10)
VINSTUP
-
0.20
0.30
V
Ta ≧+25ºC
-
-
0.40
V
Minimum Input Voltage
DC/DC converting up to 3.3V is
completed (*11), (*12)
VINDCDC
-
0.24
-
V
Ta=+25ºC
Switching Frequency
fSW
-
60
-
kHz
VIN=0.4V
Ta= +25ºC
Low Side Switching Time
TON
0.75
1.25
1.75
s
VIN=0.4V
Hysteresis comparator 1 (COMP1)
Detection Voltage “High”
VDETH1
3.45
3.55
3.595
V
Ta ≧+25ºC
Detection Voltage ”Low”
VDETL1
3.35
3.45
3.55
V
Ta ≧+25ºC
Hysteresis (VDETH1-VDETL1)
VHYS1
0.02
0.10
0.18
V
Ta ≧+25ºC
Hysteresis comparator 2 (COMP2)
Detection Voltage “High”
VDETH2
3.20
3.30
3.40
V
Ta ≧+25ºC
Detection Voltage ”Low”
VDETL2
2.50
2.60
2.70
V
Ta ≧+25ºC
Hysteresis (VDETH2-VDETL2)
VHYS2
0.62
0.70
0.78
V
Ta ≧+25ºC
HSW2 On-resistance
RONP
-
1.5
3.5

IOUT=10mA
IOUT :
output from VSYS pin
Current Consumption (*16)
Quiescent current with over voltage
protection consumption
(*13)
IDD0
-
0.45
-
A
VIN=0.2V
VDD1=VDD2=3.55V
PDH_STUP=3.55V
-
0.50
6
A
VIN=0.4V
VDD1=VDD2=3.55V
PDH_STUP=3.55V
Operation
Current
Self consumption
(*14)
+
COMP1/2 consumption
ICORE
-
0.15
-
A
VIN=0.2V
VDD1=VDD2=3.55V
PDH_STUP=0V
-
7
50
A
VIN=0.4V
VDD1=VDD2=3.55V
PDH_STUP=0V
Switching Current
(*12)
(*15)
ISW
-
3
-
A
VIN=0.2V
VDD1=VDD2=3.55V
PDH_STUP=0V
-
400
-
A
VIN=0.4V
VDD1=VDD2=3.55V
PDH_STUP=0V
Notes:
*10. The voltage that STUP_FLG pin outputs “Low”.
*11. On-chip diode (HSW) is used.
COMP1 and COMP2 are active. A 330F/25V electrolytic capacitor is connected to CSTRG.
*12. Guaranteed by design (Not tested)
*13. Including high level input current IIH that is described on Table 9.1 IIH=0.355A (PDH_STUP pin=3.55V)
*14. Power consumption for VIN pin.
*15. Sink current for SW pin
*16. VSYS pin and OUT1 pin drive currents, PGOOD pin and STUP_FLG pin sink currents are NOT included.

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11. Description
11.1. Hysteresis comparator 1 (COMP1)
11.1.1 When VDD1 voltage is increasing (Up phase)
The OUT1 pin will be in undefined status when VDD1 voltage is from VSS to AP4470 minimum
operating voltage(1.2V).
As Chapter 11.3.1 and 11.3.2 described, the AP4470 won’t accidentally stop DC/DC converting
because the PDH_STUP pin is set to “Low” by the on-chip pull-down resistor of PDH_STUP under
recommended circuit design.
The OUT1 outputs VSS when VDD1 volgate exceeds minimum operating voltage. When VDD1 voltage
reaches to the detection voltage (VDETH1), OUT1 outputs VDD1 voltage.
11.1.2 When VDD1 voltage is decreasing (Down phase)
When VDD1 voltage is higher than the detection voltage (VDETL1), OUT1 outputs VDD1 volatge.
When VDD1 goes under the detection voltage (VDETL1), OUT1 outputs VSS. OUT1 becomes Hi-Z
when VDD1 voltege becomes lower than AP4470 minimum operating voltage(1.2V).
Following Figure 11.1.1 shows Hysteresis comparator1 functions.
Figure 11.1.1 COMP1 Voltage detection
11.2. Hysteresis comparator 2 (COMP2)
The COMP2 controls on-chip HSW2 switch and open drain LSW3 based on voltage detection results.
VSYS pin and PGOOD pin output Hi-Z when VDD2 voltage is from VSS to AP4470 minimum operating
voltage(1.2V).

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11.3. Startup to DC/DC operation
Figure 11.3.1 shows a typical circuit design. The description of AP4470 functions on this document is
based on this circuit.
The AP4470 DC/DC converting function is shown in Figure 11.3.2. The DC/DC converting sequence is
shown in Figure 11.3.3 and Figure 11.3 4.
VSYS2 which pull up STUP_FLG is external system power supply. Following Chapter 11.5 describes
detail.
Figure 11.3.1 Typical circuit design
Figure 11.3.2 DC/DC converting function
→ VSYS out
Time
VSTRG
VDETH2
(Start supplying voltage)
Supplyingpower
→ VSYS out
VDETH1
VDETL1
Hysteresis comparator 2：
System power supply control
VDETL2
(Stop supplying voltage)
Hysteresis comparator 1：
・Storage device protection
・VSYS System protection ISTRG > (IOUT + IVDD1+ IVDD2)
ISTRG < (IOUT + IVDD1+ IVDD2)
Voltage

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Figure 11.3.3 DC/DC converting sequence 1 (ISTRG < (IOUT + IVDD1 + IVDD2))
VIN (V)
0
0.5
1.0
0
1.0
2.0
0
2.6(VDETL2)
0
VSYS2
VBOOST(V)
VSTRG(V)
STUP_FLG(V)
OFF
(Hi-Z)
ON
(=VSS)
3.3(VDETH2)
3.45(VDETL1)
3.55(VDETH1)
0
2.6(VDETL2) VSYS(V)
3.3(VDETH2)
3.45(VDETL1)
3.55(VDETH1)
OFF
(Hi-Z)
0
2.6(VDETL2) PDH_STUP(V)
3.3(VDETH2)
3.45(VDETL1)
3.55(VDETH1)
Pull-down
(10MΩ)
0
2.6(VDETL2) PGOOD(V)
3.3(VDETH2)
3.45(VDETL1)
3.55(VDETH1)
LSW3
ON
(=VSS)
VSYS
LSW3
OFF
(Hi-Z)
Time
OFF
(Hi-Z)
OFF
(Hi-Z)
LSW3
OFF
(Hi-Z)

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Figure 11.3 4 DC/DC converting sequence 2 (ISTRG > (IOUT + IVDD1 + IVDD2))
VIN (V)
0
0.5
1.0
0
1.0
2.0
0
2.6(VDETL2)
0
VSYS2
VBOOST(V)
VSTRG(V)
STUP_FLG(V)
OFF
(Hi-Z)
ON
(=VSS)
3.3(VDETH2)
3.45(VDETL1)
3.55(VDETH1)
0
2.6(VDETL2) VSYS(V)
3.3(VDETH2)
3.45(VDETL1)
3.55(VDETH1)
OFF
(Hi-Z)
0
2.6(VDETL2) PDH_STUP(V)
3.3(VDETH2)
3.45(VDETL1)
3.55(VDETH1)
Pull-down
(10MΩ)
Pull-down
(10MΩ)
Pull-down
(10MΩ)
Pull-down
(10MΩ)
OUT1 OUT1 OUT1
0
2.6(VDETL2) PGOOD(V)
3.3(VDETH2)
3.45(VDETL1)
3.55(VDETH1)
LSW3
ON
(=VSS)
VSYS
LSW3
OFF
(Hi-Z)
Power
Down
OFF
(Hi-Z)
OFF
(Hi-Z)
OFF
(Hi-Z)
Time
Power
Down Power Down

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11.3.1 Cold Startup
The AP4470 starts DC/DC converting when more than 0.20V(typical) is applied to VIN pin (VIN ≧ VIN,
STUP). The input voltage to VIN pin is upconverted to VBOOST pin. The LSW is switched by the
VBOOST voltage powered driver circuit and stored energy to an external inductor is charged to CSTRG
by this switching operation.
For rectifier circuit for this startup, adding an external diode (D) or using the on-chip diode (HSW)
should be used, either will work.
11.3.2 DC/DC
11.3.2.1 When (ISTRG > (IOUT + IVDD1 + IVDD2))
When CSTRG has no initial charge, VSTRG voltage is increasing by DC/DC converting operation while
energy is stored to CSTRG.
When VSTRG voltage reaches to VDETH2, the COMP2 turns on the High Side Switch (HSW2) and then,
VSTRG is supplied to VSYS.
In case in which the OUT1 pin is connected to PDH_STUP pin, the startup will be powered down and
DC/DC converting will be stopped when VSTRG voltage reaches to VDETH1. In this case, a system that is
connected to VSYS will be operated from VDETH2 to VDETH1
To connect OUT1 pin and PDH_STUP pin avoids stopping accidentally startup operation because
PDH_STUP state is defined to “Low” by the on-chip pull down resistor even if the COMP1 output is
unknown (VDD1<1.2V).
When DC/DC operation is stopped, VSTRG voltage will be decreased because of leakage current of a
storage device, etc.
In case in which the OUT1 pin is connected to PDH_STUP pin, the startup is returned from power down
and the AP4470 starts DC/DC operation again when the COMP1 detects VSTRG voltage goes down to
VDETL1.
11.3.2.2 When (ISTRG < (IOUT + IVDD1 + IVDD2))
If VSYS is supplied under the flowing condition, VSTRG voltage will be decreased even though the AP4470
is on DC/DC converting operation.
Current supply from VSYS pin (IOUT) + COMP1 consumption (IVDD1) + COMP2 consumption (IVDD2) are
larger than ISTRG which is charge current to CSTRG via a diode
AND
VSTRG≧VDETH2
When the COMP2 detects VSTRG voltage goes down to VDETL2, power supply from VSYS is stopped
continuing DC/DC operation. Power supply from VSYS to a system starts again when VSTRG voltage
become larger than VDETH2 (VSTRG≧VDETH2).

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11.4. Power Good
System Reset Application Circuit
The output of Power Good (PGOOD) becomes “Low” to “Hi-Z” when the AP4470 starts supplying power
from VSYS pin. Connecting a resistor R1 and a capacitor C1, the Power Good function can be used to
release system reset using delay that is defined by R1 and C1 time constant.
Figure 11.4.1 shows an example system reset circuit.
Figure 11.4.1 Power Good function application example

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11.5. Startup FLG
Zero Standby Current Trigger Switch Application Circuit.
The STUP_FLG output DC/DC converting status of the AP4470. This can be used trigger switch
function with zero standby current if a system has proprietary power supply (VSYS2). Figure 11.5.1
shows a typical circuit for zero standby trigger switch. Using only this switch function doesn’t require an
external inductor and a storage device.
The AP4470’s startup does upconverting VIN input voltage to VBOOST pin. When on-chip driver circuit
is powered on by VBOOST voltage, an open drain output goes from “Hi-Z” to “Low”.
The example Figure 11.5.1, shows STUP_FLG pin transition from “High (VSYS2)” to “Low (VSS)”.
This function can be used to recover from sleep mode using this signal as a trigger. STUP_FLG signal
is cleared by RSTH_FLG pin “High” input.
Figure 11.5.1 Zero Standby Current Trigger Switch

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12. Test Circuits
12.1. External Circuit Example
Figure 12.1.1 is for reference data measurement. The bill of materials is shown in Table 12.2.1.
Figure 12.1.1 External circuits for test
Notes:
*17. It is recommended to connect the exposed pad (EPAD), that is located on the bottom of the package, to VSS.
The pad can be left floating if needed.
*18. If on-chip diode for rectifier circuit is not used, ANODE pin and CATHODE pin both should be tied to VSS
or leave them open.
*19. CSTRG capacitance value should be optimized based on system load.
*20. The inductor L1 affects DC/DC converting efficiency. The inductor value is chosen based on system load
and ranges from 2.2H to 22H for most applications. The DC resistance of the L1 inductor directly affects
DC/DC converting efficiency. Larger inductor can improve efficiency in particularly low VIN input applications.
Please consider the characteristics of inductor for system optimization.

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12.2. PCB Guidline
TOP view BOTTOM view
Figure 12.1.1 PCB layout (2layers)
Table 12.2.1 Bill of Materials List
Name
Value
Parts
Description
L1
22H
LBR2518T220K
Inductor for Step-up DC/DC
R1
DNP
Pull-up resistor for STUP_FLG
R2
DNP
Pull-up resistor for PGOOD
C1
10H
Capacitor for the VIN source
Suppress the fluctuation of the VIN
C2
100pF
Capacitor for VBOOST
C3
DNP
Capacitor for CSTRG
C4
0.1F/ 5.5V
FG0H104ZF
Capacitor for CSTRG
C5
DNP
Capacitor for PGOOD
D1
DNP
Diode for External rectifier
IC1
AP4470
*DNP : Do Not Populate (Even if it is not implemented, there is no problem with basic operation)
Notes:
*21. On-chip diode (HSW) for rectifier is used in this circuit. If an external diode for rectifier circuit is used,
ANODE pin and CATHODE pin both should leave open and mount a component on D1.
*22. Using low leakage current capacitor is strongly recommended for C3 and C4.
*23. For reference data measurement, NC pin (#2) =VSS.

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13. Typical Characteristics
Unless otherwise noted, specifications apply for conditions of
⚫Test Circuit：PCB/BOM specified on Chapter 12.
⚫On-chip diode (HSW) is used.
⚫Ta=25ºC
13.1. Cold Startup
Figure 13.1.1 Minimum input startup voltage vs Temperature
13.2. Switching Frequency
Figure 13.2.1 Switching Frequency vs VIN

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13.3. Low side ON pulse width
Low Side Switching Time is constant regardless of VIN and temperature.
Figure 13.3.1 Low side ON pulse width vs VIN
13.4. COMP1
Figure 13.4.1 temperature characteristics of VDETH1 and VDETL1 normalized at 25ºC

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13.5. COMP2
Figure 13.5.1 temperature characteristics of VDETH2 and VDETL2 normalized at 25ºC
13.6. Current consumption
ISW and ISTRG are data at VSTRG=1.0V
Figure 13.6.1 ICORE vs VIN