Astronics OMNIBUS II NI PXIe User manual

Astronics Ballard Technology/National Instruments
LV-222-511-442 Manual
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Astronics Ballard Technology
www.astronics.com
MA223-20180201 Rev. C.1
OMNIBUS II NI PXIe
USER MANUAL
Interface Card
To Avionics Databuses
February 1, 2018
Rev. C.1
Copyright 2018
by
Ballard Technology, Inc.

COPYRIGHT NOTICE
Copyright  2018 by Ballard Technology, Inc.—hereafter referred to as Ballard. Ballard’s
permission to copy and distribute this manual is for the purchaser's private use only and is
conditioned upon the purchaser's use and application with the OmniBus II hardware that was
shipped with this manual. This notice allows no commercial resale or outside distribution rights.
This material remains the property of Ballard. All other rights reserved by Ballard.
SAFETY WARNING
Ballard products are not intended, warranted, or certified for any particular use or application or for
use in any application where failure of the products could lead directly to death, personal injury, or
damage to property. Customers, licensees, and/or users are responsible for establishing and
assuring suitability and proper use of Ballard products for their particular use or application.
INTERFERENCE
This equipment generates, uses, and can radiate radio frequency energy and if not installed and
used in accordance with the user manual, may cause interference to radio communications.
Operation of this equipment in a residential area is likely to cause interference in which case the
user at their own expense will be responsible for taking whatever measures may be required to
correct the interference.
TRADEMARKS
PCIe is a registered trademark of PCI-SIG. PXI is a trademark of PXI Systems Alliance.
CompactPCI is a registered trademark of the PCI Industrial Computation Manufacturers Group.
Molex LFH is a trademark of Molex Inc. Windows is a registered trademark of Microsoft
Corporation. Ballard Technology, OmniBus, BTIDriver and CoPilot are registered trademarks of
Ballard Technology, Inc. All other product names or trademarks are property of their respective
owners.

PRODUCT CERTIFICATION
RESPONSIBLE PARTY
Astronics Ballard Technology, Inc.
11400 Airport Road, Suite 201
Everett, WA 98204, USA
Web: www.astronics.com
PRODUCTS
OmniBus II PXIe versions LV-222-xxx-xxx (NI P/N 784xxx-xx) (where x is any numeric character
or blank).
FCC
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two
conditions:
1) This device may not cause harmful interference, and
2) This device must accept any interference received, including interference that may cause
undesired operation.
CE
This device complies with the European Union Directives and standards for electromagnetic
compatibility (EMC) and product safety.
RoHS
This device complies with the European Union Restriction of Hazardous Substances directive.

OmniBus II NI PXIe User Manual i
TABLE OF CONTENTS
1. INTRODUCTION .........................................................................................1-1
1.1 OmniBus II Overview ........................................................................................1-1
1.2 OmniBus II Configurations................................................................................ 1-3
1.3 Avionics Databus Protocols...............................................................................1-4
1.4 Other Documentation......................................................................................... 1-5
1.5 Support and Service ...........................................................................................1-5
1.6 Updates...............................................................................................................1-5
1.7 Mean Time Between Failure..............................................................................1-5
2. INSTALLATION........................................................................................... 2-1
2.1 Step 1: Insert the Card into the System .............................................................. 2-1
2.2 Step 2: Install the Driver Software.....................................................................2-2
2.3 Step 3: Set the Card Number and Test the Installation....................................... 2-2
2.4 Step 4: Connect to Databus(s) I/O......................................................................2-3
3. OPERATION................................................................................................3-1
3.1 CoPilot................................................................................................................ 3-1
3.2 User-Developed Software ..................................................................................3-2
4. OMNIBUS II FEATURES ............................................................................ 4-1
4.1 PCI Express Bus.................................................................................................4-1
4.1.1 PXIe Form Factor................................................................................ 4-1
4.2 Built-in Test ....................................................................................................... 4-1
4.2.1 Power-on Built-in Test (PBIT)............................................................. 4-1
4.2.2 Initiated Built-in Test (IBIT) ............................................................... 4-1
4.2.3 Continuous Built-in Test (CBIT).......................................................... 4-2
4.3 System Time Synchronization............................................................................4-2
4.3.1 Core Timer.......................................................................................... 4-3
4.3.2 IRIG.................................................................................................... 4-5
4.3.3 PPS..................................................................................................... 4-6
4.3.4 10MHz................................................................................................ 4-7
4.4 Core Discretes....................................................................................................4-7
4.5 1553 Avionics Discretes.....................................................................................4-9
4.5.1 Shunt Inputs........................................................................................ 4-9
4.5.2 Shunt Input Considerations.................................................................4-10
4.5.3 Shunt Outputs.....................................................................................4-10
4.5.4 Shunt Output Considerations ..............................................................4-10
4.5.5 Shunt Discrete Input/Output Usage.....................................................4-12
5. OMNIBUS II PXIE SPECIFIC FEATURES................................................. 5-1
5.1 Clock Switch (CLK SEL)...................................................................................5-1

TABLE OF CONTENTS
ii OmniBus II NI PXIe User Manual
5.2 PXIe Trigger Access...........................................................................................5-1
5.3 Protocol Sync and Trigger Support.....................................................................5-3
5.4 PXIe Status .........................................................................................................5-4
5.5 Chassis Slot Glyph..............................................................................................5-5
6. MODULE CONFIGURATIONS ...................................................................6-1
6.1 OmniBus II PXIe Boards....................................................................................6-1
6.2 MIL-STD-1553 Modules....................................................................................6-1
6.2.1 Software-Selectable Bus Termination .................................................. 6-2
6.2.2 Configurable RT Response Time ......................................................... 6-2
6.2.3 Variable Transmit Amplitude............................................................... 6-2
6.2.4 Zero-Crossing Distortion..................................................................... 6-3
6.3 ARINC 429 Modules..........................................................................................6-4
6.3.1 Parametric Waveform.......................................................................... 6-4
6.3.2 Configurable Frequency....................................................................... 6-5
6.3.3 Output State ........................................................................................ 6-5
6.4 Part Number Cross Reference.............................................................................6-6
7. CONNECTOR PINOUTS.............................................................................7-1
7.1 Interface Connector.............................................................................................7-1
7.2 General Pinout ....................................................................................................7-2
7.3 Module-Specific Wiring .....................................................................................7-3
7.3.1 MIL-STD-1553 ................................................................................... 7-3
7.3.2 ARINC 429 ......................................................................................... 7-4
7.4 Standard Cables ..................................................................................................7-5
7.4.1 PN 16036 Cable Assembly: LFH to Two 25-pin D-subs....................... 7-5
7.4.2 MIL-STD-1553 Cable Assemblies ....................................................... 7-6
APPENDIX A: COUPLING AND TERMINATION......................................... A-1
A.1 Bus Termination ................................................................................................A-1
A.2 Transformer versus Direct Coupling..................................................................A-1
APPENDIX B: SPECIFICATIONS................................................................. B-1
B.1 General...............................................................................................................B-1
B.2 Interfaces (Model Dependent) ...........................................................................B-1
B.3 Environmental/Physical.....................................................................................B-3
APPENDIX C: ERRATA SHEET................................................................... C-1
APPENDIX D: REVISION HISTORY............................................................. D-1

OmniBus II NI PXIe User Manual iii
LIST OF FIGURES
Figure 1.1—OmniBus II PXIe Card.........................................................................1-1
Figure 1.2—The Two-Core Architecture of OmniBus II PXIe Card .......................1-2
Figure 2.1—PXIe Compatible Chassis Glyphs ........................................................2-1
Figure 3.1—Sample CoPilot Screen.........................................................................3-1
Figure 4.1—Built-in Test and System Monitor Architecture ...................................4-2
Figure 4.2—OmniBus II Discrete Shunt Input Circuit.............................................4-9
Figure 4.3—OmniBus II Discrete Shunt Output Circuit ........................................4-10
Figure 5.1—PXIe Onboard Clock Switch................................................................5-1
Figure 5.2—PXIe Chassis Slot Glyphs.....................................................................5-5
Figure A.1—Transformer Coupling to a Dual-Redundant Databus........................A-2
Figure A.2—Direct Connection to a Dual-Redundant Databus...............................A-3
Figure B.1—Dimensions of OmniBus II PXIe Card............................................... B-3

TABLE OF CONTENTS
iv OmniBus II NI PXIe User Manual
LIST OF TABLES
Table 4.1—I/O Combinations for System Synchronization .....................................4-3
Table 4.2— Pinout Supported by BTICard_IRIG ....................................................4-3
Table 4.3—Input and Output IRIG Formats.............................................................4-5
Table 4.4—Electrical Characteristics of the AM IRIG Signals................................4-5
Table 4.5—Electrical Characteristics of the PCM IRIG Signals..............................4-6
Table 4.6—IRIG Pinout............................................................................................4-6
Table 4.7—Electrical Characteristics of the PPS Signal...........................................4-6
Table 4.8—PPS Pinout .............................................................................................4-7
Table 4.9—10 MHz Input/Output Characteristics....................................................4-7
Table 4.10—10 MHz Pinout.....................................................................................4-7
Table 4.11—Hardware Versus Software Designation of Core Discretes.................4-8
Table 4.12—1553 Discrete I/O Designations.........................................................4-12
Table 5.1—PXIe Trigger Signals..............................................................................5-2
Table 5.2—PXIe Trigger to Protocol Trigger Mapping ...........................................5-3
Table 5.3—PXIe Trigger to Protocol Sync Mapping ...............................................5-3
Table 5.4—Transitional Protocol Trigger Parameters..............................................5-4
Table 5.5—PXIe Status Parameters..........................................................................5-4
Table 6.1—OmniBus II PXIe Host Part Numbering ................................................6-1
Table 6.2—MIL-STD-1553 Module Part Numbering..............................................6-1
Table 6.3—MIL-STD-1553 Level Function Definition ...........................................6-2
Table 6.4—MIL-STD-1553 ParamAmplitudeConfig Configval..............................6-3
Table 6.5—MIL-STD-1553 ParamAmplitudeConfig Output Drive.........................6-3
Table 6.6—ARINC 429 Module New Applications Part Numbering ......................6-4
Table 6.7—ARINC 429 Parametric Waveform Characteristics...............................6-5
Table 7.1—General Pin Designations.......................................................................7-2
Table 7.2—Pinouts for MIL-STD-1553 Modules.....................................................7-3
Table 7.3—Pinouts for ARINC 429 modules...........................................................7-4
Table 7.4—Wiring Chart for 16036 Cable Assembly (See next page for “*” note).7-5
Table 7.5—MIL-STD-1553 Cable Assembly Configurations..................................7-6
Table 7.6—Twinax Wiring on MIL-STD-1553 Cable Assemblies..........................7-6
Table 7.7—D-sub Connector Pinout for Cable Assemblies 16037 and 16039.........7-7

OmniBus II NI PXIe User Manual 1-1
1. INTRODUCTION
This manual is the user guide for PXI™ Express (PXIe) models of Astronics
Ballard Technology®’s (Ballard) OmniBus®II family of products. Throughout this
manual any reference to the PXIe card applies to the OmniBus II PXIe card, and
references to OmniBus and OmniBus II apply generically to all the products in the
designated family. This guide gives the background for the OmniBus II PXIe card,
discusses special features, describes the installation process, and references
programming alternatives.
1.1 OmniBus II Overview
OmniBus II (OB2) is a family of products that enable computer systems to
communicate with avionics databuses for the purpose of testing, simulation, and/or
operation. Each OB2 unit can support more than one protocol and a large number
of channels. They are available as an interface card for popular computer standards
(PCIe, cPCIe/PXIe, etc.) and as a stand-alone bridge to other communications
protocols (USB, Ethernet, etc.). All common avionics databus protocols are
supported, including MIL-STD-1553, ARINC 429, and Discrete I/O. Other
protocols (such as ARINC 575, ARINC 573, ARINC 453, etc.) are also supported.
Upon request, custom protocols can be implemented.
Figure 1.1—OmniBus II PXIe Card
The high-density modular design of the OB2 family provides flexibility that
enables the user to select from many protocol, platform, and channel count com-
binations. Each OB2 product can have at least two modules, and each module has