The 0S uses 192 TV llnes for its display and devotes the remalnlng
24 ltnes to overscanr It uses the standard dlsplay irldth of 160 color
clocks, The hard\rare will allo\r displays of any length, but it ts recon-
nended lhat the standards be followed. The exception night be a border
or other lnfornatlon whlch is nerely decota!1ve and not esse[tla1 to use
of the prograno.
.q,q_lleggjglqE: Since nany of the hard\,rare reglsters are write-only
and cannot be read the 0S has a mnber of "shadow registers'i in RAM.
Every TV frarne durlng vertical blank the OS takes lhe values ln sone of
its shadowregisters, and wriles thero ou! to the correspondlng hardware
register. The 0S does attracr color shlfting on all of rhe color registers
ii ATRACT
(on 0S reglsrer) is negatlve. This is to prevent da&age Eo rhe
TV screen phosphors h'trlch can occur 1f the brlghtness 1s turned up too hlgh
and the santehlgh-luninance dlsplay is lef! on for a long tlne. The OS also
reads lhe Joysticks and other conrrollets during vertlcal blank and stores
lhe resulls 1n shadow reglsrers, so rhat user plograns do not have to tnclude
code to unpack the data. Ttere are a few interrupt-related reglsrers $hlch
lhe 0S changes or reads during inlerrupt processing. Prograr0s
usually access
the OS shadow registers instead of accessing the hard\tare directly. Ho\rever,
the OS shadoirlng can be disabled by changtng the vertical blank and lnterrup!
veclors (see OSmarlual).
l{!:Ig: In addirion to a Vertical Blank Interrupt, which allons rhe
I'Ilctoprocessor to s)'nchronlze to the vertical TV display, this systed also
provides a Walt for Horizontal Sync (WSYNC)
cornnand rhat al1ows Ehe
lolcroprocessor to synchronlze ilself to lhe TV horlzontal line rate. Thts
sync takes effect \rhen the processor r.rrites to an I/O location ca11ed
WSYNC,\rhenever it deslres horizontal synchronizat lon. Wriling to thls
address sets a larch which pul1s to zero a pln on the lllctoprocessor
called REAIY. IdhenREADY
goes to zeto the Elcroprocessor stops and \raits.
The lalch is autonatlcally reset (returning REAIY true) at the beglnnlng
of the next horizontal blank interval, releasing the nicroprocessor to
resunoe
progran execution.
Obiect DMA
(Direct Menorv Access): The primary functlon of the Antlc
chip ls to fetch data fron roenoty (independent of the nlcroprocessor) for
display on the TV screen. It does thls lrlth a lechnlqle called "Dlrect
Meoory Access" or Dl4A. It reqrests lhe use of the inenory address and dala
bus by sending a stgnal called HALTto lhe microprocessor, causlng the
processor to becoEe "TRI-STATE" (open circuit) all durlng the next cornputer
cycle. The ANTIC chlp lhen takes over rhe address blrs and reads any data
it r,rishes fron nenory. Another nan€ fo! Lhis rype of DMA
1s "cyc1e stealing".
Once lnitlated, this DMAis conpletely and autonatically conlrolled by lhe
Antlc chip Fithout need for futher microprocessor lnlervention.
There are l\ro types of Dl4A: Playfleld and Player-Missile (see Figure
1I.2). The playfield Dl4Acontrol clrcult on the Antlc chip resernbles a
snall durnbdrlcroprocessor. By halting the main nicroprocessor 1t can
fetch its ol'n instructions fron uernory (lhe dtsplay list) addressed by 1ts
program counter(d1splay llst poln!e.). Each instructlon defines the type
(alpha character or nemory nap), and the resolurlon (slze of bits on the
screen), and the Iolation of the data ln menoryL'hich is to be dtsplayed
group or rlnes.
II.2
