Intel Xeon Phi User manual

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Intel® Xeon Phi™ Coprocessor
DEVELOPER’S QUICK START GUIDE
Version 1.7

Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE
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Contents
Introduction........................................................................................................................................................................................................4
Goals ............................................................................................................................................................................................................................. 4
This document does:...................................................................................................................................................................................... 4
This document does not:............................................................................................................................................................................. 4
Terminology.............................................................................................................................................................................................................. 4
System Configuration ....................................................................................................................................................................................5
Intel® Xeon Phi™ Software ................................................................................................................................................................................ 5
Intel® Many Integrated Core Architecture Overview........................................................................................................................7
Administrative Tasks......................................................................................................................................................................................8
Preparing Your System for First Use.......................................................................................................................................................... 8
Steps to install the driver and start the card.................................................................................................................................. 8
Steps to install the Software Development tools ........................................................................................................................ 9
Updating an Existing System ....................................................................................................................................................................... 10
Updating a system that already has an Intel® Xeon Phi™ Coprocessor ........................................................................ 10
Regaining Access to the Intel® Xeon Phi™ Coprocessor after Reboot................................................................................... 11
Restarting the Intel® Xeon Phi™ Coprocessor If It Hangs.............................................................................................................. 11
Monitoring the Intel® Xeon Phi™ Coprocessor ..................................................................................................................................... 12
Running an Intel® Xeon Phi™ Coprocessor program from the host system ........................................................................ 12
Working directly with the uOS Environment Intel® Xeon Phi™ Coprocessor ...................................................................... 13
Useful Administrative Tools ......................................................................................................................................................................... 13
Getting Started/Developing Intel® Xeon Phi™ Software .............................................................................................................. 13
Available Software Development Tools / Environments.............................................................................................................. 14
Development Environment: Available Compilers and Libraries ......................................................................................... 14
Development Environment: Available Tools................................................................................................................................. 14
General Development Information............................................................................................................................................................ 14
Development Environment Setup....................................................................................................................................................... 14
Documentation and Sample Code....................................................................................................................................................... 15
Build-Related Information ....................................................................................................................................................................... 16
Compiler Switches and Makefiles........................................................................................................................................................ 16
Debugging During Runtime..................................................................................................................................................................... 17
Where to Get More Help........................................................................................................................................................................... 17
Using the Offload Compiler –Explicit Memory Copy Model......................................................................................................... 17
Reduction .......................................................................................................................................................................................................... 18
Creating the Offload Version................................................................................................................................................................. 18

Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE
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Asynchronous Offload and Data Transfer ..................................................................................................................................... 19
Using the Offload Compiler –Implicit Memory Copy Model ......................................................................................................... 19
Native Compilation............................................................................................................................................................................................. 21
Parallel Programming Options on the Intel® Xeon Phi™ Coprocessor..................................................................................... 22
Parallel Programming on the Intel® Xeon Phi™ Coprocessor: OpenMP* ........................................................................ 22
Parallel Programming on the Intel® Xeon Phi™ Coprocessor: OpenMP* + Intel® Cilk™ Plus Extended Array
Notation ............................................................................................................................................................................................................. 23
Parallel Programming on the Intel® Xeon Phi™ Coprocessor: Intel® Cilk™ Plus........................................................... 24
Parallel Programming on Intel® Xeon Phi™ Coprocessor: Intel® Threading Building Blocks (Intel® TBB)..... 25
Using Intel®MKL................................................................................................................................................................................................... 26
SGEMM Sample............................................................................................................................................................................................... 27
Intel® MKL Automatic Offload Model........................................................................................................................................................ 28
Debugging on the Intel® Xeon Phi™ Coprocessor............................................................................................................................. 29
Performance Analysis on the Intel® Xeon Phi™ Coprocessor ..................................................................................................... 29
About the Authors........................................................................................................................................................................................ 30
Notices............................................................................................................................................................................................................... 31
Performance Notice..................................................................................................................................................................................... 32
Optimization Notice ..................................................................................................................................................................................... 32

Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE
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Introduction
This document will help you get started writing code and running applications on a system (host) that includes
the Intel® Xeon Phi™ Coprocessor based on the Intel® Many Integrated Core Architecture (Intel® MIC
Architecture). It describes the available tools and includes simple examples to show how to get C/C++ and
Fortran-based programs up and running. For now, the developer will have to cut/paste the examples provided
in the document to their system.
This document is available at http://software.intel.com/mic-developer under the “Overview”tab.
Goals
This document does:
1. Walk you through the Intel® Manycore Platform Software Stack (Intel® MPSS) installation.
2. Introduce the build environment for software enabled to run on Intel® Xeon Phi™ Coprocessor.
3. Give an example of how to write code for Intel® Xeon Phi™ Coprocessor and build using Intel®
Composer XE 2013 SP1.
4. Demonstrate the use of Intel libraries like the Intel® Math Kernel Library (Intel® MKL).
5. Point you to information on how to debug and profile programs running on an Intel® Xeon Phi™
Coprocessor.
6. Share some best known methods (BKMs) developed by users at Intel.
This document does not:
1. Cover each tool in detail. Please refer to the user guides for the individual tools.
2. Provide in-depth training.
Terminology
Host –The Intel® Xeon® platform containing the Intel® Xeon Phi™ Coprocessor installed in a PCIe* slot. The
operating systems (OS) supported on the host are Red Hat* Enterprise Linux* 6.0, Red Hat* Enterprise Linux*
6.1, Red Hat* Enterprise Linux* 6.2, Red Hat* Enterprise Linux* 6.3, Red Hat* Enterprise Linux* 6.4, Red Hat*
Enterprise Linux* 6.5, SUSE* Linux* Enterprise Server SLES 11 SP2 and SUSE* Linux* Enterprise Server SLES
11 SP3. The user will have to install the OS.
Target –The Intel® Xeon Phi™ Coprocessor and corresponding runtime environment installed inside the
coprocessor.
uOS –Micro Operating System –the Linux*-based operating system and tools running on the Intel® Xeon Phi™
Coprocessor.
ISA –Instruction Set Architecture –part of the computer architecture related to programming, including the
native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception
handling, and external I/O (Input/Output).
1
VPU –Vector Processing Unit- the portion of a CPU responsible for the execution of SIMD (single instruction,
multiple data) instructions.
1
Intel acronyms dictionary, 8/6/2009, http://library.intel.com/Dictionary/Details.aspx?id=5600

Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE
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NAcc –Native Acceleration –a mode or form of Intel® MKL in which the data being processed and the MKL
function processing the data reside on the Intel® Xeon Phi™ Coprocessor.
Offload Compilers –The Intel® C/C++ Compiler and Intel® Fortran Compiler compilers, which can generate
binaries for both the host system and the Intel® Xeon Phi™ Coprocessor. The offload compilers can generate
binaries that will run only on the host, only on the Intel® Xeon Phi™ Coprocessor, or paired binaries that run on
both the host and the Intel® Xeon Phi™ Coprocessor and communicate with each other.
Intel® MPSS –Intel® Manycore Platform Software Stack–the user- and system-level software that allows
programs to run on and communicate with the Intel® Xeon Phi™ Coprocessor.
SCI- Symmetric Communications Interface –the mechanism for inter-node communication within a single
platform, where an node is a Intel® Xeon Phi™ Coprocessor or an Intel Xeon processor-based host processor
complex. In particular, SCI abstracts the details of communicating over the PCIe bus (and controlling related
Intel® Xeon Phi™ Coprocessor hardware) while providing an API that is symmetric between all types of nodes
System Configuration
The configuration assumed in this document is an Intel workstation containing two Intel® Xeon® processors,
one or two Intel® Xeon Phi™ Coprocessors attached to a PCIe* x16 bus, and a GPU for graphics display.
Intel® Xeon Phi™ Software
Figure 1: Software Stack
The Intel® Xeon Phi™Coprocessor software stack consists of layered software architecture as noted below
and depicted in Figure 1.
Driver Stack:
The Linux software for the Intel® Xeon Phi™ Coprocessor consists of a number of components:

Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE
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Device Driver: At the bottom of the software stack in kernel space is the Intel® Xeon Phi™ Coprocessor
device driver. The device driver is responsible for managing device initialization and communication
between the host and target devices.
Libraries: The libraries live on top of the device driver in user and system space. The libraries provide basic
card management capabilities such as enumeration of cards in a system, buffer management, and host-to-
card communication. The libraries also provide higher-level functionality such as loading and unloading
executables onto the Intel® Xeon Phi™ Coprocessor, invoking functions from the executables on the card,
and providing a two-way notification mechanism between host and card. The libraries are responsible for
buffer management and communication over the PCIe* bus.
Tools: Various tools that help maintain the software stack. Examples include /usr/bin/micinfo for querying
system information, /usr/bin/micflash for updating the card’s flash, /usr/sbin/micctrl to help administrators
configure the card, etc.
Card OS (uOS): The Linux-based operating system running on the Intel® Xeon Phi™ Coprocessor.
NOTE: Source for relatively recent versions of the uOS, the device driver, and the low-level SCI library
interface can be found at http://software.intel.com/mic-developer .

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Intel® Many Integrated Core Architecture Overview
The Intel® Xeon Phi™ Coprocessor has up to 61 in-order Intel® MIC Architecture processor cores running at
1GHz (up to 1.3GHz). The Intel® MIC Architecture is based on the x86 ISA, extended with 64-bit addressing and
new 512-bit wide SIMD vector instructions and registers. Each core supports 4 hardware threads. In addition
to the cores, there are multiple on-die memory controllers and other components.
Figure 2: Architecture overview of an Intel® MIC Architecture core
Each core includes a newly-designed Vector Processing Unit (VPU). Each vector unit contains 32 512-bit
vector registers. To support the new vector processing model, a new 512-bit SIMD ISA was introduced.
The VPU is a key feature of the Intel® MIC Architecture-based cores. Fully utilizing the vector unit is critical for
best Intel® Xeon Phi™ Coprocessor performance. It is important to note that Intel® MIC Architecture cores do
not support other SIMD ISAs (such as MMX™, Intel® SSE, or Intel® AVX).
Each core has a 32KB L1 data cache, a 32KB L1 instruction cache, and a 512KB L2 cache. The L2 caches of all
cores are interconnected with each other and the memory controllers via a bidirectional ring bus, effectively
creating a shared last-level cache of up to 32MB. The design of each core includes a short in-order pipeline.
There is no latency in executing scalar operations and low latency in executing vector operations. Due to the
short in–order pipeline, the overhead for branch misprediction is low.
For more details on the machine architecture, please refer to the Intel® Xeon Phi™ Coprocessor Software
Developer’s Guide posted at http://software.intel.com/mic-developer under “TOOLS & DOWNLOADS” tab.

Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE
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Administrative Tasks
If you purchased the Intel® Xeon Phi™ Coprocessor from an equipment manufacturer, please go to the Intel®
Developer Zone page http://software.intel.com/mic-developer and click on tab “TOOLS & DOWNLOADS”, then
select “Intel® Manycore Architecture Platform Software Stack (Intel® MPSS)” on this page. This brings you to a
page where you can download the latest hardware drivers and release notes for the platform.
Preparing Your System for First Use
Steps to install the driver and start the card
1. From Intel® Developer Zone page http://software.intel.com/mic-developer, click on tab “TOOLS &
DOWNLOADS”, then select “Intel® Manycore Platform Software Stack (Intel® MPSS)”on this page.
Navigate to the latest version of MPSS release for Linux and download “Readme file for Linux
(English)”(readme.txt). Also download the release notes (releaseNotes-linux.txt) and the User’s
Guide for MPSS.
2. You may install your system with Red Hat* Enterprise Linux 64-bit 6.0 kernel 2.6.32-71, Red Hat
Enterprise Linux 64-bit 6.1 kernel 2.6.32-131, Red Hat Enterprise Linux 6.2 64-bit kernel 2.6.32-220,
Red Hat Enterprise Linux 6.3 64-bit kernel 2.6.32-279, Red Hat Enterprise Linux 6.4 64-bit kernel
2.6.32-358, Red Hat Enterprise Linux 6.5 64-bit kernel 2.6.32-431, SUSE Linux Enterprise Server
SLES 11 SP2 kernel 3.0.13-0.27-default or SUSE Linux Enterprise Server SLES 11 SP3 kernel 3.0.76-
0.11-default (Section 2.1 in readme.txt ). Be sure to install ssh, which is used to log in to the card’s
uOS.
WARNING: On installing Red Hat, it may automatically update you to a new version of the Linux kernel.
If this happens, you will not be able to use the pre-built host driver, but will need to rebuild it manually
for the new kernel version. Please see section 2.1 in readme.txt for instructions on building an Intel®
MPSS host driver for a specific Linux kernel.
3. Log in as root.
4. Download the release driver appropriated for your operating system in step 1 (<mpss-version>-rhel-
6.0.tgz, <mpss-version>-rhel-6.1.tgz, <mpss-version>-rhel-6.2.tgz, <mpss-version>-rhel-6.3.tgz,
<mpss-version>-rhel-6.4.tgz, <mpss-version>-rhel-6.5.tgz, <mpss-version>-suse-11.2.tgz or <mpss-
version>-suse-11.3.tgz) where <mpss-version> is mpss-3.2 at the time when this document was
updated
5. Install the host driver RPMs as detailed in section 2.2 of readme.txt. Don’t skip the creation of
configuration files for your coprocessor.
6. Update the flash on your coprocessor(s) as detailed in section 2.4 of readme.txt.
7. Reboot the system.
8. Start the Intel® Xeon Phi™ Coprocessor (while you can set up the card to start with the host system, it
will not do so by default), and then run “micinfo”to verify that it is set up properly:
sudo service mpss start
sudo micctrl –w
sudo /usr/bin/micinfo

Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE
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Make sure that the Driver Version, MPSS Version and Flash Version are verified according to the
following table:
MPSS stack installed
Driver Version
MPSS Version
Flash Version
mpss-3.2
3.2-xx
3.2
2.1.03.0386
mpss-3.1
3.1-xx
3.1
2.1.03.0386
mpss_gold_update_3-2.1.6720-13
6720-13
2.1.6720-13
2.1.02.0386
KNC_gold_update_2-2.1.5889-16
5889-16
2.1.5889-16
2.1.05.0385
KNC_gold_update_1-2.1.4982-15
4982-15
2.1.4982-15
2.1.05.0375
KNC_gold-2.1.4346-xx
4346-xx
2.1.4346-xx
2.1.01.0375
Table 1: Corresponding Driver Version, MPSS Version and Flash Version found in each MPSS release.
Steps to install the Software Development tools
You can purchase Software Development Tools at http://software.intel.com/en-us/linux-tool-suites. Select the
tool(s) that fit(s) your need (e.g., “Intel® Cluster Studio XE 2013”, “Intel® C++ Composer XE for Linux*”, “Intel®
Fortran Composer XE for Linux*”, etc.). After selecting the tool that you need and completing the purchasing
process, you will receive a serial number. Alternatively, visit http://software.intel.com/en-us/mic-developer ,
under the “Tools and Downloads” select the “Intel® Software Development Products” to find the latest list of
supported tools for the Intel® Xeon Phi™ Coprocessor.
If you acquired a serial number for Intel tools, go to the Intel® Registration Center (IRC) at
http://registrationcenter.intel.com to register and download the products. Click the button “Register Product”
will bring you to the download page of the tool(s) you purchased. The following example shows a case when a
user bought the Intel Cluster Studio XE for Linux: from http://software.intel.com/en-us/intel-cluster-studio-xe/ ,
under the tab Documentation, you can get the Install Guide, Getting Started Guide and Release Notes
documents.
1. Follow the instructions in the Install Guide to install the Intel Cluster Studio XE for Linux*. If you
bought the Intel C++ Composer XE for Linux, or the Intel Fortran Composer XE for Linux only, read the
corresponding Install Guide to install these packages, as well as separately installing Intel® VTune™
Amplifier XE 2013 for Linux*.
For first time installations, be sure to get the product license number described above that is
required to activate the product, and then provide the license number during installation.
Subsequent installations can select the “Use existing license”option.
Read the release notes of the product (icsxe2013sp1-update1-release-notes.pdf if you
bought the Intel Cluster Studio XE for Linux, or
Release_Notes_C_2013SP1_L_EN_Update2.pdf if you bought the Intel C++ Composer XE for
Linux, or Release-notes-f-2013sp1-l-en-u2.pdf if you bought the Intel Fortran Composer XE
for Linux) carefully.
Untar the product file

Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE
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otar –xvzf l_ics_2013.<update>.<package_num>.tgz, or
otar –xvf l_ccompxe_intel64_2013.<update>.<package_num>.tgz, or
otar –xvf l_fcompxe_intel64_2013.<update>.<package_num>.tgz
2. Install the software tools using the previously acquired serial number.
3. Verify that the card is working by running a sample program (located in
/opt/intel/composerxe/Samples/en_US/C++/mic_sample for C/C++ code or in
/opt/intel/composerxe/Samples/en_US/Fortran/mic_sample for Fortran code) with
“setenv H_TRACE 2”or “export H_TRACE=2”to display the dialog between the Host and Intel®
Xeon Phi™ Coprocessor (messages from the processor will be prefixed with “MIC:”). If you do see
dialog then everything is running fine and the system is ready for general use.
4. If you intend to collect performance data on this system using Intel VTune Amplifier XE 2013:
a) After MPSS gets started, it loads the data collection driver automatically. But for some reason, if
it fails to load the data collection driver, you can manually load the driver by going to
/opt/intel/vtune_amplifier_xe/bin64/k1om/ and running:
sudo sep_micboot_install.sh
b) Start (or restart) the Intel® Manycore Platform Software Stack service (this also starts the
sampling driver once the files are copied in the previous step):
sudo service mpss restart
sudo micctrl -r
sudo micctrl -w
The coprocessor has successfully restarted when micctrl –wreports “micx: online”
c) The sampling driver will now start every time the coprocessor is restarted
d) If you ever need to reinstall the sampling driver, it can be done as follows:
sudo service mpss stop
sudo sep_micboot_uninstall.sh
sudo service mpss restart
sudo micctrl –w
Updating an Existing System
Updating a system that already has an Intel® Xeon Phi™ Coprocessor
1. From Intel® Developer Zone page http://software.intel.com/mic-developer, click on the “TOOLS &
DOWNLOADS”tab, then select “Software Drivers: Intel® Manycore Platform Software Stack (Intel®

Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE
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MPSS)” on this page. Download “Readme file for the Intel® MPSS release”(readmetxt). Also
download the release notes (releaseNotes-linux.txt)
2. Uninstall the previous version of the MPSS and install the new MPSS using the instructions in
section 2.3 of readme.txt .
3. Update the flash on your card(s) as detailed in section 2.4 of readme.txt
4. Reboot the system
5. Start the Intel® Xeon Phi™ Coprocessor (while you can set up the card to start with the host
system, it will not do so by default), and then run “micinfo” to verify that it is set up properly:
sudo service mpss start
sudo micctrl -w
/usr/bin/micinfo
Make sure that the Driver Version, MPSS Version and Flash Version are verified according to table
1 in the previous section.
Regaining Access to the Intel® Xeon Phi™ Coprocessor after Reboot
The Intel® Xeon Phi™ Coprocessor will not start when the host system reboots. You will need to manually start
the Intel® Xeon Phi™ Coprocessor, and then run “micinfo” to verify that it started properly. You may need to
add /usr/sbin and /sbin to your path to do this successfully as a non-root user via sudo:
sudo service mpss start
sudo micctrl -w
/usr/bin/micinfo
Note: It is possible to make the coprocessor uOS automatically start on reboot and preload desired files. See
section 19.12 of the MPSS User’s Guide for details
Restarting the Intel® Xeon Phi™ Coprocessor If It Hangs
If a process running on the Intel® Xeon Phi™ Coprocessor hangs, but the coprocessor is otherwise responsive
via ssh, log onto the coprocessor and kill the process like any other Linux process.
When a coprocessor hangs, and is inaccessible or unresponsive via ssh, there are two ways to restart it. But
first, see if you can tell what is happening:
sudo micctrl –-status <micx>

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Assuming that the Intel® MPSS service is still functioning properly, you can try to restart the coprocessor
without affecting any other attached coprocessors as follows:
sudo micctrl –-reset <micx>
sudo micctrl –-boot <micx>
sudo micctrl -w
/usr/bin/micinfo
If the Intel® MPSS service is not running properly, then you need to restart the driver and all connected
coprocessors:
sudo service mpss stop
sudo service mpss unload
sudo service mpss start
sudo micctrl -w
/usr/bin/micinfo
Monitoring the Intel® Xeon Phi™ Coprocessor
If you want to monitor the load on your coprocessor, its temperature, etc., run the System Management and
Configuration (SMC) utility. See section 8.3 of the MPSS User’s Guide for details:
Execute the monitor
/usr/bin/micsmc &
When started with no arguments, micsmc will run in GUI-mode. When invoked with arguments, it will run in
character-mode.
Running an Intel® Xeon Phi™ Coprocessor program from the host system
It is possible to copy an Intel® MIC Architecture native binary to a specified Intel® Xeon Phi™ Coprocessor and
execute it using the “micnativeloadex”utility. This utility conveniently copies library dependencies to the
coprocessor. See section 8.5 of the MPSS User’s Guide for details.

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Working directly with the uOS Environment Intel® Xeon Phi™ Coprocessor
Since the coprocessor is running Linux and is effectively a separate network node, root or non-root users can
log into it via “ssh” and issue many common Linux commands. Files are transferred to/from the coprocessor
using “scp” or other means.
The default IP address for the coprocessor as seen from the host is 172.31.<coprocessor>.1, while the
coprocessor sees the host at 172.31.<coprocessor>.254 by default. The coprocessor can also be
referred to from the host by the alias mic<coprocessor>. For example, the first coprocessor you install in
your system is called “mic0” and is located at 172.31.1.1. It sees the host as 172.31.1.254. If a second
coprocessor were installed, it would be called “mic1” and located at 172.31.2.1, and it would see the host
as 172.31.2.254.
For detailed information on setting up the card for non-root users, adjusting the network configuration,
mounting an NFS file system exported by the host for use on the Intel® Xeon Phi™ coprocessor, etc., please
see the document Intel® MPSS User’s Guide.
Useful Administrative Tools
This product ships with the following administrative tools, found in the “/usr/bin” directory. Root, and
users needing to use these tools, should add this directory to their default path:
micinfo - provides information about host and coprocessor system configuration.
micflash - updates the flash on the coprocessor; saves and retrieves the version and other
information for each section of the flash
micsmc - a tool designed to ease the burden of monitoring and managing Intel® Xeon Phi™
coprocessors.
miccheck –a utility for verifying the configuration of an Intel® Xeon Phi™ coprocessor by running
various diagnostic tests.
micnativeloadex –a utility that will copy an Intel® MIC Architecture native binary to a specified Intel®
Xeon Phi™ coprocessor r and execute it
micctrl –a tool to help the system administrator configure and restart the coprocessor
micrasd –an application running on the host to handle and log hardware errors.
mpssflash –the POSIX version of micflash.
mpssinfo –the POSIX version of micinfo.
Please see section 8 in the MPSS User’s Guide for details on these tools and their arguments.
Getting Started/Developing Intel® Xeon Phi™ Software
You develop applications for the Intel® MIC Architecture using your existing knowledge of multi-core and SIMD
programming. The offload language extensions allow you to port sections of your code (written in C/C++ or
FORTRAN) to run on the Intel® Xeon Phi™ Coprocessor, or you can port your entire application to the Intel® MIC
Architecture. Best performance will only be attained with highly parallel applications that also use SIMD
operations (generated by the compiler or using compiler intrinsics) for most of their execution.

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Available Software Development Tools / Environments
You can start programming for the Intel® Xeon Phi™ Coprocessor using your existing parallel programming
knowledge and the same techniques you use to develop parallel applications on the host. New tools were not
created to support development directly on the Intel® Xeon Phi™ Coprocessor; rather, the familiar host-based
Intel tools have been extended to add support for the Intel® MIC Architecture via a few additions to standard
languages and APIs. However, to make best use of the development tools and to get best performance from
the Intel® Xeon Phi™ Coprocessor, it is important to understand the Intel® MIC Architecture.
Development Environment: Available Compilers and Libraries
Compilers
oIntel C++ Composer XE 2013 SP1 for building applications that run on Intel® 64 architecture
and Intel® MIC Architecture
oIntel® Fortran Composer XE 2013 SP1 for building applications that run on Intel® 64
architecture and Intel® MIC Architecture
Libraries packaged with the compilers include:
oIntel® Math Kernel Library (Intel® MKL) optimized for the Intel® MIC Architecture
oIntel® Threading Building Blocks (Intel® TBB)
oIntel® Integrated Performance Primitive (Intel® IPP)
Libraries packaged separately include:
oIntel® MPI for Linux* OS including Intel® Many Integrated Core (Intel® MIC) Architecture
oIntel® Trace Collector and Analyzer
oIntel® SDK for OpenCL* Applications XE 2013 available at: http://software.intel.com/en-
us/vcsource/tools/opencl-sdk-xe
Development Environment: Available Tools
In addition to the standard compilers and Intel libraries, the following tools are available to help you debug and
optimize software running on the Intel® Xeon Phi™ Coprocessor.
Debugger
oIntel® Debugger for applications running on the Intel® 64 architecture and Intel® MIC
Architecture
oIntel® C++ Eclipse* Product Extension including Debugging
Profiling
oIntel® VTune™ Amplifier XE 2013 for Linux, which is used on the host Linux OS to collect and
view performance data collected on the Intel® Xeon Phi™ Coprocessor
oIntel® Inspector XE 2013, which is used to detect memory and threading error for serial and
parallel applications
oIntel® Advisor XE 2013, which is used to assist developers to design threads.
General Development Information
Development Environment Setup
•To set up your development environment for use with the Intel tools, you need to source the
following script (the default install locations are assumed):

Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE
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oIntel® C++ and Fortran Composer XE 2013 SP1:
/opt/intel/composerxe/bin/compilervars.csh or compilervars.sh script
with intel64 as the argument, e.g.
source /opt/intel/composerxe/bin/compilervars.sh intel64
The following scripts are run as a result of calling the compilervars script. To get your
environment properly initialized, it is advisable not to run them individually (Among other things,
there are ordering issues that might result in unpredictable behavior.)
oIntel Debugger: /opt/intel/composerxe/pkg_bin/idbvars.csh or idbvars.sh
script with intel64 as the argument.
oIntel TBB: /opt/intel/composerxe/tbb/bin/tbbvars.csh or tbbvars.sh with
intel64 as the argument.
oIntel® MKL: /opt/intel/composerxe/mkl/bin/mklvars.csh or mklvars.sh with
intel64 as the argument.
Documentation and Sample Code
•The most useful documentation can be found in
/opt/intel/composerxe/Documentation/en_US/including:
ocompiler_c/main_cls/index.htm and compiler_f/main_cls/index.htm -
complete documentation for Intel® C++ Compiler XE 13.0 SP1 and the Intel® Fortran Compiler
XE 2013 SP1.
Most information on how to build for the Intel® MIC Architecture can be found in the “Key
Features/Intel® MIC Architecture” section under “Programming for the Intel® MIC
Architecture”
Information on Intel® MIC Architecture intrinsics can be found in the “Compiler
Reference/Intrinsics” section under “Intrinsics for Intel® MIC Architecture”
oRelease_notes_*_2013SP1_l_en.pdf - please read these carefully for known issues
and their workarounds, plus installation instructions, for all the tools with Intel® MIC
Architecture support. You’ll find Intel® MIC Architecture-specific information primarily in
section 3.
Note: For various reasons, this document can miss some last-minute updates. The most
recent Release_notes_*_2013SP1_l_en.pdf documents can be downloaded from the
Intel Registration Center (see Section “Steps to install the Software Development tools”).
odebugger/debugger_documentation.htm –Information on how to use the Intel
Debugger. You will find information specific to debugging Intel® MIC Architecture applications
under the “Debugging with the Intel® Debugger on Eclipse*” and “Debugging on the Command
Line” sections
•Other documentation that includes sections on using the Intel® Xeon Phi™ Coprocessor:
oThe Intel MKL User’s Guide, which can be accessed via mkl_documentation.htm found in
/opt/intel/composerxe/Documentation/en_US/mkl, contains a section called
“Using the Intel® Math Kernel Library on Intel® MIC Core Architecture Coprocessors” which
describes both “Automatic Offload” and “Compiler Assisted Offload” of Intel® MKL functions.
oInformation on collecting performance data on the Intel® Xeon Phi™ Coprocessor using VTune
Amplifier XE 2013 for Linux* can be found in

Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE
16
/opt/intel/vtune_amplifier_xe_2013/documentation/en/tutorials/fin
d_lw_hotspots/C++/index.htm
•Useful documentation on the Web:
oOn the website http://software.intel.com/mic-developer you will find a wide range of
documentation that can be downloaded, most notably the Intel® Xeon Phi™ Coprocessor
Software Developers Guide under “PROGRAMMING” tab., as well as including the System V
Application Binary Interface K1OM Architecture Processor Supplement, Intel® Xeon Phi™
Performance Monitor Units, and the Intel® Xeon Phi™ Coprocessor Instruction Set Reference
Manual (under “OVERVIEW” tab) . From this site you will also be able to find a community
forum to ask questions, links to other available tools, code samples, and case studies.
ohttp://software.intel.com/en-us/articles/programming-and-compiling-for-intel-many-
integrated-core-architecture contains a wealth of information on compilers.
•Some sample offload code using the explicit memory copy model can be found in:
oC++:
/opt/intel/composerxe/Samples/en_US/C++/mic_samples/intro_sampleC/
oFortran: /opt/intel/composerxe/Samples/en_US/Fortran/mic_samples/
oIntel® MKL: /opt/intel/composerxe/mkl/examples/mic*
oFor examples of Intel® MKL automated offload:
/opt/intel/composerxe/mkl/examples/mic_ao/blasc
and …/mic_ao/blasf
oThe rest of the samples demonstrate use of MKL via compiler-assisted offload
(/opt/intel/composerxe/mkl/examples/mic_offload).
•Some sample offload code using the implicit memory copy model can be found in:
oC:
/opt/intel/composerxe/Samples/en_US/C++/mic_samples/shrd_sampleC
and …/LEO_tutorial
oC++:
/opt/intel/composerxe/Samples/en_US/C++/mic_samples/shrd_sampleCP
P
Build-Related Information
•The offload compiler produces “fat” binaries and .so files that contain code for both host and the
Intel® Xeon Phi™ Coprocessor.
•The offload compiler produces code that examines the runtime execution environment for the
presence of an Intel® Xeon Phi™ Coprocessor. The offload compiler will create both host and Intel® MIC
Architecture versions of all code marked for offload.
•A number of workarounds and hints can be found in releaseNotes-linux.txt.
Compiler Switches and Makefiles
When building applications that offload some of their code to the Intel® Xeon Phi™ Coprocessor, it is possible to
cause the offloaded code to be built with different compiler options from the host code. The method of
passing these options to the compiler is documented in the compiler documentation under the “Compiler
Reference/Compiler Options/Compiler Option Categories and Descriptions” section. Look for the –offload-
option compiler switch. In that same section, also look up the –offload-attribute-target compiler

Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE
17
switch, which provides an alternative to editing your source files in some situations (applies to the pragma-
based offload methods). Finally, -no-offload provides a way to make the compiler ignore the
_Cilk_offload and #pragma_offload constructs (which cause it by default to build a heterogeneous
binary).
Debugging During Runtime
To debug offload activity, the following environment variables are available:
To learn whether offload portions of the program are running on the host or coprocessor
For csh –setenv H_TRACE 1
For sh –export H_TRACE=1
For more complete debug information
For csh –setenv H_TRACE 2
For sh –export H_TRACE=2
To print the compiler’s internal offload timers, a value of 1 reports just the time the offload took
measured by the host, and the amount of computation time done by the coprocessor. A value of
2 adds information on how much data was transferred in either direction.
For csh –setenv OFFLOAD_REPORT <1 or 2>
For sh –export OFFLOAD_REPORT=<1 or 2>
Details can be found in the compiler documentation in the “Compilation/Setting Environment Variables” section.
Where to Get More Help
You can visit the Forum on the Intel® Xeon Phi™ Coprocessor to post questions. It can be found at the
http://software.intel.com/en-us/forums/intel-many-integrated-core .
Using the Offload Compiler –Explicit Memory Copy Model
In this section, a reduction is used as an example to show a step-by-step approach for developing applications
for the Intel® Xeon Phi™ Coprocessor using the offload compiler. The offload compiler is a heterogeneous
2
compiler, with both host CPU and target compilation environments. Code for both the host CPU and Intel® Xeon
Phi™ coprocessor is compiled within the host environment, and offloaded code is automatically run within the
target environment. The offload behavior is controlled by compiler directives: pragmas in C/C++, and
directives in Fortran.
Some common libraries, such as the Intel® Math Kernel Library (Intel® MKL), are available in host versions as
well as target versions. When an application executes its first offload and the target is available, the runtime
loads the target executable onto the Intel® Xeon Phi™ Coprocessor. At this time, it also initializes the libraries
linked with the target code. The loaded target executable remains in the target memory until the host
program terminates. Thus, any global state maintained by the library is maintained across offload instances.
2
http://dictionary.reference.com/browse/heterogeneous

Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE
18
Note: Although, the user may specify the region of code to run on the target, there is no guarantee of
execution on the Intel® Xeon Phi™ Coprocessor. Depending on the presence of the target hardware or the
availability of resources on the Intel® Xeon Phi™ Coprocessor when execution reaches the region of code
marked for offload, the code can run on the Intel® Xeon Phi™ Coprocessor or not.
The following code samples show several versions of porting reduction code to the Intel® Xeon Phi™
Coprocessor using the offload pragma directive.
Reduction
The operation refers to computing the expression:
ans = a[0] + a[1] + … + a[n-1]
Host Version:
The following sample code shows the C code to implement this version of the reduction.
float reduction(float *data, int size)
{
float ret = 0.f;
for (int i=0; i<size; ++i)
{
ret += data[i];
}
return ret;
}
Code Example 1: Implementing Reduction Code in C/C++
Creating the Offload Version
Serial Reduction with Offload
The programmer uses #pragma offload target(mic) (as shown in the example below) to mark statements
(offload constructs) that should execute on the Intel® Xeon Phi™ Coprocessor. The offloaded region is defined
as the offload construct plus the additional regions of code that run on the target as the result of function
calls. Execution of the statements on the host will resume once the statements on the target have executed
and the results are available on the host (i.e. the offload will block, although there is a version of this pragma
that allows asynchronous execution). The in,out,and inout clauses specify the direction of data to be
transferred between the host and the target.
Variables used within an offloaded construct that are declared outside the scope of the construct (including
the file-scope) are copied (by default) to the target before execution on the target begins and copied back to
the host on completion.
For example, in the code below, the variable ret is automatically copied to the target before execution on the
target and copied back to the host on completion. The offloaded code below is executed by a single thread on
a single Intel® MIC Architecture core.

Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE
19
float reduction(float *data, int size)
{
float ret = 0.f;
#pragma offload target(mic) in(data:length(size))
for (int i=0; i<size; ++i)
{
ret += data[i];
}
return ret;
}
Code Example 2: Serial Reduction with Offload
Vector Reduction with Offload
Each core on the Intel® Xeon Phi™ Coprocessor has a VPU. The auto vectorization option is enabled by default
on the offload compiler. Alternately, as seen in the example below, the programmer can use the Intel® Cilk™
Plus Extended Array Notation to maximize vectorization and take advantage of the Intel® MIC Architecture
core’s 32 512-bit registers. The offloaded code is executed by a single thread on a single core. The thread
uses the built-in reduction function __sec_reduce_add() to use the core’s 32 512-bit vector registers to
reduce the elements in the array sixteen at a time.
float reduction(float *data, int size)
{
float ret = 0;
#pragma offload target(mic) in(data:length(size))
ret = __sec_reduce_add(data[0:size]); //Intel® Cilk™ Plus
//Extended Array Notation
return ret;
}
Code Example 3: Vector Reduction with Offload in C/C++
Asynchronous Offload and Data Transfer
Asynchronous offload and data transfer between the host and the Intel® Xeon Phi™ Coprocessor is available.
For details see the “About Asynchronous Computation” and “About Asynchronous Data Transfer” sections in
the Intel® C++ Compiler User and Reference Guide (under “Key Features/Programming for the Intel® MIC
Architecture”).
For an example showing the use of asynchronous offload and transfer, refer to /opt/intel/composerxe
/Samples/en_US/C++/mic_samples/intro_sampleC/sampleC13.c
Note that when using the Explicit Memory Copy Model in C/C++, arrays are supported provided the array
element type is scalar or bitwise copyable struct or class. So arrays of pointers are not supported. For C/C++
complex data structure, use the Implicit Memory Copy Model. Please consult the section “Restrictions on
Offload Code Using a Pragma” in the document “Intel C++ Compiler User and Reference Guide” for more
information.
Using the Offload Compiler –Implicit Memory Copy Model
Intel Composer XE 2013 SP1 includes two additional keyword extensions for C and C++ (but not Fortran) that
provide a “shared memory”offload programming model appropriate for dealing with complex, pointer-based

Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE
20
data structures such as linked lists, binary trees, and the like (_Cilk_shared and _Cilk_offload).This
model places variables to be shared between the host and coprocessor (marked with the _Cilk_shared
keyword) at the same virtual addresses on both machines, and synchronizes their values at the beginning and
end of offload function calls marked with the _Cilk_offload keyword. Data to be synchronized can also
be dynamically allocated using special allocation and free calls that ensure the allocated memory exists at the
same virtual addresses on both machines.
APIs for Dynamic shared memory allocation:
void *_Offload_shared_malloc(size_t size);
_Offload_shared_free(void *p);
APIs for Dynamic Aligned Shared memory allocation
void *_Offload_shared_aligned_malloc(size_t size, size_t alignment);
_Offload_shared_aligned_free(void *p);
It should be noted that this is not actually “shared memory”: there is no hardware that maps some portion of
the memory on the Intel® Xeon Phi™ Coprocessor to the host system. The memory subsystems on the
coprocessor and host are completely independent, and this programming model is just a different way of
copying data between these memory subsystems at well-defined synchronization points. The copying is
implicit, in that at these synchronization points (offload calls marked with _Cilk_offload) do not specify
what data to copy. Rather, the runtime determines what data has changed between the host and coprocessor,
and copies only the deltas at the beginning and end of the offload function call.
The following code sample demonstrates the use of the _Cilk_shared and _Cilk_offload keywords
and the dynamic allocation of “shared”memory.
float * _Cilk_shared data; //pointer to “shared”memory
_Cilk_shared float MIC_OMPReduction(int size)
{
#ifdef __MIC__
float Result;
int nThreads = 32;
omp_set_num_threads(nThreads);
#pragma omp parallel for reduction(+:Result)
for (int i=0; i<size; ++i)
{
Result += data[i];
}
return Result;
#else
printf("Intel(R) Xeon Phi(TM) Coprocessor not available\n");
#endif
return 0.0f;
}
int main()
{