BenQ M23 Guide

©2003 BenQ Corporation Confidential Property
M23DesignGuide Version:0.1 -2003/12/12
1
M23
GSM / GPRS Wireless Module
Design Guide
Rev. 0.1
December. 2003
COPYRIGHT BENQ Corporation
This document contains proprietary technical information which is the property of BenQ Corporation
and is issued in strict confidential and shall not be disclosed to others parties in whole or in parts
without written permission of BenQ Corporation
The documents contain information on a product, which is under development and is issued for cus-
tomer evaluation purposes only.
BENQ may make changes to product specifications at any time, without notice.
BenQ Corporation
Networking & Communications BG
18 JiHu Road, Nei-Hu, Taipei 114, Taiwan, R.O.C.
Tel: [phone]
Fax: [phone]
http://www.benq.com

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M23DesignGuide Version:0.1 -2003/12/12
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1. OVERVIEW.............................................................................................................................................................................................3
2. DESIGN GUIDE ORGANIZATION.....................................................................................................................................................4
3. PIN ASSIGNMENT OF M23 MODULE...............................................................................................................................................5
3.1. M23 MODULE PLACEMENT .....................................................................................................................................................5
3.2. GROUND PIN..................................................................................................................................................................................5
3.3. VBATRF PIN (PIN 41~43) /VBATBB PIN (PIN 1).........................................................................................................5
3.4. POWER ON SEQUENCE ................................................................................................................................................................6
3.5. INTERRUPT .....................................................................................................................................................................................6
3.7 THE HANDSHAKING MECHANISM BETWEEN SYSTEM (HOST)AND MODULE (CLIENT).......................................10
3.8 POWER ON/OFF SEQUENCE BETWEEN SYSTEM (HOST)AND MODULE (CLIENT)................................................12
4PERIPHERALS.....................................................................................................................................................................................14
4.1 SIM.................................................................................................................................................................................................14
4.2 AUDIO............................................................................................................................................................................................14
4.3 PAGING INDICATOR ............................................................................................................................................................................16
4.4ACOUSTIC TEST (DAI INTERFACE)...............................................................................................................................................17
5IO MAPPING.........................................................................................................................................................................................18
6UART INTERFACE ..............................................................................................................................................................................19
7RS232 (HW FLOW CONTROL).........................................................................................................................................................20
8POWER ON/OFF CONCERNS...........................................................................................................................................................22

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M23DesignGuide Version:0.1 -2003/12/12
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1. Overview
This design guide is based mainly on the M23 evaluation board (EVB). The M23 EVB enables you to
evaluate the M23 module and peripheral design. In addition, it provides sampling firmware that you
can use as a starting point to develop code. To give the user a system concept of the interconnections
between the host and M23 module, we first give a block diagram as
The reference schematics for M23 peripherals will be given in details in this design guide. Since the
interconnections between the host and M23 vary by application, we tend to give only reference de-
signs of general functions, such as, interrupts,
re-download mechanisms, flow control of RS232, etc.

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2. Design Guide Organization
The rest of the manual is organized as follows:
Section 3 Pin out definition of M23 module is given along with the RF antenna placement and trace
guidelines. In addition, the recommended power on; and handshaking sequences are
shown.
Section 4 Suggested peripheral schematics, i.e., SIM, audio, and paging indicator is given.
Section 5 The IO mapping of the M23 module is explained in details.
Section 6 The UART interface pin description is given.
Section 7 The re-download procedure is shown.
Section 8 Hardware flow control of the RS232 is illustrated in details.
Section 9 Some related power on/off concerns are given.

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3. Pin Assignment of M23 module
The following is the pin out definition of the M23 module
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VBATBB
TXD2
VBATRF
VBATRF
VBATRF
GND
IO10
PWON
RXD2
GND
AUXOP
GND
AUXI
DSR
IO8
IO13
IO11
GND
IO6
IO1/RI
EARN
EARP
GND
VRSIM
MICIN
MICIP
MICBIAS
NC
SIM_RST
SIM_IO
SIM_CLK
CTS
IO12/DCD BU
ROW4
LEDA
GND
GND
GND
RTS
GND
GND
TXD
RXD
3.1. M23 Module Placement
In our module, we have one 50ohm antenna port (interfaced by MMCX female connector) for signal
transfer, and the Antenna port can be directly connected to antenna though RF coaxial cable. In addi-
tion, the RF signal will be impacted by high data rate. We strongly suggest the audio trace and SIM
signal trace to be short as possible and as far away as possible from the RF trace and power line to
prevent cross coupling.
3.2. Ground Pin
There are 10 ground pins in M23 module, they should be connected together and routed to the
common connection of the PCB ground plane (The ground plane in PCB should be as large as
possible).
3.3. VBATRF Pin (Pin 41~43) / VBATBB Pin (Pin 1)
The “Power amplifier” is supplied by the VBATRF pins. During transmitting mode, high output power
will draw a large amount of current. The width of this power trace that is connected to the VBATRF
pins could not be less than 80mils. In addition, it is better to shunt a 100uF (low ESR) bypass ca-
pacitor on VBATRF pins to prevent voltage drop and to reduce ripple. Furthermore, another chips in

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M23DesignGuide Version:0.1 -2003/12/12
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the module are supplied by the VBATBB pin. The width of this trace that connected to this pin
should also be wider.
3.4. Power on sequence
The pin POWON is dedicated to powering on the M23 module. The pin is initially HIGH when
power is applied to the M23 module. Once the pin is pulled low for more than 120 ms, M23 will
power on.
3.5. Interrupt
There are two pins dedicated to work as an acknowledge function between the system (Host) and
module (Client):
The pin IO10 is used for the M23 module (Client) to interrupt the system (Host), whereas the pin
Row4 is used for the system (Host) to interrupt the M23 module (Client).
Pin Name Function
39 IO10 (active high) Module (Client) informs system (Host)
7 Row 4 (active low) System (Host) informs module (Client)
120 ms

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Note: Vcc comes from system.
Note: The scenario in Figure 1 is to be used when the Module is required to control the switches
connecting the UARTs and GPIOs of the host and module. This is done when the module power off.
The AND gate in the above diagram can be implemented by the following schematics.
Figure 1 Application Connection Diagram

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AND GATE OUTPUT, PWON, ROW4, IO11 Sequence
IO11
ROW4
R2
100K
U5
NC7SZ08
1
2
3
6
5
4
A
B
GND
VCC
NC
Y
R1
220K
R4
2K
BGND
BGND
BGND
R3
22K
VCC
BQ1
BC817-40W
1
2 3
VCC
BGND

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VCC=4V; M23 VBAT=4V
IO11：reset status is input
ROW4/wakeup：input pin pull high after trigger
Note: The mechanism shows that after the PWON pin is pulled low, ROW4 becomes HIGH after 63ms.
At the same time interval IO11 remains input status, since the resistor R3 pulls IO11 to low within the
reset period, therefore BQ1 is kept open and pin 3 of BQ1 is kept high. Meanwhile Row4 is high, so the
output of the AND gate (U5) is high and the switch is closed. If the switch needs to be opened, the
IO11 can be controlled to be high and BQ1 will close. This in turn will make pin 2 of U5 Low. The output
of the AND gate will therefore be low and the switch will be opened. During power off of the module,
the pull Low resistor R1 will keep the pin 1 of U5 to low and therefore the output of theAND gate will be
Low also. Thus opening the switch in Figure 1.

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3.7 The handshaking mechanism between System (Host) and Module (Client)
Note: The UART function of the handshaking mechanism is defined to be hardware flow control type.
Module (Client) needs to inform system (Host) of tasks
Module (Client)
Yes
Is there incoming task? No
Module pulls high IO10 40~50ms to inform
system, Module is going to do something
and sets IO11 Low (default)
Module (Client) via UART
sends command to system
40~50ms
IO 10
Module (Client) kept at
original status
The above block diagram shows how the module informs the host system that a task requiring inter-
action will be carried out. When the tasking is coming, the module pulls HIGH IO10 for at least 40~50
ms to inform host that a task will be carried out.
Note: Based on Figure 1, assume the interrupt pin in system (Host) is low active, therefore if module
needs to inform system via IO10, the module have to pull high IO10 a time interval to achieve this
requirement,

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System (Host) informs Module (Client) of tasks
Inform Module?
System (Host) Side
Module kept at original
status
Check if module
sleep mode is off Send AT command
Host need to keep module
out of sleep mode?
Send AT command to
activate sleep mode
System(Host) pull low Row4
50ms to inform Module, and
immediately sends "don't
deep sleep" command to
disable module deep sleep
mode (or any other AT
command)
Yes
No
Yes
No
No
Yes
The above block diagram shows how the host system informs the module that a task requiring inter-
action will be carried out.
Note: The above procedure is exclusively used in hardware flow control configuration.

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3.8 Power on/off sequence between System (Host) and Module (Client)
Power on sequence
System (Host) side
Power on Module?
Pull Low PWON for 120 ms
M22 is Powered On
Module sets IO10 High 40 ~ 50 ms
to inform system power on
Module kept
power off
No
Yes
Success
120ms
PWON
40~50ms
IO10
System (Host) sends "AT" to
Module, and Module returns "OK" to
Host
The above block diagram shows the power on sequence. First the host powers on and pulls Low
PWON of the module for at least 120 ms. When the module is powered on, it sets IO10 will High 40 ~
50 ms .

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Power off sequence
System (Host) side
Power off Module?
System sends AT command
'at$poweroff' to set Module into
power off
Module receives AT command
Module prepares to power off
Module kept on
No
Yes
Success (returns ACK to host)
Fail
The above block diagram shows the power off sequence. The host sends an AT command
‘at$poweroff’ to set module into power off. Module powers off once AT command is received. Please
note that if the host system is left powered on, switches are suggested to protect from current leakage.
Note : User can not try to power on module within 2000 ms after sending at$poweroff command
to module

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4 Peripherals
4.1 SIM
The SIM Card digital interface in the M23 ensures the translation of logic levels between M23 and
the SIM Card, for the transmission of 3 different signals: SIM_CLK; a reset signal from M23 to the
SIM Card (SIM_RST); and serial data from M23 to the SIM Card (SIM_IO). The SIM card interface
can be programmed to drive a 3V SIM Card.
(1) Type I ( 8 Pin SIM Socket )
(2) Type II ( 6 Pin SIM Socket )
4.2 Audio
There are 2 embedded audio drivers built in the BenQ M23 module. The 2 drivers can drive different
kinds of audio load (such as receiver, microphone, or hands free).
¾Microphone

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¾Auxiliary Input/output
¾Ear output
Audio Path Selection AT Commands
The M23 module provides the switching of audio paths using AT commands (In connection status):
Default value: case (2)
(1) at$aupath=3,0 (EARN, EARP, MICIN, MICIP, MICBIAS path OFF)
(2) at$aupath=3,1 (EARN, EARP, MICIN, MICIP, MICBIAS path ON)
(3) at$aupath=2,0 (AUXI,AUXOP,MICBIAS path OFF)
(4) at$aupath=2,1 (AUXI,AUXOP,MICBIAS path ON)
R53
1K
C17
4.7UF
AUXOP
J6
Audio Jack
GND 1 SW
2
SPK
3
MIC
4
T3
TVS
.1
.
2
BGND
T2
TVS
.1
.
2
BGND
R51
2K
R54
2K
BGND
R57
5.6K
C17
4.7UF
BGND
MICBIAS
BQ5
BC817-40W
1
2 3
C15
1UF
C13
0.1UF
AUXI
BGNDBGND
Volta
g
e Gain = 2 with R60=3.3K
R60
3.3K
R58
12K

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4.3 Paging Indicator
LEDA is dedicated for paging indication. The application circuit is shows as below. The diagram
below illustrates the application schematic for LED driver inputs LEDA. In each case the current
limiter resistor R has to be selected in order to be compliant with maximum current drive capability
of each input.
Pin Name Max drive current High level voltage Low level voltage supply Function
6 LEDA 10mA VBATBB 0.4 VBATBB paging indicator
Module
<Value>
LEDA
VBAT
LEDA is controlled through software program using a dedicated bit, which is built in the M23
module already.
The LEDA pin status :
a. When there is no voltage input, the LEDA is in high status. It means that the LED won’t be
illuminated.
b. When the module is powered on and not making phone calls, LEDAwill pull low 500 ms and
pull high 500 ms, alternately.
c. When incoming phone call, the LEDA will pull low 125 ms and return to high status 125ms
after hanging up the phone

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4.4 Acoustic test (DAI interface)
*Pin 28 is multipurpose function pin (switch by config JP5). In normal operation mode, it pin is function
as GPIO1 (JP5 is setting as Case 1). In acoustic test mode, it pin is function as DAI interface (JP5
should be setting as Case 2)
Pin Name Pin Out Pull Reset Config Description
MCSI_TXD/IO 9 28* 0 0 Transmit serial data
MCSI_RXD/IO10 4 Input Input Receive serial data
MCSI_CLK/IO 11 30 Input Input Bit synchronization clock
MCSI_FSYNCH/IO 12 10 Input Input Frame synchronization clock or SS reset
JP5
IO9
JP5
Case1 Case2

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5 IO mapping
There have 6 IO pins available for M23 module. The function for these IO pins is List below.
No. Pin Description I/O PU Reset Config
39 IO 10 M23 (Client) wake up System (Host) O Input Output / 0
28 IO 13 GPIO13 I Output/1 Input
25 IO 6 Re-download Data path and audio path switch O Input Output/1
27 IO 11
Power off mode switch control signal to open or
link the connection between system (Host) and
module (client).
Low :; Connect
High: Disconnect
Default = Connect ( Low )
O Input Output / 0
9 IO 12/DCD IO12/Data Carrier Detect O Input Output / 0
24 IO 1/RI IO1/Ring Indicator O Input Output / 0

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6 UART Interface
UART/RS232
The UART includes the following additional features
-Hardware flow control (DSR, RTS/CTS)
-Auto-bauding rate with the possibility of baud-rates ranging from 1200 to 115.2K bits.
Pin Name Pin Out Pull Reset Config Description
TXD 34 1 Output/1 Transmit Data
RXD 33 PU Input Input Receive Data
RTS 32 1 Output/1 Request to Send
CTS 31 PD Input Input Clear to Send
DSR 30 Input Input Data Set Ready
IO 8/DTR 29 1 Output/0 Data Terminal Ready
Note: The difference between Reset and Config in the pin definition table
UART 2
Used for software debug.
Pin Name Pin Out Pull Reset Config Description
TXD2 8 1 Output/1 Transmit Data
RXD2 37 PU Input Input Receive Data

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TX
RX
RTS
CTS
GND
7 RS232 (HW flow control)
There are two types of UART connection able to implement the communication between the sys-
tem (Host side) and module (Client side).
HW flow control
When the hardware flow control type is recommended for communication between the Host and client,
IO13 of the module must be pulled high to 3V to setup module into this condition. Regarding the
hardware flow control mechanism between the system (host side) and module (client side), there are
two connections possible and are illustrated as follows:
Option 1:
Option :2
Note: Since the DSR in M23 is PU 10K.
TX
RX
DTR
DSR
RTS
CTS
GND
TX
RX
DTR
DSR
RTS
CTS
GND
TX
RX
RTS
CTS
DSR
DTR
GND
M23
External
Device
HOST
Device
M23
HOST
Device