BenQ M23 Guide

©2003 BenQ Corporation Confidential Property
M23DesignGuide Version:0.1 -2003/12/12
1
M23
GSM / GPRS Wireless Module
Design Guide
Rev. 0.1
December. 2003
COPYRIGHT BENQ Corporation
This document contains proprietary technical information which is the property of BenQ Corporation
and is issued in strict confidential and shall not be disclosed to others parties in whole or in parts
without written permission of BenQ Corporation
The documents contain information on a product, which is under development and is issued for cus-
tomer evaluation purposes only.
BENQ may make changes to product specifications at any time, without notice.
BenQ Corporation
Networking & Communications BG
18 JiHu Road, Nei-Hu, Taipei 114, Taiwan, R.O.C.
Tel: [phone]
Fax: [phone]
http://www.benq.com

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M23DesignGuide Version:0.1 -2003/12/12
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1. OVERVIEW.............................................................................................................................................................................................3
2. DESIGN GUIDE ORGANIZATION.....................................................................................................................................................4
3. PIN ASSIGNMENT OF M23 MODULE...............................................................................................................................................5
3.1. M23 MODULE PLACEMENT .....................................................................................................................................................5
3.2. GROUND PIN..................................................................................................................................................................................5
3.3. VBATRF PIN (PIN 41~43) /VBATBB PIN (PIN 1).........................................................................................................5
3.4. POWER ON SEQUENCE ................................................................................................................................................................6
3.5. INTERRUPT .....................................................................................................................................................................................6
3.7 THE HANDSHAKING MECHANISM BETWEEN SYSTEM (HOST)AND MODULE (CLIENT).......................................10
3.8 POWER ON/OFF SEQUENCE BETWEEN SYSTEM (HOST)AND MODULE (CLIENT)................................................12
4PERIPHERALS.....................................................................................................................................................................................14
4.1 SIM.................................................................................................................................................................................................14
4.2 AUDIO............................................................................................................................................................................................14
4.3 PAGING INDICATOR ............................................................................................................................................................................16
4.4ACOUSTIC TEST (DAI INTERFACE)...............................................................................................................................................17
5IO MAPPING.........................................................................................................................................................................................18
6UART INTERFACE ..............................................................................................................................................................................19
7RS232 (HW FLOW CONTROL).........................................................................................................................................................20
8POWER ON/OFF CONCERNS...........................................................................................................................................................22

©2003 BenQ Corporation Confidential Property
M23DesignGuide Version:0.1 -2003/12/12
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1. Overview
This design guide is based mainly on the M23 evaluation board (EVB). The M23 EVB enables you to
evaluate the M23 module and peripheral design. In addition, it provides sampling firmware that you
can use as a starting point to develop code. To give the user a system concept of the interconnections
between the host and M23 module, we first give a block diagram as
The reference schematics for M23 peripherals will be given in details in this design guide. Since the
interconnections between the host and M23 vary by application, we tend to give only reference de-
signs of general functions, such as, interrupts,
re-download mechanisms, flow control of RS232, etc.

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M23DesignGuide Version:0.1 -2003/12/12
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2. Design Guide Organization
The rest of the manual is organized as follows:
Section 3 Pin out definition of M23 module is given along with the RF antenna placement and trace
guidelines. In addition, the recommended power on; and handshaking sequences are
shown.
Section 4 Suggested peripheral schematics, i.e., SIM, audio, and paging indicator is given.
Section 5 The IO mapping of the M23 module is explained in details.
Section 6 The UART interface pin description is given.
Section 7 The re-download procedure is shown.
Section 8 Hardware flow control of the RS232 is illustrated in details.
Section 9 Some related power on/off concerns are given.

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M23DesignGuide Version:0.1 -2003/12/12
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3. Pin Assignment of M23 module
The following is the pin out definition of the M23 module
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VBATBB
TXD2
VBATRF
VBATRF
VBATRF
GND
IO10
PWON
RXD2
GND
AUXOP
GND
AUXI
DSR
IO8
IO13
IO11
GND
IO6
IO1/RI
EARN
EARP
GND
VRSIM
MICIN
MICIP
MICBIAS
NC
SIM_RST
SIM_IO
SIM_CLK
CTS
IO12/DCD BU
ROW4
LEDA
GND
GND
GND
RTS
GND
GND
TXD
RXD
3.1. M23 Module Placement
In our module, we have one 50ohm antenna port (interfaced by MMCX female connector) for signal
transfer, and the Antenna port can be directly connected to antenna though RF coaxial cable. In addi-
tion, the RF signal will be impacted by high data rate. We strongly suggest the audio trace and SIM
signal trace to be short as possible and as far away as possible from the RF trace and power line to
prevent cross coupling.
3.2. Ground Pin
There are 10 ground pins in M23 module, they should be connected together and routed to the
common connection of the PCB ground plane (The ground plane in PCB should be as large as
possible).
3.3. VBATRF Pin (Pin 41~43) / VBATBB Pin (Pin 1)
The “Power amplifier” is supplied by the VBATRF pins. During transmitting mode, high output power
will draw a large amount of current. The width of this power trace that is connected to the VBATRF
pins could not be less than 80mils. In addition, it is better to shunt a 100uF (low ESR) bypass ca-
pacitor on VBATRF pins to prevent voltage drop and to reduce ripple. Furthermore, another chips in

©2003 BenQ Corporation Confidential Property
M23DesignGuide Version:0.1 -2003/12/12
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the module are supplied by the VBATBB pin. The width of this trace that connected to this pin
should also be wider.
3.4. Power on sequence
The pin POWON is dedicated to powering on the M23 module. The pin is initially HIGH when
power is applied to the M23 module. Once the pin is pulled low for more than 120 ms, M23 will
power on.
3.5. Interrupt
There are two pins dedicated to work as an acknowledge function between the system (Host) and
module (Client):
The pin IO10 is used for the M23 module (Client) to interrupt the system (Host), whereas the pin
Row4 is used for the system (Host) to interrupt the M23 module (Client).
Pin Name Function
39 IO10 (active high) Module (Client) informs system (Host)
7 Row 4 (active low) System (Host) informs module (Client)
120 ms

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M23DesignGuide Version:0.1 -2003/12/12
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Note: Vcc comes from system.
Note: The scenario in Figure 1 is to be used when the Module is required to control the switches
connecting the UARTs and GPIOs of the host and module. This is done when the module power off.
The AND gate in the above diagram can be implemented by the following schematics.
Figure 1 Application Connection Diagram

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M23DesignGuide Version:0.1 -2003/12/12
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AND GATE OUTPUT, PWON, ROW4, IO11 Sequence
IO11
ROW4
R2
100K
U5
NC7SZ08
1
2
3
6
5
4
A
B
GND
VCC
NC
Y
R1
220K
R4
2K
BGND
BGND
BGND
R3
22K
VCC
BQ1
BC817-40W
1
2 3
VCC
BGND

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M23DesignGuide Version:0.1 -2003/12/12
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VCC=4V; M23 VBAT=4V
IO11：reset status is input
ROW4/wakeup：input pin pull high after trigger
Note: The mechanism shows that after the PWON pin is pulled low, ROW4 becomes HIGH after 63ms.
At the same time interval IO11 remains input status, since the resistor R3 pulls IO11 to low within the
reset period, therefore BQ1 is kept open and pin 3 of BQ1 is kept high. Meanwhile Row4 is high, so the
output of the AND gate (U5) is high and the switch is closed. If the switch needs to be opened, the
IO11 can be controlled to be high and BQ1 will close. This in turn will make pin 2 of U5 Low. The output
of the AND gate will therefore be low and the switch will be opened. During power off of the module,
the pull Low resistor R1 will keep the pin 1 of U5 to low and therefore the output of theAND gate will be
Low also. Thus opening the switch in Figure 1.

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3.7 The handshaking mechanism between System (Host) and Module (Client)
Note: The UART function of the handshaking mechanism is defined to be hardware flow control type.
Module (Client) needs to inform system (Host) of tasks
Module (Client)
Yes
Is there incoming task? No
Module pulls high IO10 40~50ms to inform
system, Module is going to do something
and sets IO11 Low (default)
Module (Client) via UART
sends command to system
40~50ms
IO 10
Module (Client) kept at
original status
The above block diagram shows how the module informs the host system that a task requiring inter-
action will be carried out. When the tasking is coming, the module pulls HIGH IO10 for at least 40~50
ms to inform host that a task will be carried out.
Note: Based on Figure 1, assume the interrupt pin in system (Host) is low active, therefore if module
needs to inform system via IO10, the module have to pull high IO10 a time interval to achieve this
requirement,