Bg BG0836 User manual

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BG0836 1/2.7inch 1080P CMOS
Imaging sensor application note
General Descriptions
BG0836 is a high performance 1/2.7 inch CMOS imaging
sensor with an active-pixel array of 1928H x 1088V.
Features
⚫Support 1-Lane MIPI interface.
⚫Trigger exposure operation: single and multi-
frame.
⚫Auto black level calibration.
⚫Maximum 30 frame per second.
Applications
⚫Senior surveillance
⚫Automobile data recorder
Key Parameter
Table 1 Key Specification
Parameter
Typical Value
Optical format
1/2.7inch
Active pixel array
1928H x1088V
Pixel size
3.00um(H) x
3.00um(V)
Active pixel array Area
5784um x
3264um
Frame rate
30fps@full frame
Color filter array
Bayer RGB
CRA
0°
Shutter Type
Electronic Rolling
Sensitivity@550nm
3.8V/(lux.sec)
Dark current@60⁰C
10mV/s
SNRmax
36dB
Dynamic range
65dB
Output
12-bit DVP
1-Lane MIPI
Power
supply
Digital
1.42V~1.65V
IO
1.7V~3.45V
Analog
3.15V~3.45V
Pixel
3.15V~3.45V
Power Consumption
TBD@30fps
Temperature range
-30 ~70 ⁰C
Package Option
CSP
In the absence of confirmation by device specification sheets, BRIGATES takes no responsibility for any defects that may occur in equipment using any BRIGAGES
device shown in catalogs, data book, etc. Contact BRIGATES in order to obtain the latest device specification before using any BRIGATES device.

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Table of Content
General Descriptions.......................................................................................................................................................1
Features...........................................................................................................................................................................1
Applications ....................................................................................................................................................................1
Key Parameter.................................................................................................................................................................1
PCB design guideline......................................................................................................................................................5
Package diagram .....................................................................................................................................................5
Pin configuration.....................................................................................................................................................6
Application circuits.................................................................................................................................................8
Power supply design ...............................................................................................................................................9
PCB notice ............................................................................................................................................................10
Checklist ...............................................................................................................................................................11
Register Slave Interface ................................................................................................................................................11
I2C Slave Interface................................................................................................................................................11
Shadow register.....................................................................................................................................................12
Optical Design ..............................................................................................................................................................13
Imaging direction ..................................................................................................................................................13
Mirror function......................................................................................................................................................13
Adjust the wide and frame rate .....................................................................................................................................14
CFA assignment ....................................................................................................................................................14
The calculation of the clock..........................................................................................................................................14
The definition of the clock....................................................................................................................................14
PLL control ...................................................................................................................................................................15
Main System Clock control...................................................................................................................................15
Adjust the size.......................................................................................................................................................16
Adjust the frame rate.............................................................................................................................................16
Adjust the exposure and gain ........................................................................................................................................17
Adjust the exposure...............................................................................................................................................17
Adjust the gain ......................................................................................................................................................18
Adjust the gain strategy.........................................................................................................................................19
Black level calibration ..................................................................................................................................................19
MIPI ..............................................................................................................................................................................20
Others............................................................................................................................................................................21
IO adjust the drive ability......................................................................................................................................21
Pixel Clock phase adjustment ...............................................................................................................................21
FQA ..............................................................................................................................................................................22
Revision history ............................................................................................................................................................23

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List of Figures
Figure 1 Mechanical Drawing ........................................................................................................................................5
Figure 2 Pin configuration ..............................................................................................................................................6
Figure 3 Recommended schematic with MIPI interface.................................................................................................8
Figure 4 Recommended schematic with DVP interface..................................................................................................9
Figure 5 Recommend Power Tree（1.8V IO）..............................................................................................................9
Figure 6 Power-up Sequence ........................................................................................................................................10
Figure 7 I2C write operation........................................................................................................................................11
Figure 8 I2C read operation .........................................................................................................................................12
Figure 9 Imaging a Scene.............................................................................................................................................13
Figure 10 mirror function schematic.............................................................................................................................13
Figure 11 Color Filter Arrangements ............................................................................................................................14
Figure 12 PLL block diagram .......................................................................................................................................15
Figure 13 output waveform and frame rate calculation ................................................................................................16
Figure 14 BLC Convergence signal..............................................................................................................................20
Figure 15 raw10/raw12 Data output sequence..............................................................................................................21
Figure 16 Mipi Frame Timing.......................................................................................................................................21

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List of Tables
Table 1 Key Specification ...............................................................................................................................................1
Table 2 pin description....................................................................................................................................................6
Table 3 power supply requirement（MIPI mode）........................................................................................................9
Table 4 power supply requirement（DVP mode）........................................................................................................9
Table 5 IO level configuration ......................................................................................................................................10
Table 6 BG0836 PID.....................................................................................................................................................12
Table 7 shadow register update control.........................................................................................................................12
Table 8 mirror control register ......................................................................................................................................13
Table 9 clock definition.................................................................................................................................................14
Table 10 PLL control register........................................................................................................................................15
Table 11 PLL VCO frequency setting up corresponding table......................................................................................15
Table 12 Main System Clock control............................................................................................................................16
Table 13 Control the output format registers ................................................................................................................16
Table 14 Frame rate control register .............................................................................................................................17
Table 15 Exposure control register................................................................................................................................18
Table 16 Analog gain control registers..........................................................................................................................18
Table 17 Digital gain control registers ..........................................................................................................................18
Table 18 BLC control register.......................................................................................................................................19
Table 19 mipi control register .......................................................................................................................................20
Table 20 Adjust the driving ability registers .................................................................................................................21
Table 21 Adjust Pclk phase position .............................................................................................................................21

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PCB design guideline
This chapter presents PCB design rules.
Package diagram
Figure 1 shows BG0836 CSP package diagram, which defines mechanical size and the
optical center. With the chip center（-64.210um，75.495um）, specific content please
refer to the Top View.
Figure 1 Mechanical Drawing

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Pin configuration
1
2
3
4
5
6
7
8
9
10
A
VDDA
VN
PCLK
VSS
D5
D9
VSS
VDA15
D0/DN
0
D1/DP0
B
SDA
VSSD
VSSD
D3
D6
CLKIN
VSSA
HSYNC
/CKN
VSYNC
/CKP
VDDD
C
TRIG
SCL
D2
D4
D7
D8
VDDIO
VSSA
VDD15
D11
D
VSS
VDD15
VP
VDD15
RSTB
VDD15
D10
VDDA
VSSA
E
VSSA
VDDPI
X
PD
VDD15
NC
NC
VDD15
VSS
VDDPI
X
VSSA
F
VDDA
VSSA
VDDA
NC
VSS
VSS
VDD15
VDDA
VSSA
VDDA
Figure 2 Pin configuration shows the pin configuration from top view. Table 2 lists the
pin description.
1
2
3
4
5
6
7
8
9
10
A
VDDA
VN
PCLK
VSS
D5
D9
VSS
VDA15
D0/DN
0
D1/DP0
B
SDA
VSSD
VSSD
D3
D6
CLKIN
VSSA
HSYNC
/CKN
VSYNC
/CKP
VDDD
C
TRIG
SCL
D2
D4
D7
D8
VDDIO
VSSA
VDD15
D11
D
VSS
VDD15
VP
VDD15
RSTB
VDD15
D10
VDDA
VSSA
E
VSSA
VDDPI
X
PD
VDD15
NC
NC
VDD15
VSS
VDDPI
X
VSSA
F
VDDA
VSSA
VDDA
NC
VSS
VSS
VDD15
VDDA
VSSA
VDDA
Figure 2 Pin configuration
Table 2 pin description
(P=Power, G=Ground, D=Digital, A=Analog)
NO
PIN NO
NAME
I/O
TYPE
DESCRIPTION
1
A1
VDDA
-
P
Analog 3.3V power supply
2
A2
VN
-
A
Reference voltage
3
A3
PCLK
O
D
Pixel sync clock
4
A4
VSS
-
G
Digital ground

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5
A5
D5
O
D
Data <5>
6
A6
D9
O
D
Data <9>
7
A7
VSS
-
G
Digital ground
8
A8
VDA15
-
P
Analog 1.5V power supply
9
A9
D0/DN0
O
D
Data <0>/mipi dn0
10
A10
D1/DP0
O
D
Data <1>/mipi dp0
11
B1
SDA
I/O
D
IIC data
12
B2
VSSD
-
G
Digital ground
13
B3
VSSD
-
G
Digital ground
14
B4
D3
O
D
Data <3>
15
B5
D6
O
D
Data <6>
16
B6
CLKIN
I
D
Input clock
17
B7
VSSA
-
G
Analog ground
18
B8
HSYNC/CKN
O
D
Hsync/mipi clkn
19
B9
VSYNC/CKP
O
D
Vsync/mipi clkp
20
B10
VDDD
-
P
Digital 3.3V power supply
21
C1
TRIG
I
D
Trigger pin，pull down actively
22
C2
SCL
I/O
D
IIC clock
23
C3
D2
O
D
Data <2>
24
C4
D4
O
D
Data <4>
25
C5
D7
O
D
Data <7>
26
C6
D8
O
D
Data <8>
27
C7
VDDIO
-
P
IO power supply
28
C8
VSSA
-
G
Analog ground
29
C9
VDD15
-
P
Digital 1.5V power supply
30
C10
D11
O
D
Data <11>
31
D1
VSS
-
G
Digital ground
32
D2
VDD15
-
P
Digital 1.5V power supply
33
D3
VP
-
A
Reference voltage
34
D4
VDD15
-
P
Digital 1.5V power supply
35
D5
RSTB
I
D
Chip rstb pin，Active low
36
D6
VDD15
-
P
Digital 1.5V power supply
37
D8
D10
O
D
Data <10>
38
D9
VDDA
-
P
Analog 3.3V power supply
39
D10
VSSA
-
G
Analog ground
40
E1
VSSA
-
G
Analog ground
41
E2
VDDPIX
-
P
Pixel power supply
42
E3
PD
I
D
Power down pin，pull down actively
43
E4
VDD15
-
P
Digital 1.5V power supply
44
E5
NC
-
-
No connect
45
E6
NC
-
-
No connect
46
E7
VDD15
-
P
Digital 1.5V power supply

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47
E8
VSS
-
G
Digital ground
48
E9
VDDPIX
-
P
Pixel power supply
49
E10
VSSA
-
G
Analog ground
50
F1
VDDA
-
P
Analog 3.3V power supply
51
F2
VSSA
-
G
Analog ground
52
F3
VDDA
-
P
Analog 3.3V power supply
53
F4
NC
-
-
No connect
54
F5
VSS
-
G
Digital ground
55
F6
VSS
-
G
Digital ground
56
F7
VDD15
-
P
Digital 1.5V power supply
57
F8
VDDA
-
P
Analog 3.3V power supply
58
F9
VSSA
-
G
Analog ground
59
F10
VDDA
-
P
Analog 3.3V power supply
Application circuits
The application circuits is recommended in the figures below.
Figure 3 Recommended schematic with MIPI interface

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Figure 4 Recommended schematic with DVP interface
Power supply design
The range of VDDIO is 1.8V~3.3V. 1.8V is recommended.
12V DCDC 3.3V Bead
Bead
VDDA
VDDD
Bead VDDPIX
D3.3V LDO VDDIO
1.5V Bead VDD
LDO
1.8V
Figure 5 Recommend Power Tree（1.8V IO）
The power consumption and requirement peripheral capacitor of each power supply
are listed in the table 3 and table 4.
Table 3 power supply requirement（MIPI mode）
NO
power
supply
Recommended
voltage
Consumption
current
(maximum)
External small capacitance
1
VDDD
3.3V
10mA
0.1uF x 1

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2
VDDA
3.3V
30mA
0.1uF x4
3
VDDPIX
3.3V
10mA
0.1uF x2
4
VDDIO
1.8V~3.3V
5mA
0.1uF x1
5
VDA15
1.5V
20 mA
0.1uF x1
6
VDD
1.5V
50mA
0.1uF x4
Table 4 power supply requirement（DVP mode）
NO
power
supply
Recommended
voltage
Consumption
current
(maximum)
External small capacitance
1
VDDD
3.3V
10mA
0.1uF x 1
2
VDDA
3.3V
30mA
0.1uF x4
3
VDDPIX
3.3V
10mA
0.1uF x2
4
VDDIO
1.8V~3.3V
5mA
0.1uF x1
5
VDA15
1.5V
10 mA
0.1uF x1
6
VDD
1.5V
50mA
0.1uF x4
Notice：
0.1uF capacitors should be mounted as close to power supply pins as possible.
Each power supply needs at least a 10uF capacitor, which is mounted around the
sensor. If conditional, add a large capacitor of 100uF for 3.3V or VDDA. All the GND
pins connect to the common single ground.
It costs lower power consumption using 1.8V VDDIO than using 3.3 V VDDIO.
It is important to note that the configuration is different in two cases, as listed in
Table 5.
Table 5 IO level configuration
Name
Address
Width
function
IO level
configuration
0x005c
3
Bit[2:0]:
IO1.8V: configured to 0x00
IO 3.3V : configured to 0x07
The timing diagram of clock, reset and power supply is shown in the following figure,

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Figure 6 Power-up Sequence
PCB notice
Chips have multiple sets of power supply, VDDD33/VDDIO/VDD are digital power
supply, VDDA33/VDDPIX are analog power supply. Analog power line need to pay
special attention that there must be no digital power and digital signal nearby to avoid
interference.
Power Line and ground line should as wide as possible, in general, the power line
wide should be more than 20MIL, if it is a very long power line，it`s width need to reach
30MIL ~40MIL. Try to use GND to isolate analog power line or copper. If the PCB is
multilayer, it’s inner layer should have independent power layer and independent GND
layer, it is recommended to conduct a small range of copper for each power network,
and then lay GND on the free spare area of the power layer. The distance between
copper of Analog power and digital power must more than 20MIL, preferably use GND
to separate the two power, Analog power and digital power.
The ground net is generally made of copper. It helps to reduce crosstalk if copper
is spread over the TOP and BOTTOM layers. LDO or DC-DC should be placed far away
from the sensor to prevent the power chip from overheating. The MIPI clock line(CP/CN)
and the LVDS signal(D0P/D0N) should be differential pair lines and the differential
impedance is 100ohm. Their length should be same as possible, and the errors
between P & N should be less than 5MIL.
Checklist
（TBD）
Register Slave Interface
I2C Slave Interface
BG0836 is programmablethrough I2C interface with reading slave device address 0x65
and writing slave deviceaddress 0x64.The related IOpin is SCL and SDA. I2C interface
supports a 16-bit register address and 8-bit data message type.
Figure 7 I2C write operation shows example of the write operation (Writing 0x012C
register with 0x56 data). DSP is the master, BG0836 is the slave. The sequence is

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defined as following:
⚫The master sends a start bit to the slave.
⚫The master sends the slave device address (0x64) with write mode.
⚫The slave sends an acknowledge bit to the master to indicate receive its slave
device address.
⚫The master sends 8-bit higher register address (0x01) to the slave.
⚫The slave sends an acknowledge bit to the master.
⚫The master sends 8-bit lower register address (0x2C) to the salve.
⚫The slave sends an acknowledge bit to the master.
⚫The master sends 8-bit register data to the salve.
⚫The slave sends an acknowledge bit to the master.
⚫The master sends a stop bit to the slave.
SCL
SDA
START
0x64 ADDR
ACK
0x2C REG
ACK
0x56 DATA
ACK STOP
0x01 REG
ACK
Figure 7 I2C write operation
Figure 8 I2C read operation shows example of the reading operation (Reading data
from 0x012C register). DSP is the master, BG0836 is the slave. The sequence defined
as following:
⚫The master sends a start bit to the slave.
⚫The master sends the slave device address (0x64) with write mode.
⚫The slave sends an acknowledge bit to the master to indicate receive its slave
device address.
⚫The master sends 8-bit higher register address (0x01) to the slave.
⚫The slave sends an acknowledge bit to the master.
⚫The master sends 8-bit lower register address (0x2C) to the salve.
⚫The slave sends an acknowledge bit to the master.
⚫The master sends 8-bit register data to the salve.
⚫The master sends the slave device address (0x65) with read mode.
⚫The slave sends an acknowledge bit to the master.
⚫The slave sends 8-bit data to the master
⚫The master sends 8-bit register data to the salve.
⚫The master sends a stop bit to the slave.

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SCL
SDA
START
0x64 ADDR
ACK
0x2C REG
ACK
0x65 DATA
ACK
0x56 DATA
ACK
STOP
0x01 REG
STARTACK
Figure 8 I2C read operation
Table 6 BG0836 PID
Name
Address
Width
Function
PID_H
0x0000
8
High 8 bit of BG0836 PID
registers, to identify the chip, the
content is “08”.
PID_L
0x0001
8
Low 8 bit of BG0836 PID
registers, to identify the chip, the
content is “06”.
Shadow register
Some special registers of BG0836 are implemented by the shadow registers.That is to
say, when these registers are written through the I2C, they will not automatically update
immediately. Updating these registers needs special operation, and these registers will
be specially explain later.
Table 7 shadow register update control
Name
Address
Width
Function
Register
update
control
0x001d
2
Bit[1:0]:
0x01:
Making the shadow registers take
effect immediately and break off
the current frame right away, then
restart the next frame.
0x02:
After writing, the shadow register
will take effect at the beginning of
the frame.
Optical Design
Imaging direction
The pixel (0, 0) of BG0836 is near the A10 pin of the package as shown in Figure 1
Mechanical Drawing. The default horizontal readout direction is scanning from A10 to
A1. The default vertical readout direction is scanning from A10 to F10.

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(BG0806 rear view) (0 ,0)
Sensor
Lens
Sense
A1
B1
A2 A10
F10
Figure 9 Imaging a Scene
Mirror function
BG0836 supports row mirror and column mirror process, as shown in Figure 10.
It is important to note that, output sequence and color filter might be changed after
mirror operation. After mirror operation, Color Filter Pattern need to be adjusted.
Specificadjustmentmeasuresare describedin"adjustthe framerateandwide"section.
original Horizontal
mirror Vertical mirror Horizontal & Vertical mirror
Figure 10 mirror function schematic
The register corresponding to Mirror function is the lowest two bits of 0x0020.
Please note that don't change the other bits of the register values. The register has
shadow registers, it need to write 0x02 in to the register to update
Table 8 mirror control register
Name
Address
Width
Function
Readout
control
0x0020
8
Bit[7:2] Reserved
Bit[1] Horizontal mirrored image
control
Bit[0] Vertical mirrored image
control

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Adjust the wide and frame rate
CFA assignment
The pixel array of BG0836 contains 1928Hx1088V active pixel. The color filters
are arranged in the Bayer RGB pattern, as shown in Figure 11. The location of the
pixels (0, 0) correspond to the pixel (0, 0) which is described in Imaging Direction
section.
R G
BG
R G
BG
R G
BG
GR
BG
R G
BG
GR
BG
R G
BG
GR
BG
R G
BG
BLACK PIXELS
BLACK PIXELS
(0,0)
point
Figure 11 Color Filter Arrangements
The calculation of the clock
The definition of the clock
Table 9 clock definition
Name
Sym
Description
计算办法
External clock
Clkin
The chip outside access
the clock
-
Main System
Clock
Mclk
Inside the chip operate
the master clock
Please refer to
chapter <system
main clock >
Pixel output
clock
Pclk
The chip DVP output
pixel clock
Please refer to
<PLL control>

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PLL control
pre-divider
pln_p<5:0>
clkin PFD CP
LPF VCO
vco_fsel_p<1:0>
loop-divider
plm_p<8:0>
pllclk_sel
clkin
fvco
fvco
pln_p+2
plm_p+2
pclk_sel
pclkdiv<2:0>
fpll=fvco
fpll
pclkdiv+2 pixclk
Figure 12 PLL block diagram
The relationship between output Pclk frequency and clkin frequency is :
 󰇛  󰇜 
󰇛  󰇜 󰇛  󰇜
Registers corresponding to PLL are listed in Table 10:
Table 10 PLL control register
Register
Addr
Width
Function
PLM
0x00f3
0x00f4
9
PLM data
PLN
0x00f5
6
PLN data
PCLK_CTRL
0x006d
7
Bit[6] Reserved
Bit[5:4] vco_freq_sel
Bit[2:0] pclkdiv
When you adjust vco oscillation frequency, you need to set vco_freq_sel of PLLCTRL_P. Formula
for vco frequency is

    󰇛  󰇜 󰇛  󰇜

Setting vco_freq_sel according to the following table.
Table 11 PLL VCO frequency setting up corresponding table
vco_freq_sel<1:0>
vco frequency range
00 B
200M ~ 380M
01 B
230M ~ 460M
10 B
360M ~ 600M
11 B
500M ~ 770M
Main System Clock control
Mclk（Main System Clock）can be chosen as Clkin (external clock ) or the frequency
multiplication of Pclk(Pixel output clock).

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Table 12 Main System Clock control
Name
Address
Width
Function
MCLK_CTRL
0x0048
8
Bit[7:4] mclkc
Bit[1] reserved
Bit[0] mclk option:
1: make mclk equal to clkin
0: make mclk equal to the
fractional frequency of pclk,
mean Fmclk = Fpclk/(mclkc+1)。
F indicate the Corresponding to
the clock frequency.
Adjust the size
HSIZE (width) register and VSIZE register (height) control the size of the output images.
HSTART register and VSTART register control the readout start position ,the address
is shown in Table 13.The default of HSIZE is 0x780，The default of VSIZE is 0x438，
the size of the default image is 1920x1080. After HSIZE，VSIZE，HSTART and
VSTART are wrote , 0x001d register need to write 0x01 or 0x02
Table 13 Control the output format registers
Name
Address
Width
Function
HSIZE_H
0x0006
3
Bit[10:8] of Horizontal size
HSIZE_L
0x0007
8
Bit[7:0] of Horizontal size
VSIZE_H
0x0008
3
Bit[10:8] of Vertical size
VSIZE_L
0x0009
8
Bit[7:0] of Vertical size
HSTART_H
0x0002
3
Bit[10:8] of Horizontal start position
HSTART_L
0x0003
8
Bit[7:0] of Horizontal start position
VSTART_H
0x0004
3
Bit[10:8] of Vertical start position
VSTART_L
0x0005
8
Bit[7:0] of Vertical start position
Adjust the frame rate
The waveform of BG0836 Output synchronizing signal is shown as below:
Figure 13 output waveform and frame rate calculation

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In the figure below，
 is the frame time.  is called porch back, it means time
between vsync and the first image data. 
 is called front porch, it means time
between the last image data and invalid vsync. VBLANK and ROWTIME is the name
of BG0836 registers, their relationship as follows：
      󰇛  󰇜   
        
Combined, the frame time formula is:
  󰇛    󰇜   
Registers which control the output frame rate is ROWTIME（line time）and VBLANK
（vertical blanking）, the address is shown below：
Table 14 Frame rate control register
Name
Address
Width
Function
ROWTIME_
H
0x000e
8
Bit[15:8] of Row time control
registers(main clock unit)
ROWTIME_L
0x000f
8
Bit[7:0] of Row time control
registers(main clock unit)
VBLANK_H
0x0021
8
Bit[15:8] of Vertical blanking control
registers(row time unit)
VBLANK_L
0x0022
8
Bit[7:0] of Vertical blanking control
registers(row time unit)
The default value of ROWTIME is 0x12C4（4808）, the default value of VBLANK is
0x0024, according to the above formula，frame time is：
  󰇛   󰇜   
ROWTIME and VBLANK registers are written, 0x001d register need to write 0x01
or 0x02.
Adjust the exposure and gain
Adjust the exposure
The register TEXP and the register TEXP_MCK control exposure time. TEXP is as
row time as a unit，TEXP_MCK is as main clock as a unit. Formula for calculating
exposure time as follow：
  󰇛    󰇜  
Where ROWTIME is the register name. Please refer to the section "adjust the output
frame rate". Texp must be smaller than Tfrm, otherwise you can't output image. TEXP
and TEXP_MCK register address is as shown in the table below:

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Table 15 Exposure control register
Name
Address
Width
Function
TEXP_H
0x000c
8
Bit[15:8] of Exposure length control
register (row as unit)
TEXP_L
0x000d
8
Bit[7:0] of Exposure length control
register (row as unit)
TEXP_MCK_H
0x0026
8
Bit[15:8] of Exposure length control
register (main clock as unit)
TEXP_MCK_L
0x0027
8
Bit[7:0] of Exposure length control
register (main clock as unit)
The default of the TEXP is 0x0032, the default of the TEXP_MCK is 0x0000. If incoming
frequency is 27 MHZ, exposure time is:
  󰇛    󰇜 
TEXP and TEXP_MCK registers are written, 0x001d register need to write 0x01 or
0x02.
Adjust the gain
BG0805 has two stages of gain, including analog gain and digital gain.
The analog gain control register：
Table 16 Analog gain control registers
Name
Address
Width
Function
VREFL
0x00b1
8
Analog gain control
Digital gain can be controlled by the above register is
  󰇛  󰇜

Default  is zero. In normal case, please adjust analog gain by . has
minimum limit practically. Please Insure  is equal or larger than 0x0c；
Digital gain control register is ：
Table 17 Digital gain control registers
Name
Address
Width
Function
DIG_GAIN_H
0x00bc
4
Bit[11:8] of digital gain control
DIG_GAIN_L
0x00bd
8
Bit[7:0] of digital gain control
Digital gain control register is DIG_GAIN, 0 x0200 is 1 times digital gain. That is to say
  .
In conclusion, the overall gain is:
    

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Adjust the gain strategy
The strategy of gain mapping is shown as below. Assuming that gain is total system
gain:
(1) If gain is less than or equal to the maximum limitation of the analog gain, analog
gain is set to gain, and digital gain is set to 1 times.
(2) If gain is greater than the maximum limitation of the analog gain. First, less than the
limit part map to the maximum analog gain, the rest map to digital gain.
(3) The analog gain maximum before and after（vrefh equal to 0x0c and vrefh
greater than 0x0c），There are additional register need linkage to ensure the best
image quality(Refers to vertical grain which under the maximum gain, specific
settings related to frame rate, please consult to FAE or refer to sample code).
(4) Write back to the Sensor internal registers through the I2C.
Black level calibration
BG0836 chip provides black level correction module. Its basic principle is using the
black level reference pixel to correct the effective pixels for black level, to eliminate
circuit, the environment temperature brought the black level drift.
Table 18 BLC control register
Name
Address
Width
Function
BLC_CTRL
0x0120
7
Bit[6:1] Reserved
Bit[0]: BLC enable, valid high 。
DBLC_OB_H
0x0130
4
[11:8] of Object of expected final image,
unsigned.
DBLC_OB_L
0x0131
8
[11:8] of Object of expected final image,
unsigned.
DBLC_LOWER
HI_ADJ
0x0136
8
Adjust the lower bound of convergence
range, unsigned.
DBLC_UPPER
LO_ADJ
0x0137
8
Upper bound of convergence range, lower
bound, unsigned.
DBLC_UPPER
HI_ADJ
0x0138
8
Upper bound of convergence range, higher,
bound, unsigned.
BLC_CTRL is the switch of control for BLCC function；
BLCC target value is adjust by DBLC_OB, It means that expect to get the black level.
after the BLCC completed the operation.
BLC_LOWERHI_ADJ, BLC_UPPERLO_ADJ, DBLC_UPPERHI_ADJ is used to adjust
the rangeof stabilityof thealgorithm. The finalconvergencesignal isas shownin Figure
14 BLC Convergence signal.