Bg BG0836 User manual

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BG0836 1/2.7inch 1080P CMOS
Imaging sensor application note
General Descriptions
BG0836 is a high performance 1/2.7 inch CMOS imaging
sensor with an active-pixel array of 1928H x 1088V.
Features
⚫Support 1-Lane MIPI interface.
⚫Trigger exposure operation: single and multi-
frame.
⚫Auto black level calibration.
⚫Maximum 30 frame per second.
Applications
⚫Senior surveillance
⚫Automobile data recorder
Key Parameter
Table 1 Key Specification
Parameter
Typical Value
Optical format
1/2.7inch
Active pixel array
1928H x1088V
Pixel size
3.00um(H) x
3.00um(V)
Active pixel array Area
5784um x
3264um
Frame rate
30fps@full frame
Color filter array
Bayer RGB
CRA
0°
Shutter Type
Electronic Rolling
Sensitivity@550nm
3.8V/(lux.sec)
Dark current@60⁰C
10mV/s
SNRmax
36dB
Dynamic range
65dB
Output
12-bit DVP
1-Lane MIPI
Power
supply
Digital
1.42V~1.65V
IO
1.7V~3.45V
Analog
3.15V~3.45V
Pixel
3.15V~3.45V
Power Consumption
TBD@30fps
Temperature range
-30 ~70 ⁰C
Package Option
CSP
In the absence of confirmation by device specification sheets, BRIGATES takes no responsibility for any defects that may occur in equipment using any BRIGAGES
device shown in catalogs, data book, etc. Contact BRIGATES in order to obtain the latest device specification before using any BRIGATES device.

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Table of Content
General Descriptions.......................................................................................................................................................1
Features...........................................................................................................................................................................1
Applications ....................................................................................................................................................................1
Key Parameter.................................................................................................................................................................1
PCB design guideline......................................................................................................................................................5
Package diagram .....................................................................................................................................................5
Pin configuration.....................................................................................................................................................6
Application circuits.................................................................................................................................................8
Power supply design ...............................................................................................................................................9
PCB notice ............................................................................................................................................................10
Checklist ...............................................................................................................................................................11
Register Slave Interface ................................................................................................................................................11
I2C Slave Interface................................................................................................................................................11
Shadow register.....................................................................................................................................................12
Optical Design ..............................................................................................................................................................13
Imaging direction ..................................................................................................................................................13
Mirror function......................................................................................................................................................13
Adjust the wide and frame rate .....................................................................................................................................14
CFA assignment ....................................................................................................................................................14
The calculation of the clock..........................................................................................................................................14
The definition of the clock....................................................................................................................................14
PLL control ...................................................................................................................................................................15
Main System Clock control...................................................................................................................................15
Adjust the size.......................................................................................................................................................16
Adjust the frame rate.............................................................................................................................................16
Adjust the exposure and gain ........................................................................................................................................17
Adjust the exposure...............................................................................................................................................17
Adjust the gain ......................................................................................................................................................18
Adjust the gain strategy.........................................................................................................................................19
Black level calibration ..................................................................................................................................................19
MIPI ..............................................................................................................................................................................20
Others............................................................................................................................................................................21
IO adjust the drive ability......................................................................................................................................21
Pixel Clock phase adjustment ...............................................................................................................................21
FQA ..............................................................................................................................................................................22
Revision history ............................................................................................................................................................23

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List of Figures
Figure 1 Mechanical Drawing ........................................................................................................................................5
Figure 2 Pin configuration ..............................................................................................................................................6
Figure 3 Recommended schematic with MIPI interface.................................................................................................8
Figure 4 Recommended schematic with DVP interface..................................................................................................9
Figure 5 Recommend Power Tree（1.8V IO）..............................................................................................................9
Figure 6 Power-up Sequence ........................................................................................................................................10
Figure 7 I2C write operation........................................................................................................................................11
Figure 8 I2C read operation .........................................................................................................................................12
Figure 9 Imaging a Scene.............................................................................................................................................13
Figure 10 mirror function schematic.............................................................................................................................13
Figure 11 Color Filter Arrangements ............................................................................................................................14
Figure 12 PLL block diagram .......................................................................................................................................15
Figure 13 output waveform and frame rate calculation ................................................................................................16
Figure 14 BLC Convergence signal..............................................................................................................................20
Figure 15 raw10/raw12 Data output sequence..............................................................................................................21
Figure 16 Mipi Frame Timing.......................................................................................................................................21

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List of Tables
Table 1 Key Specification ...............................................................................................................................................1
Table 2 pin description....................................................................................................................................................6
Table 3 power supply requirement（MIPI mode）........................................................................................................9
Table 4 power supply requirement（DVP mode）........................................................................................................9
Table 5 IO level configuration ......................................................................................................................................10
Table 6 BG0836 PID.....................................................................................................................................................12
Table 7 shadow register update control.........................................................................................................................12
Table 8 mirror control register ......................................................................................................................................13
Table 9 clock definition.................................................................................................................................................14
Table 10 PLL control register........................................................................................................................................15
Table 11 PLL VCO frequency setting up corresponding table......................................................................................15
Table 12 Main System Clock control............................................................................................................................16
Table 13 Control the output format registers ................................................................................................................16
Table 14 Frame rate control register .............................................................................................................................17
Table 15 Exposure control register................................................................................................................................18
Table 16 Analog gain control registers..........................................................................................................................18
Table 17 Digital gain control registers ..........................................................................................................................18
Table 18 BLC control register.......................................................................................................................................19
Table 19 mipi control register .......................................................................................................................................20
Table 20 Adjust the driving ability registers .................................................................................................................21
Table 21 Adjust Pclk phase position .............................................................................................................................21

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PCB design guideline
This chapter presents PCB design rules.
Package diagram
Figure 1 shows BG0836 CSP package diagram, which defines mechanical size and the
optical center. With the chip center（-64.210um，75.495um）, specific content please
refer to the Top View.
Figure 1 Mechanical Drawing

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Pin configuration
1
2
3
4
5
6
7
8
9
10
A
VDDA
VN
PCLK
VSS
D5
D9
VSS
VDA15
D0/DN
0
D1/DP0
B
SDA
VSSD
VSSD
D3
D6
CLKIN
VSSA
HSYNC
/CKN
VSYNC
/CKP
VDDD
C
TRIG
SCL
D2
D4
D7
D8
VDDIO
VSSA
VDD15
D11
D
VSS
VDD15
VP
VDD15
RSTB
VDD15
D10
VDDA
VSSA
E
VSSA
VDDPI
X
PD
VDD15
NC
NC
VDD15
VSS
VDDPI
X
VSSA
F
VDDA
VSSA
VDDA
NC
VSS
VSS
VDD15
VDDA
VSSA
VDDA
Figure 2 Pin configuration shows the pin configuration from top view. Table 2 lists the
pin description.
1
2
3
4
5
6
7
8
9
10
A
VDDA
VN
PCLK
VSS
D5
D9
VSS
VDA15
D0/DN
0
D1/DP0
B
SDA
VSSD
VSSD
D3
D6
CLKIN
VSSA
HSYNC
/CKN
VSYNC
/CKP
VDDD
C
TRIG
SCL
D2
D4
D7
D8
VDDIO
VSSA
VDD15
D11
D
VSS
VDD15
VP
VDD15
RSTB
VDD15
D10
VDDA
VSSA
E
VSSA
VDDPI
X
PD
VDD15
NC
NC
VDD15
VSS
VDDPI
X
VSSA
F
VDDA
VSSA
VDDA
NC
VSS
VSS
VDD15
VDDA
VSSA
VDDA
Figure 2 Pin configuration
Table 2 pin description
(P=Power, G=Ground, D=Digital, A=Analog)
NO
PIN NO
NAME
I/O
TYPE
DESCRIPTION
1
A1
VDDA
-
P
Analog 3.3V power supply
2
A2
VN
-
A
Reference voltage
3
A3
PCLK
O
D
Pixel sync clock
4
A4
VSS
-
G
Digital ground

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5
A5
D5
O
D
Data <5>
6
A6
D9
O
D
Data <9>
7
A7
VSS
-
G
Digital ground
8
A8
VDA15
-
P
Analog 1.5V power supply
9
A9
D0/DN0
O
D
Data <0>/mipi dn0
10
A10
D1/DP0
O
D
Data <1>/mipi dp0
11
B1
SDA
I/O
D
IIC data
12
B2
VSSD
-
G
Digital ground
13
B3
VSSD
-
G
Digital ground
14
B4
D3
O
D
Data <3>
15
B5
D6
O
D
Data <6>
16
B6
CLKIN
I
D
Input clock
17
B7
VSSA
-
G
Analog ground
18
B8
HSYNC/CKN
O
D
Hsync/mipi clkn
19
B9
VSYNC/CKP
O
D
Vsync/mipi clkp
20
B10
VDDD
-
P
Digital 3.3V power supply
21
C1
TRIG
I
D
Trigger pin，pull down actively
22
C2
SCL
I/O
D
IIC clock
23
C3
D2
O
D
Data <2>
24
C4
D4
O
D
Data <4>
25
C5
D7
O
D
Data <7>
26
C6
D8
O
D
Data <8>
27
C7
VDDIO
-
P
IO power supply
28
C8
VSSA
-
G
Analog ground
29
C9
VDD15
-
P
Digital 1.5V power supply
30
C10
D11
O
D
Data <11>
31
D1
VSS
-
G
Digital ground
32
D2
VDD15
-
P
Digital 1.5V power supply
33
D3
VP
-
A
Reference voltage
34
D4
VDD15
-
P
Digital 1.5V power supply
35
D5
RSTB
I
D
Chip rstb pin，Active low
36
D6
VDD15
-
P
Digital 1.5V power supply
37
D8
D10
O
D
Data <10>
38
D9
VDDA
-
P
Analog 3.3V power supply
39
D10
VSSA
-
G
Analog ground
40
E1
VSSA
-
G
Analog ground
41
E2
VDDPIX
-
P
Pixel power supply
42
E3
PD
I
D
Power down pin，pull down actively
43
E4
VDD15
-
P
Digital 1.5V power supply
44
E5
NC
-
-
No connect
45
E6
NC
-
-
No connect
46
E7
VDD15
-
P
Digital 1.5V power supply

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47
E8
VSS
-
G
Digital ground
48
E9
VDDPIX
-
P
Pixel power supply
49
E10
VSSA
-
G
Analog ground
50
F1
VDDA
-
P
Analog 3.3V power supply
51
F2
VSSA
-
G
Analog ground
52
F3
VDDA
-
P
Analog 3.3V power supply
53
F4
NC
-
-
No connect
54
F5
VSS
-
G
Digital ground
55
F6
VSS
-
G
Digital ground
56
F7
VDD15
-
P
Digital 1.5V power supply
57
F8
VDDA
-
P
Analog 3.3V power supply
58
F9
VSSA
-
G
Analog ground
59
F10
VDDA
-
P
Analog 3.3V power supply
Application circuits
The application circuits is recommended in the figures below.
Figure 3 Recommended schematic with MIPI interface

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Figure 4 Recommended schematic with DVP interface
Power supply design
The range of VDDIO is 1.8V~3.3V. 1.8V is recommended.
12V DCDC 3.3V Bead
Bead
VDDA
VDDD
Bead VDDPIX
D3.3V LDO VDDIO
1.5V Bead VDD
LDO
1.8V
Figure 5 Recommend Power Tree（1.8V IO）
The power consumption and requirement peripheral capacitor of each power supply
are listed in the table 3 and table 4.
Table 3 power supply requirement（MIPI mode）
NO
power
supply
Recommended
voltage
Consumption
current
(maximum)
External small capacitance
1
VDDD
3.3V
10mA
0.1uF x 1

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2
VDDA
3.3V
30mA
0.1uF x4
3
VDDPIX
3.3V
10mA
0.1uF x2
4
VDDIO
1.8V~3.3V
5mA
0.1uF x1
5
VDA15
1.5V
20 mA
0.1uF x1
6
VDD
1.5V
50mA
0.1uF x4
Table 4 power supply requirement（DVP mode）
NO
power
supply
Recommended
voltage
Consumption
current
(maximum)
External small capacitance
1
VDDD
3.3V
10mA
0.1uF x 1
2
VDDA
3.3V
30mA
0.1uF x4
3
VDDPIX
3.3V
10mA
0.1uF x2
4
VDDIO
1.8V~3.3V
5mA
0.1uF x1
5
VDA15
1.5V
10 mA
0.1uF x1
6
VDD
1.5V
50mA
0.1uF x4
Notice：
0.1uF capacitors should be mounted as close to power supply pins as possible.
Each power supply needs at least a 10uF capacitor, which is mounted around the
sensor. If conditional, add a large capacitor of 100uF for 3.3V or VDDA. All the GND
pins connect to the common single ground.
It costs lower power consumption using 1.8V VDDIO than using 3.3 V VDDIO.
It is important to note that the configuration is different in two cases, as listed in
Table 5.
Table 5 IO level configuration
Name
Address
Width
function
IO level
configuration
0x005c
3
Bit[2:0]:
IO1.8V: configured to 0x00
IO 3.3V : configured to 0x07
The timing diagram of clock, reset and power supply is shown in the following figure,