Burr-Brown Corporation SpeedPLUS 165MSPS User manual

DAC902
DAC902
12-Bit, 165MSPS
DIGITAL-TO-ANALOG CONVERTER
FEATURES
●SINGLE +5V OR +3V OPERATION
● HIGH SFDR: 5MHz Output at 100MSPS: 67dBc
●LOW GLITCH: 3pV-s
●LOW POWER: 170mW at +5V
●INTERNAL REFERENCE:
Optional Ext. Reference
Adjustable Full-Scale Range
Multiplying Option
APPLICATIONS
●COMMUNICATION TRANSMIT CHANNELS:
WLL, Cellular Base Station
Digital Microwave Links
Cable Modems
●WAVEFORM GENERATION:
Direct Digital Synthesis (DDS)
Arbitrary Waveform Generation (ARB)
●MEDICAL/ULTRASOUND
●HIGH-SPEED INSTRUMENTATION AND CON-
TROL
●VIDEO, DIGITAL TV
DESCRIPTION
The DAC902 is a high-speed, Digital-to-Analog Converter (DAC)
offering a 12-bit resolution option within the SpeedPlus Family of
high-performance converters. Featuring pin compatibility among
family members, the DAC908, DAC900, and DAC904 provide a
component selection option to an 8-, 10-, and 14-bit resolution,
respectively. All models within this family of DACs support update
rates in excess of 165MSPS with excellent dynamic performance,
and are especially suited to fulfill the demands of a variety of
applications.
The advanced segmentation architecture of the DAC902 is opti-
mized to provide a high Spurious-Free Dynamic Range (SFDR) for
single-tone, as well as for multi-tone signals—essential when used
for the transmit signal path of communication systems.
The DAC902 has a high impedance (200kΩ) current output with a
nominal range of 20mA and an output compliance of up to 1.25V.
The differential outputs allow for both a differential or single-
ended analog signal interface. The close matching of the current
outputs ensures superior dynamic performance in the differential
configuration, which can be implemented with a transformer.
Utilizing a small geometry CMOS process, the monolithic DAC902
can be operated on a wide, single-supply range of +2.7V to +5.5V.
Its low power consumption allows for use in portable and battery-
operated systems. Further optimization can be realized by lowering
the output current with the adjustable full-scale option.
For noncontinuous operation of the DAC902, a power-down mode
results in only 45mW of standby power.
The DAC902 comes with an integrated 1.24V bandgap reference
and edge-triggered input latches, offering a complete converter
solution. Both +3V and +5V CMOS logic families can be inter-
faced to the DAC902.
The reference structure of the DAC902 allows for additional
flexibility by utilizing the on-chip reference, or applying an exter-
nal reference. The full-scale output current can be adjusted over a
span of 2mA to 20mA, with one external resistor, while maintain-
ing the specified dynamic performance.
The DAC902 is available in the SO-28 and TSSOP-28 packages.
Current
Sources
LSB
Switches
Segmented
Switches
+1.24V Ref. Latches
12-Bit Data Input
D11...D0
DAC902
FSA
BW +V
D
+V
A
AGND CLK DGND
REF
IN
INT/EXT
I
OUT
I
OUT
BYP
PD
DAC902
SBAS094B – MAY 2002
www.ti.com
Copyright © 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TM
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

DAC902
2SBAS094B
ELECTRICAL CHARACTERISTICS
At TA= full specified temperature range, +VA= +5V, +VD= +5V, differential transformer coupled output, 50Ωdoubly terminated, unless otherwise specified.
DAC902U/E
PARAMETER CONDITIONS MIN TYP MAX UNITS
RESOLUTION 12 Bits
OUTPUT UPDATE RATE 2.7V to 3.3V 125 165 MSPS
Output Update Rate (fCLOCK) 4.5V to 5.5V 165 200 MSPS
Full Specified Temperature Range, Operating Ambient, TA–40 +85 °C
STATIC ACCURACY(1) TA= +25°C
Differential Nonlinearity (DNL) fCLOCK = 25MSPS, fOUT = 1.0MHz –1.75 ±0.5 +1.75 LSB
Integral Nonlinearity (INL) –2.5 ±1.0 +2.5 LSB
DYNAMIC PERFORMANCE TA= +25°C
Spurious-Free Dynamic Range (SFDR) To Nyquist
fOUT = 1MHz, fCLOCK = 25MSPS 71 77 dBc
fOUT = 2.1MHz, fCLOCK = 50MSPS 75 dBc
fOUT = 5.04MHz, fCLOCK = 50MSPS 68 dBc
fOUT = 5.04MHz, fCLOCK = 100MSPS 67 dBc
fOUT = 20.2MHz, fCLOCK = 100MSPS 61 dBc
fOUT = 25.3MHz, fCLOCK = 125MSPS 61 dBc
fOUT = 41.5MHz, fCLOCK = 125MSPS 57 dBc
fOUT = 27.4MHz, fCLOCK = 165MSPS 60 dBc
fOUT = 54.8MHz, fCLOCK = 165MSPS 53 dBc
Spurious-Free Dynamic Range within a Window
fOUT = 5.04MHz, fCLOCK = 50MSPS 2MHz Span 80 dBc
fOUT = 5.04MHz, fCLOCK = 100MSPS 4MHz Span 80 dBc
Total Harmonic Distortion (THD)
fOUT = 2.1MHz, fCLOCK = 50MSPS –74 dBc
fOUT = 2.1MHz, fCLOCK = 125MSPS –75 dBc
Two Tone
f
OUT1
= 13.5MHz, f
OUT2
= 14.5MHz, f
CLOCK
= 100MSPS 64 dBc
ABSOLUTE MAXIMUM RATINGS
PACKAGE SPECIFIED
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER(1) MEDIA
DAC902U SO-28 217 –40°C to +85°C DAC902U DAC902U Rails
"""""DAC902U/1K Tape and Reel
DAC902E TSSOP-28 360 –40°C to +85°C DAC902E DAC902E Rails
"""""DAC902E/2K5 Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of “DAC902E/2K5”will get a single 2500-piece Tape and Reel.
PACKAGE/ORDERING INFORMATION
+VA to AGND ........................................................................ –0.3V to +6V
+VD to DGND ........................................................................ –0.3V to +6V
AGND to DGND................................................................. –0.3V to +0.3V
+VAto +VD............................................................................... –6V to +6V
CLK, PD to DGND ..................................................... –0.3V to VD+ 0.3V
D0-D11 to DGND ....................................................... –0.3V to VD+ 0.3V
IOUT, IOUT to AGND........................................................ –1V to VA+ 0.3V
BW, BYP to AGND..................................................... –0.3V to VA+ 0.3V
REFIN, FSA to AGND ................................................. –0.3V to VA+ 0.3V
INT/EXT to AGND ...................................................... –0.3V to VA+ 0.3V
Junction Temperature.................................................................... +150°C
Case Temperature......................................................................... +100°C
Storage Temperature .................................................................... +125°C
DEMO BOARD
PRODUCT ORDERING NUMBER COMMENT
DAC902U DEM-DAC90xU
Populated evaluation board without the DAC. Order sample of desired DAC90x model separately.
DAC902E DEM-DAC902E Populated evaluation board including the DAC902E.
DEMO BOARD ORDERING INFORMATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

DAC902 3
SBAS094B
DAC902U/E
PARAMETER CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS (Cont.)
At TA= full specified temperature range, +VA= +5V, +VD= +5V, differential transformer coupled output, 50Ωdoubly terminated, unless otherwise specified.
DYNAMIC PERFORMANCE (Cont.)
Output Settling Time(2) to 0.1% 30 ns
Output Rise Time(2) 10% to 90% 2 ns
Output Fall Time(2) 10% to 90% 2 ns
Glitch Impulse 3pV-s
DC-ACCURACY
Full-Scale Output Range(3)(FSR) All Bits High, IOUT 2.0 20.0 mA
Output Compliance Range –1.0 +1.25 V
Gain Error With Internal Reference –10 ±1 +10 %FSR
Gain Error With External Reference –10 ±2 +10 %FSR
Gain Drift With Internal Reference ±120 ppmFSR/°C
Offset Error With Internal Reference –0.025 +0.025 %FSR
Offset Drift With Internal Reference ±0.1 ppmFSR/°C
Power-Supply Rejection, +VA–0.2 +0.2 %FSR/V
Power-Supply Rejection, +VD–0.025 +0.025 %FSR/V
Output Noise IOUT = 20mA, RLOAD = 50Ω50 pA/√Hz
Output Resistance 200 kΩ
Output Capacitance IOUT, IOUT to Ground 12 pF
REFERENCE
Reference Voltage +1.24 V
Reference Tolerance ±5%
Reference Voltage Drift ±50 ppmFSR/°C
Reference Output Current 10 µA
Reference Input Resistance 1MΩ
Reference Input Compliance Range 0.1 1.25 V
Reference Small-Signal Bandwidth(4) 1.3 MHz
DIGITAL INPUTS
Logic Coding Straight Binary
Latch Command Rising Edge of Clock
Logic High Voltage, VIH +VD= +5V 3.5 5 V
Logic Low Voltage, VIL +VD= +5V 0 1.2 V
Logic High Voltage, VIH +VD= +3V 2 3 V
Logic Low Voltage, VIL +VD= +3V 0 0.8 V
Logic High Current,IIH(5) +VD= +5V ±20 µA
Logic Low Current, IIL +VD= +5V ±20 µA
Input Capacitance 5pF
POWER SUPPLY
Supply Voltages
+VA+2.7 +5 +5.5 V
+VD+2.7 +5 +5.5 V
Supply Current(6)
IVA 24 30 mA
IVA, Power-Down Mode 1.1 2 mA
IVD 815mA
Power Dissipation +5V, IOUT = 20mA 170 230 mW
+3V, IOUT = 2mA 50 mW
Power Dissipation, Power-Down Mode 45 mW
Thermal Resistance,
θ
JA
SO-28 75 °C/W
TSSOP-28 50 °C/W
NOTES: (1) At output IOUT, while driving a virtual ground. (2) Measured single-ended into 50ΩLoad. (3) Nominal full-scale output current is 32 •IREF; see Application
Section for details. (4) Reference bandwidth depends on size of external capacitor at the BW pin and signal level. (5) Typically 45µA for the PD pin, which has an
internal pull-down resistor. (6) Measured at fCLOCK = 50MSPS and fOUT = 1.0MHz.

DAC902
4SBAS094B
PIN DESIGNATOR DESCRIPTION
1 Bit 1 Data Bit 1 (D11), MSB
2 Bit 2 Data Bit 2 (D10)
3 Bit 3 Data Bit 3 (D9)
4 Bit 4 Data Bit 4 (D8)
5 Bit 5 Data Bit 5 (D7)
6 Bit 6 Data Bit 6 (D6)
7 Bit 7 Data Bit 7 (D5)
8 Bit 8 Data Bit 8 (D4)
9 Bit 9 Data Bit 9 (D3)
10 Bit 10 Data Bit 10 (D2)
11 Bit 11 Data Bit 11 (D1)
12 Bit 12 Data Bit 12 (D0), LSB
13 NC No Connection
14 NC No Connection
15 PD Power Down, Control Input; Active
HIGH.
Contains internal pull-down circuit;
may be left unconnected if not used.
16 INT/EXT Reference Select Pin; Internal ( = 0) or
External ( = 1) Reference Operation.
17 REFIN Reference Input/Ouput. See Applica-
tions section for further details.
18 FSA Full-Scale Output Adjust
19 BW Bandwidth/Noise Reduction Pin:
Bypass with 0.1µF to +VAfor Optimum
Performance.
20 AGND Analog Ground
21 IOUT Complementary DAC Current Output
22 IOUT DAC Current Output
23 BYP Bypass Node: Use 0.1µF to AGND
24 +VAAnalog Supply Voltage, 2.7V to 5.5V
25 NC No Connection
26 DGND Digital Ground
27 +VDDigital Supply Voltage, 2.7V to 5.5V
28 CLK Clock Input
PIN DESCRIPTIONSPIN CONFIGURATION
Top View SO, TSSOP
TYPICAL CONNECTION CIRCUIT
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
NC
NC
CLK
+V
D
DGND
NC
+V
A
BYP
I
OUT
I
OUT
AGND
BW
FSA
REF
IN
INT/EXT
PD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DAC902
Current
Sources
LSB
Switches
Segmented
MSB
Switches
+1.24V Ref. Latches
12-Bit Data Input
D11.......D0
DAC902
FSA
BW +V
D
+V
A
R
SET
AGND CLK DGND
REF
IN
0.1µF
INT/EXT
I
OUT
I
OUT
BYP
PD
20pF
50Ω50Ω20pF
1:1
0.1µF
0.1µF
+5V +5V

DAC902 5
SBAS094B
TIMING DIAGRAM
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t1Clock Pulse HIGH Time 3.0 ns
t2Clock Pulse LOW Time 3.0 ns
tSData Setup Time 1.0 ns
tHData Hold Time 1.5 ns
tPD Propagation Delay Time 1 ns
tSET Output Settling Time to 0.1% 30.0 ns
t2 t1
tStH
tSET tPD
CLOCK
D13 D0
Iout or
Iout
Data Changes Stable Valid Data Data Changes