Bustec ProDAQ 3424 User manual

USER MANUAL
ProDAQ Data Acquisition Function Cards
ProDAQ 3424 8-Channel, 24-Bit,
Sigma-Delta ADC Function Card
PUBLICATION NUMBER: 3424-XX-UM-0010
Copyright, © 2014, Bustec Production, Ltd.
Bustec Production, Ltd.
Bustec House, Shannon Business Park, Shannon, Co. Clare, Ireland
Tel: +353 (0) 61 707100, FAX: +353 (0) 61 707106

PROPRIETARY NOTICE
This document and the technical data herein disclosed, are proprietary to Bustec
Production Ltd., and shall not, without express written permission of Bustec
Production Ltd, be used, in whole or in part to solicit quotations from a competitive
source or used for manufacture by anyone other than Bustec Production Ltd. The
information herein has been developed at private expense, and may only be used for
operation and maintenance reference purposes or for purposes of engineering
evaluation and incorporation into technical specifications and other documents,
which specify procurement of products from Bustec Production Ltd.. This document
is subject to change without further notification. Bustec Production Ltd. Reserve the
right to change both the hardware and software described herein.

ProDAQ 3424 Function Card User Manual 3424-XX-UM
Copyright, 1998-2005 Bustec Production Ltd. Page 3 of 56
Table of Contents
1. INTRODUCTION...........................................................................................................7
2. INSTALLATION ............................................................................................................8
2.1. Unpacking and Inspection....................................................................................8
2.2. Reshipment Instructions.......................................................................................8
2.3. Preparing the ProDAQ Module.............................................................................9
2.4. Installing a ProDAQ Function Card.....................................................................10
2.5. Removing a ProDAQ Function Card...................................................................12
3. THEORY OF OPERATION .........................................................................................13
3.1. Analog Front-End Circuitry.................................................................................13
3.1.1. Analog Front-End general description..........................................................13
3.1.2. ICP sensor conditioning...............................................................................14
3.1.3. TEDS reader interface.................................................................................14
3.2. Digital Front-End Circuitry ..................................................................................15
3.2.1. Motherboard
function card interface........................................................15
3.2.2. Front panel digital signals ............................................................................15
3.2.3. Local synchronization link............................................................................16
3.3. Data Acquisition .................................................................................................16
3.3.1. Data Acquisition modes ...............................................................................17
3.3.2. Data storage and readout............................................................................18
3.3.3. FIR filters and decimation ............................................................................19
3.3.4. Sampling settings.........................................................................................19
3.3.5. Input Trigger ................................................................................................21
3.3.6. Output Trigger, Direct Interrupt and Direct Error..........................................22
3.3.7. Analog Trigger .............................................................................................24
3.3.8. Analog channel correction............................................................................25
3.3.9. Multiple cards configuration .........................................................................25
4. FRONT PANEL CONNECTORS.................................................................................29
5. REGISTER DESCRIPTION.........................................................................................31
5.1. FCID –Function Card ID Register......................................................................32
5.2. FCVER –Function Card Version Register..........................................................32
5.3. FCCRS –Function Card Control and Status Register........................................32
5.4. MODE1 –Mode 1 Register.................................................................................34
5.5. MODE2 –Mode 2 Register.................................................................................35
5.6. OTRI_CFG –Output Trigger Configuration Register..........................................38
5.7. ITRI_CFG –Input Trigger Configuration Register ..............................................40
5.8. FIFO_CTRL –FIFO Control Register.................................................................41
5.9. FIFO_WRL –FIFO Write Low Register..............................................................42
5.10. FIFO_WRH –FIFO Write High Register............................................................43
5.11. PRET_NOS –Pre-Trigger Number of Scans Register.......................................43
5.12. POSTT_NOSL –Post-Trigger Number of Scans Low Register..........................43
5.13. POSTT_NOSH –Post Trigger Number of Scans High Register.........................43

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5.14. AT_THR_SIGERR –Analog Trigger Threshold / Signal Error Register..............44
5.15. AT_CTRL –Analog Trigger Control Register .....................................................44
5.16. CHNxCFG –Channel x Configuration Register..................................................45
5.17. DDS_WX –DDS Word Register ........................................................................46
5.18. DAC_DATA –DAC Data Register......................................................................47
5.19. DAC_ADDR –DAC Address Register................................................................47
5.20. TEDS_ACC –TEDS Access Register................................................................48
5.21. GCOEFL –Gain correction coefficient write register, bits 15..0..........................49
5.22. GCOEFH –Gain correction coefficient write register, bits 23..16 and address ..49
5.23. EPD –EEPROM Data Register..........................................................................49
5.24. EPC –EEPROM Control Register......................................................................50
5.25. FCSUB –Function Card Sub-Type Register......................................................51
5.26. FCSERH –Function Card Serial Number High Register....................................51
5.27. FCSERL –Function Card Serial Number Low Register .....................................52
6. TECHNICAL SPECIFICATION ...................................................................................53
7. THE VXIPLUG&PLAY DRIVER ..................................................................................55
8. PROGRAMMING THE PRODAQ 3424.......................................................................55

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Table of figures
Figure 1 –Removing the ProDAQ module cover.................................................................9
Figure 2 –The ProDAQ module assembly .........................................................................11
Figure 3 –Simplified block diagram of 3424 function card..................................................13
Figure 4 –Configuration of analog front-end circuitry (single channel) of the 3424 card.....14
Figure 5 –ADC clock configuration.....................................................................................20
Figure 6 –Input Trigger configuration scheme ...................................................................21
Figure 7 –Examples of the Input Trigger configuration ......................................................22
Figure 8 –Output Trigger, Direct Interrupt and Direct Error configuration scheme.............23
Figure 9 –Analog Trigger modes explanation ....................................................................24
Figure 10 –The series of the pulses on SYNC/TRIG signal...............................................27
Figure 11 –Multiple boards link scheme.............................................................................28
Figure 12 –Front panel connectors layout..........................................................................29

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Reference Documents
Title
Number
ProDAQ 3120 User Manual
3120-XX-UM
ProDAQ 3150 User Manual
3150-XX-UM
Glossary
ADC
:
Analog-to-Digital Converter
CRD
:
Current Regulator Diode
DA
:
Data Acquisition
DAC
:
Digital-to-Analog Converter
DDS
:
Direct Digital Synthesis
DTC
:
Discharge Time Constant
ECL
:
Emitter-Coupled Logic
FIR
:
Finite Impulse Response digital filter
FPGA
:
Field Programmable Gate Array
H
:
State of the bit(s) defined by hardware (in register description)
ICP
:
Integrated Circuit Piezoelectric
LED
:
Light Emitting Diode
LVDS
:
Low Voltage Differential Signal(ing)
PCB
:
Printed Circuit Board
PGA
:
Programmable Gain Amplifier
PLL
:
Phase-Locked Loop
RO
:
Read-only access to register
R/W
:
Read/Write access to register
R/WSC
:
Read/Write access to register, Self-Clear after operation finished
TEDS
:
Transducer Electronic Data Sheet
VREF
:
Voltage Reference
VXI
:
VME eXtensions for Instrumentation
WO
:
Write-only access to register

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1.Introduction
The ProDAQ 3424 function card is an 8-channel, 24-bit Sigma-Delta Analog-to-Digital converter
function card. It is an add-on card to use together with ProDAQ 3120 and 3150 motherboards.
It provides the following features:
8 analog channels of simultaneous sampling with 24-bit resolution
Differential and single-ended analog input configuration
Max. Input Range 10V
Programmable gains of 1, 2, 5, 10, 20, 50, 100, 200, 500 and 1000
DC/AC coupling
Variable sampling clock with a maximum 216 kHz output word rate
Software selectable x10 and x100 decimation for output word rate as low as 200 Hz
On-board FIFO of 64 ksamples
Possibility of multiple 3424 cards synchronization (Master/Slave approach)
ICP® sensor conditioning
IEEE 1451.4 (TEDS) Smart Transducer Interface support

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2.Installation
2.1. Unpacking and Inspection
The ProDAQ module is shipped in an antistatic package to prevent any damage from electrostatic
discharge (ESD). Proper ESD handling procedures must always be used when packing, unpacking
or installing any ProDAQ module, ProDAQ plug-in module or ProDAQ function card:
Ground yourself via a grounding strap or similar, e.g. by holding to a grounded object.
Discharge the package by touching it to a grounded object, e.g. a metal part of your VXIbus
chassis, before removing the module from the package.
Remove the ProDAQ module from its carton, preserving the factory packaging as much as
possible.
Inspect the ProDAQ module for any defect or damage. Immediately notify the carrier if any
damage is apparent.
2.2. Reshipment Instructions
Use the original packing material when returning a ProDAQ module to Bustec Production Ltd. for
calibration or servicing. The original shipping carton and the instrument's plastic foam will provide
the necessary support for safe reshipment.
If the original anti-static packing material is unavailable, wrap the ProDAQ module in anti-static
plastic sheeting and use plastic spray foam to surround and protect the instrument. Reship in either
the original or new shipping carton.

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2.3. Preparing the ProDAQ Module
To install a ProDAQ function card into one of the ProDAQ motherboards, you need to remove the
module’s top cover:
1 - Module Cover
2 - Cover Screws
3 - Cover Hooks
Figure 1 –Removing the ProDAQ module cover
To remove the top cover, remove the one countersunk screw in the back and the two panhead
screws towards the front panel (), that hold the cover in place. Remove the cover by sliding it out
of its position towards the VXIbus connectors and up. Take special care about the hooks ()
holding it in place. Try not to lift the cover straight up. See Figure 1 for the location of the screws.
To re-install the cover, slide it back into its position by placing the small hooks over their holes and
moving the cover down and forward. Secure the top cover using two panhead screws and one
countersunk screw ().

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2.4. Installing a ProDAQ Function Card
The single-width ProDAQ function cards are arranged inside the ProDAQ module in four stacks of
two cards each. The double-width ProDAQ function cards are arranged inside the ProDAQ module
in two stacks of two cards each. The function cards are mounted face down, e.g. the front-panel
connectors as well as the motherboard connectors are underneath the PCB. Single-width and
double-width ProDAQ function cards can be mixed in the ProDAQ module. The 3424 function card
is a double-width card.
To install a single-width ProDAQ function card in any of the possible positions, use the following
procedure (See Figure 2 for reference):
Remove the top cover of the module as described earlier in this chapter (Fig. 2, Pos. 1).
Remove all screws on the front-panel holding installed function cards or double filler
panels in place (Fig. 2, Pos. 2). Screws holding single filler panels don't need to be
removed.
Remove the two panhead screws that mount the front panel to the modules bottom cover
(Fig. 2, Pos. 6).
Please take special care of the module handles and the rings (Fig. 2, Pos. 3 and 4), which
are also fixed by those screws. The mounting angle (Fig. 2, Pos. 5) stays fixed to the front
panel.
Remove the front panel by moving it forward carefully so as to avoid bending the installed
function cards.
Choose the stack and position (lower or upper) where you want to mount the function
card. If the stack, in which the function card should be installed, is covered by a double
filler panel, you have to remove it before installing the function card.
Remove the three 2.5mm panhead screws and the crinkle washers from the stack's
standoffs (Fig. 2, Pos. 9 and 10 for example).
If you want to install a function card in the upper position of a stack without having a
function card in the lower position, you need to mount both spacers (Fig. 3, Pos. 11) on
each standoff. If the stack is already populated with a function card in the lower position,
mount only the bigger spacer (Fig. 2, Pos. 8) onto each standoff.
Place a bayonet (supplied) on each standoff. Align the function card over these and slide
carefully down. The function card should be held parallel to the modules bottom cover all
the time during its way down.
Fix the function card by mounting the three 2.5mm panhead screws and the crinkle
washers onto each standoff. If you install a function card in the lower position of a stack,
you need first to mount both spacers (Fig. 2, Pos. 11) onto each standoff.
Re-mount the modules front-panel. If there is only one function card mounted in a stack,
cover the remaining opening in the front panel by a single filler panel.
Re-mount the modules top cover.
Adjust the procedure respectively for a double-width ProDAQ function card.

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2
10
9
8
7
11
1
3
5
6
4
1 - 2.5mm Panhead Screws
2 - 2.5mm Panhead Screws
3 - Module Handle
4 - Ring
5 - Mounting Angle
6 - 2.5mm Panhead Screws
7 - Standoff
8 - Spacer
9 - Crinkle Washer
10 - 2.5mm Panhead Screw
11 - 2mm Spacer
Figure 2 –The ProDAQ module assembly

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2.5. Removing a ProDAQ Function Card
Removing a ProDAQ function card is exactly the reverse operation then installing it. After removing
the top cover and the front panel as described previously, remove the three roundhead screws that
fix the function card(s) on the standoffs.
Take special care when removing the function card(s) not to bend the motherboard connectors.
After removing the function card(s), install the correct combination of spacers on the standoffs. If a
stack is populated with only one function card, each of the standoffs needs to be mounted with both
spacers to cover the distance between the cards as well as the PCB thickness of the missing card.
If a stack is populated with two function cards, only the bigger spacer must be mounted.
Fix any remaining function cards again by mounting the three panhead screws on the standoffs, re-
mount the front panel and the modules cover.

ProDAQ 3424 Function Card User Manual 3424-XX-UM
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3.Theory of Operation
A simplified block diagram of 3424 function card is shown on Figure 3.
A brief description of the most important blocks and available functionality follows.
Front-End Circuitry
Channel #1
Front-End Circuitry
Channel #2
24-bit ADC
2 channels
24-bit ADC
2 channels
24-bit ADC
2 channels
24-bit ADC
2 channels
Serial to Parallel
FIFO
64kSamples
24
DA control
Internal Registers
Stack B
Stack A
24
16
8
MUX
8
Clock Generation
(PLL and DDS)
Front Panel
SYNC I/O
Local
SYNC I/O
Front-End Circuitry
Channel #3
Front-End Circuitry
Channel #4
Front-End Circuitry
Channel #5
Front-End Circuitry
Channel #6
Front-End Circuitry
Channel #7
Front-End Circuitry
Channel #8
FIR Filter and
Decimation 10x
Stage #1
FIR Filter and
Decimation 10x
Stage #2
MUX
24
24
Synchronization
System
Acquisition Clock and Reset
24
Figure 3 –Simplified block diagram of 3424 function card
3.1. Analog Front-End Circuitry
3.1.1. Analog Front-End general description
The front-end of the 3424 card gives the user a flexible solution for a wide range of applications. It
is designed to accept either single-ended or differential input signals with a bandwidth of up to
100 kHz. The input signal can be either AC or DC coupled. The full-scale range of the card is
10V. For higher input voltage levels (up to 100V maximum), it is possible to have a factory set
attenuator stage.
As well as the standard sensor interface, the card includes the possibility of direct interfacing with
ICP sensors and accessing the sensors’ Transducer Electronic Data Sheet (TEDS) information.
The constant current power source is provided on the board. A LED lights when ICP is selected
and drawing current, so it simplifies system setup and detection of open circuits.
For calibration purposes, the input of every channel can be connected to the voltage output of the
high-precision ProDAQ 3201 voltage reference board by switching with relays. This voltage
reference board can be programmed to 0V (ground connection). The card has built-in input
overvoltage protection diodes designed to prevent damage being caused to the input
programmable gain amplifier (PGA) stage.
The input signal goes to the PGA stage. The possible gain values are: 1,2,5,10,20,50,100,200,500
and 1000, thus providing immense flexibility for the user. The output of the gain stage is fed to a 4
pole fixed Butterworth anti-aliasing analog input filter which allows for output sample rates in the
range of 20 kHz to 216 kHz without violating Nyquist theorem (sampling rates as low as 200 Hz
can be achieved with implemented in FPGA digital filters and decimation stages). The output of the
filter after offset correction is fed to the differential input of the ADC. Single channel configuration of
the 3424 card front-end circuitry is shown on Figure 4.

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CHN+
Input protection
+24V
10M
10M
Input protection
1uF
1uF
PGA 1
Low PassFilter
24-bit
ADC
TEDS_ON
ICP_ON
POS_CPL
NEG_CPL
GAIN1SEL[1:0]
To FPGA
PGA 2
GAIN2SEL[1:0]
VREFGND_EN
VREFGND_EN
VREF-/GND
for calibration
NEG_GND
TEDS reader
circuitry
-5V
VREF+/GND
for calibration To FPGA
SENSE ICP
Current
regulator
diode
CHN-
Figure 4 –Configuration of analog front-end circuitry (single channel) of the 3424 card
3.1.2. ICP sensor conditioning
An ICP sensor requires a constant current bias. This is generated using a Current Regulator Diode
(CRD) connected to +24V. For a +24V supply the sensor output will then bias at about +10V with
10V max swing. The accuracy of the current source is not critical although it needs to be constant.
At high frequencies ICP sensors require higher current in order to operate with the same cable
length. The maximum frequency is proportional to the current & inversely proportional to the cable
capacitance (i.e. cable length). Thus, the 3424 is fitted with one 4.7mA CRD as a standard with the
second one fitted upon request.
The ICP excitation current is switched to the ICP sensor with a relay. If ICP is selected and the ICP
excitation current is flowing then a LED lights to indicate this. Because it often happens that the
sensor do not connect directly to the VXI module, but to some external signal conditioning unit or
breakout board, it is desired that the ICP current can be indicated in this remote location. This can
be achieved with additional SENSE ICP signal routed to the front panel SCSI connector.
Comparing voltage drop across 22sense resistor with a reference voltage level allows switching
on a LED diode in the signal conditioning unit when the ICP excitation current is really flowing.
Other solutions, like digital control of a remote LED, don’t allow for detection of open circuit in this
case.
The positive output of the ICP sensor connects to the positive input of the channel. During normal
operation, the signal is AC coupled in order to remove the DC bias. The negative side of the ICP
sensor needs to be connected to the same GND as the +24V supply. For the 3424 card this is
achieved with means of a relay that can switch the negative side to GND for single-ended sensors.
At low frequencies there are two important considerations. One is the Discharge Time Constant
(DTC) of the sensor. This varies from sensor to sensor and can be from milliseconds to several
hundreds of seconds. The user needs to consider this effect when measuring signals.
The second low frequency effect is the time constant of the coupling circuit when used in AC
coupling mode. A 10MΩ resistor with a 1μF coupling capacitor requires 50 seconds to reach 5RC
(5 time constants), required for drift free stable operation.
3.1.3. TEDS reader interface

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Transducer Electronic Data Sheet (TEDS), is a nonvolatile memory within a sensor that is utilized
for storing information about that sensor. The manufacturer of the sensor deposits, into this
memory, initial information such as manufacturer name, sensor type, model number, serial
number, and calibration data. Memory space allocation permits the user to add additional
information such as channel ID, location, position, direction, tag number, etc. The protocols and
formats of the data are defined by IEEE P1451.4 standard.
The sensor operates in a “mixed mode”, i.e. analog or digital fashion. In the digital mode, the
information stored in memory is downloaded. In the analog mode, the sensor functions normally, as
a measurement device. A suitable TEDS signal conditioner is used to access the memory digitally,
over the same wires ordinarily used for analog measurement signal transmission.
The 3424 card has a common TEDS reader interface circuitry for all eight channels. A relay in the
positive input of the channel is used to connect it to a TEDS reader. Care should be taken not to
write the software in the way that connects more than one channel to the TEDS reader at a time.
3.2. Digital Front-End Circuitry
3.2.1. Motherboard function card interface
This is the interface that is used to exchange data between motherboard and function card.
Detailed description of this interface is beyond the scope of this manual. However, a short
explanation is needed regarding names used. Following names appear interchangeably throughout
document:
Trigger input, Stack A nTRIGI_A
Trigger input, Stack B nTRIGI_B
Trigger output, Stack A nTRIGO_A
Trigger output, Stack B nTRIGO_B
Direct Interrupt, Stack A nDI_A
Direct Interrupt, Stack B nDI_B
Direct Error nDE
The shorter names are used on the drawings for better clarity. The small “n” in the beginning of the
name indicates that the signal is active low level.
3.2.2. Front panel digital signals
There are three SMB type connectors on the front panel of the card.
The connectors are:
FPSYNC_IO, bi-directional Input/Output for distribution of SYNC/TRIG signals in TTL
standard. When configured as an input, the active polarity is software selectable. When
configured as an output, it is always active low level.
FPCLK_IN, clock input in ECL standard, with software programmable termination (50to –
2V)
FPCLK_OUT, clock output in ECL standard
Care should be taken while making cable connections between multiple cards. First of all, it is
important that the cables used for clock and SYNC/TRIG signals are of the same length. Big
difference in cable length could lead to a change in their phase relationship. As a result, the Master

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and Slave cards could sample analog signal on different clock edges. Cables should be kept as
short as possible. This is important when phase performance is critical. It is worth to remember that
the cable adds approximately 6 ns delay per meter. Also it is important that the optimal way of connecting fast
digital signals in respect for their integrity is point-to-point connection. If it is impossible, the stubs should be
kept as short as possible. Note that the termination on the ECL signal should be enabled only on the last
receiver in the chain. To avoid stubs, clock forwarding mechanism was implemented on 3424 card. It works
in the way that the card that receives clock on the terminated FPCLK_IN input simultaneously outputs it on
FPCLK_OUT output. This output can be connected to the input of another 3424 card, and so on. Clock
forwading requires setting bits FPCLKO_SEL in MODE2 register to ‘11’.
3.2.3. Local synchronization link
There is possibility of synchronization of multiple 3424 cards in the same VXI module with local
cable connections between them (local synchronization link). This makes possible to distribute
clock and SYNC/TRIG signals without propagating them through switch matrix on the motherboard
(trigger output lines can be used not for synchronization, but to generate interrupts to the host). For
this purpose, two special flex cable connectors are fitted in the middle of the board. The cables
necessary to make local link connection are available from Bustec. Note that the cables have
contacts only on one side, so care must be taken to insert them properly to the connector. Clear
indications of cable orientation are printed on the 3424 card.
The local synchronization signal (nLSYNC) is distributed in TTL standard (single line with open
collector drivers). Local clock (LCLK) signal, in order to ensure its high quality, is distributed in
LVDS standard. The local synchronization link is designed in the way that ensures automatic
termination of the LVDS transmission line on the last card in the local synchronization chain. As a
result, there are some limitations on Master/Slave card positions in VXI module when local
synchronization link is used –the Master must be the first card in the local synchronization chain.
Master can be on either of the stacks, but the Slaves can be only on stacks that are down the
chain. The stack order is: stack 1-2 stack 5-6 stack 7-8 stack 2-3.
3.3. Data Acquisition
The Data Acquisition (DA) on the 3424 is a process of acquiring the samples and storing them in
the memory. The samples can be acquired as a pre-trigger and post-trigger data. Before samples
becomes valid for the pre-trigger and post-trigger, the process of updating clock generation
circuitry (DDS), resetting ADCs and settling FIR filters have to take place.
The Data Acquisition is controlled by the state machine on the board. This state machine can be in
one of the following states, which determines the state of the Data Acquisition:

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STEP
STATE
DESCRIPTION
1
IDLE
(IDLE_ST)
All needed settings (front-end configuration, clock and trigger
selection, Data Acquisition modes) must be done in this step
2
DDS UPDATE
(DDSUD_ST)
Card is brought to this state with the ARMING command if
SYNC_NEED bit has been asserted. In this state, the card
performs the update of the DDS settings. If the board is a Master
then it updates DDS automatically. In the case of a Slave, it waits
for the update pulse generated by the Master and distributed
over SYNC/TRIG line.
This state is skipped if the Arming command is launched with the
SYNC_NEED bit cleared.
3
ADC SYNC
(ADCSYNC_ST)
After DDS UPDATE is done, the card performs reset and thus
synchronization of the ADCs. Similarly to the DDS update, the
Master synchronizes the ADCs automatically while the Slave
waits for the synchronization pulse from the Master. The ADCs
reset and FIR filters settling takes approximately 900ms. At the
end of the process, the Slave gets from the Master another
pulse, which causes them to proceed to next state.
This state is skipped if the Arming command is launched with the
SYNC_NEED bit cleared.
4
READY FOR DA
(READY4DA_ST)
After synchronisation is done, the hardware is ready to start Data
Acquisition. It can either start immediately, or wait for the trigger.
In addition, the card can be configured to acquire the pre-trigger
before the post-trigger phase.
When no pre-trigger and ‘start on trigger’ is selected, the state
machine stays in READY4DA_ST state as long as the trigger is
not asserted.
5
PRE-TRIGGER
(PRET_ST)
If the pre-trigger has been enabled, the card starts to collect pre-
trigger data. The amount of the scans to collect is defined in the
PRET_NOS register. The number of the pre-trigger samples
must not exceed the FIFO size.
6
POST-TRIGGER
(POSTT_ST)
Post-trigger samples are stored in the FIFO as long as the end of
the Data Acquisition does not happen. The Data Acquisition can
be ended either after a set number of the scans is collected or
after stop trigger event. In this state, it is possible emptying FIFO
on-the-fly for acquisitions longer than the FIFO size.
Table 1 –States of the Data Acquisition state machine
3.3.1. Data Acquisition modes
Data Acquisition is a process of storing samples from ADCs in the FIFO. When the ADCs and
filters have settled (synchronization is done), the board is ready to start Data Acquisition. Data
Acquisition is composed of the pre-trigger and post-trigger. It can be configured to skip the pre-
trigger.
The pre-trigger, if enabled, starts immediately after synchronization is done. The 3424 card collects
specified number of scans (PRET_NOS register) and stores them in the FIFO. The number of the
pre-trigger samples (number of the scans multiplied by number of the channels enabled for the
Data Acquisition) cannot be bigger than the size of the FIFO, as the readout of the FIFO (emptying
the FIFO) is prohibited in this state. When the required number of the scans is collected, the pre-
trigger is done but the board stays in the pre-trigger state as long as the conditions to start the
post-trigger are not fulfilled. In this case, every new scan added to the FIFO causes the oldest scan
to be dropped.

3424-XX-UM ProDAQ 3424 Function Card User Manual
Page 18 of 56 Copyright, 1998-2005 Bustec Production Ltd.
In some cases, the pre-trigger can be ended before the set number of the scans is collected. This
can happen if the trigger can be accepted before the pre-trigger is finished (PRET_REJECT bit
cleared) and start trigger event took place. If the user wants to collect the entire specified pre-
trigger, the PRET_REJECT bit has to be set. In this case, triggers coming before completion of the
pre-trigger are rejected.
If the pre-trigger is ended before completion, then the PRET_NOS register readout returns the
number of scans left to complete.
The post-trigger starts when the start condition is met. The start condition is selected with the
DA_STARTSEL bit. The following ways can be selected:
Post-trigger starts immediately after the ADCs and filters are settled (if pre-trigger has been
disabled) or after pre-trigger is done (if the pre-trigger has been enabled)
After the trigger event happens
The post-trigger ends when the Data Acquisition stop condition is met. The stop conditions of the
Data Acquisition are as follows:
Selected number of scans has been collected (DA_STOPSEL bits set to ‘00’)
Stop trigger happens (DA_STOPSEL bits set to ‘01’)
Software stop (DA_SKIP or SW_RST bits set)
Error happens (if STOP_ON_ERR bit set and any error enabled)
Up to 16,777,215 post-trigger scans can be set in the POSTT_NOSL/H registers. The unlimited
number of samples can be achieved by setting stop mode to DA_SKIP (DA_STOPSEL bits set to
‘10’).
3.3.2. Data storage and readout
The samples are stored in the on-board FIFO memory. The depth of the FIFO is 64 ksamples
(optionally it can be 128 ksamples). The samples are stored scan-by-scan, with the channel data
interleaved within the scan (channel with the lower number goes first). The scan is composed of
one to eight channels
The write to the FIFO is always 32-bit wide. The write can be performed by the motherboard during
idle state (FIFO_WRL/H registers) or by the ADCs during Data Acquisition. The 24-bit data from
the ADC is extended to the 32-bit, two’s complement format.
The readout from the FIFO can be either 16-bit or 32-bit wide, which is selected using FIFO_16B
bit. The readout initiated by the motherboard is disabled in the pre-trigger mode.
The two read out modes from the FIFO memory are:
16-bit readout: motherboard in the first access reads the 16 least significant bits from the
FIFO, the following access is used to read 16 most significant bits. This mode is supported
on both, 3120 and 3150 motherboards
32-bit readout: two stacks (A and B) are used to read all 32 bits in one access. This mode is
supported only on 3150 motherboard and improves the throughput significantly when
emptying FIFO on-the-fly.
The FIFO memory chip outputs five status flags:
1) empty flag
2) almost empty flag
3) half flag
4) almost full flag
5) full flag

ProDAQ 3424 Function Card User Manual 3424-XX-UM
Copyright, 1998-2005 Bustec Production Ltd. Page 19 of 56
The flags are used to control the number of the samples stored in the FIFO when emptying this
memory. The status of the FIFO flags can be read directly (FIFO_CTRL register) or selected flag
(only one) can be directed to the Output Trigger or Direct Interrupt.
The following table defines the FIFO flag assertion:
Number of samples in FIFO
Empty
Almost Empty
Half
Almost Full
Full
64 ksamples FIFO
128 ksamples FIFO
0
0
1
1
0
0
0
1 to (n+1)
1 to (n+1)
0
1
0
0
0
(n+2) to 32769
(n+2) to 65537
0
0
0
0
0
32770 to (65536-m)
65538 to (131072-m)
0
0
1
0
0
(65537-m) to 65536
(131073-m) to 131072
0
0
1
1
0
65537
131073
0
0
1
1
1
Table 2 –FIFO flag thresholds
The offsets: nand mare programmable. Their default value (after FIFO master reset) is 255. They
can be updated using FIFO_WRL/H registers (bits used: 16 LSB bits for 64 ksamples FIFO and 17
LSB bits for 128 ksamples FIFO) if the FIFO_LD bit has been set. The first access stores n offset,
the second access stores m offset, then the sequence repeats.
The FIFO master reset (FIFO_MRS bit) has to be performed during the board initialisation.
Afterwards, the partial reset is sufficient to reset the FIFO as it resets the pointers only.
3.3.3. FIR filters and decimation
To achieve even lower output sampling rates with the same fixed analog filter, two decimation
stages by 10 are implemented in FPGA. Internal multiplexer in the FPGA allows for selection which
data is to be stored in the FIFO. Either not decimated samples, samples decimated by 10 (one
decimation stage), or samples decimated by 100 (two decimation stages) can be selected.
However, such selection applies to all channels, i.e. all channels must work with the same output
sampling rate. With such approach, output sample rate of the card spreads from as low as 200Hz
to 216kHz.
Theoretical passband frequency of FIR filter spreads from 0.08 rad / sample (0.04 of the FIR
input sample rate). The frequency response is extremely flat in this area and has ripple of only
2.5dB. Stopband starts at 0.1 rad / sample (0.05 of the FIR input sample rate) with attenuation
of 126dB. Very narrow transition band and high requirements to the ripple and attenuation values
resulted in filter order of 802. Symmetrical coefficients ensure linear phase response in the
passband.
To minimize effects of fixed point arithmetic implementation (quantization error), 28-bit coefficient
length is used.
3.3.4. Sampling settings

3424-XX-UM ProDAQ 3424 Function Card User Manual
Page 20 of 56 Copyright, 1998-2005 Bustec Production Ltd.
To start Data Acquisition, ADC sampling clock selection and ADC output speed rate has to be set-
up.
The sampling clock can be generated on the board out of the reference clock (2 MHz) or it can be
received from the external generator (for example from the other Master) as a target ADC sampling
clock.
When generating ADC clock on the board, a 2 MHz reference clock can be taken from one of
these sources:
Local 2 MHz oscillator
Reference clock received through the stack B trigger input line and a switch matrix on the
motherboard from another ProDAQ function card
Reference clock received through the front panel from another function card or other
external clock source
This reference clock is used then to produce 125 MHz DDS input clock. DDS circuitry is used to
synthesise the clock in the range from 12.5 MHz to 25 MHz. Together with two additional frequency
dividers (the reason for them is jitter performance optimisation outside main DDS octave) it allows
for generation of any ADC clock in the range of 5.12 MHz to 13.824 MHz. The Table 3 shows the
DDS configuration and the corresponding ADC clock frequencies.
DDS output clock [MHz]
CLKSEL
ADC clock [MHz]
20.48 –25
111
5.12 –6.25
12.5 –25
110
6.25 –12.5
12.5 –13.824
101
12.5 –13.824
Table 3 –DDS settings for the required ADC clock frequency
The details on the DDS frequency programming can be found in DDS_WX register description.
In addition to the on-board generator, the target ADC clock can be taken from front panel clock
input as well as from local synchronization link clock line. Figure 5 shows the ADC clock
configuration scheme.
nTRIGI_B
OSC
PLL DDS
125MHz
2MHz
FPCLK_IN /2
/2
LCLK
12.5 - 13.824 MHz.
6.25 - 12.5 MHz.
5.12 - 6.25 MHz.
CLKSEL[2:0]
PLL_RSEL[1:0]
ADC clock
(MCLK)
0xx
100
101
110
111
01
10
11 PLL_EN
Figure 5 –ADC clock configuration
The possible output word rates for the given ADC clock and speed settings are shown in Table 4.
ADC clock
[MHz]
ADC SPEED
(over-sampling)
Output word rate [kHz]
Decimation=Off
Decimation=10
Decimation=100
5.12 –13.824
Normal (x128)
20 –54
2.0 –5.4
0.2 –0.54
5.12 –13.824
Double (x64)
40 –108
4.0 –10.8
0.4 –1.08
5.12 –13.824
Quad (x32)
80 –216
8.0 –21.6
0.8 –2.16
Table 4 –ADC output word rates
For the overlapping regions of the output word rate use the option with the higher over-sampling for
better performance.
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