Cirrus Logic CRD5378 User manual

Copyright ©Cirrus Logic, Inc. 2008
(All Rights Reserved)
www.cirrus.com
Reference Design Panel (Actual Size)
Data Aquisition Board (Actual Size) Control Board (Actual Size)
CRD5378
Single-Channel Seismic Reference Design
Features
zSingle-channel Seismic Acquisition Node
– CS3302A hydrophone amplifier
– CS5373A ∆Σ modulator + test DAC
– CS5378 digital filter + PLL
– Precision voltage reference
zOn-board Microcontroller
– SPI™interface to digital filter
– USB communication with PC
zBoard Design
– Compact board size: 5” x 1.25” x 0.5”
– Detachable acquisition and telemetry nodes
zPC Evaluation Software
– Register setup & control
– FFT frequency analysis
– Time domain analysis
– Noise histogram analysis
General Description
The CRD5378 board is a compact reference design for
the Cirrus Logic single-channel seismic chip set. Data
sheets for the CS3302A, CS5373A, and CS5378 devic-
es should be consulted when using the CRD5378
reference design.
Pin headers connect an external differential sensor to
the analog inputs of the measurement channel. An on-
board test DAC creates precision differential analog sig-
nals for in-circuit performance testing without an external
signal source.
The reference design includes an 8051-type microcon-
troller with hardware SPI™ and USB serial interfaces.
The microcontroller communicates with the digital filter
via SPI and with the PC evaluation software via USB.
The PC evaluation software controls register and coeffi-
cient initialization and performs time domain, histogram,
and FFT frequency analysis on captured data.
The CRD5378 board features a special breakout con-
nector used to detach the acquisition and telemetry
sections for remote sensor applications.
ORDERING INFORMATION
CRD5378 Reference Design
JAN ‘08
DS639RD2

CRD5378
2DS639RD2
REVISION HISTORY
Revision Date Changes
RD1 JAN 2007 Initial release.
RD2 JAN 2008 Upgrade from CS3302 to CS3302A-ISZ/G (U19).
Change (R27,R28,R29,R30) from 0ohms to 680ohms.

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Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
suppliedat the time oforder acknowledgment, including thosepertainingto warranty, indemnification, and limitationof liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-
sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT-
ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND
CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR
CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO
FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUD-
ING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
Windows, Windows XP, and Windows NT are trademarks or registered trademark of Microsoft Corporation.
SPI is a trademark of Motorola, Inc.
USBXpress is a registered trademark of Silicon Laboratories, Inc.

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TABLE OF CONTENTS
1. INITIAL SETUP .........................................................................................................................6
1.1 Kit Contents .......................................................................................................................6
1.2 Hardware Setup .................................................................................................................6
1.2.1 Default Jumper Settings ........................................................................................7
1.3 Software Setup ..................................................................................................................8
1.3.1 PC Requirements ..................................................................................................8
1.3.2 Seismic Evaluation Software Installation ..............................................................8
1.3.3 USBXpress® Driver Installation ............................................................................8
1.3.4 Launching the Seismic Evaluation Software .........................................................9
1.4 Self-Testing CRD5378 .....................................................................................................10
1.4.1 Noise Test ...........................................................................................................10
1.4.2 Distortion Test .....................................................................................................11
2. HARDWARE DESCRIPTION .................................................................................................12
2.1 Block Diagram .................................................................................................................12
2.2 Analog Hardware .............................................................................................................13
2.2.1 Analog Inputs ......................................................................................................13
2.2.2 Differential Amplifiers ..........................................................................................16
2.2.3 Delta-Sigma Modulator .......................................................................................17
2.2.4 Delta-Sigma Test DAC ........................................................................................18
2.2.5 Voltage Reference ..............................................................................................18
2.3 Digital Hardware ..............................................................................................................19
2.3.1 Digital Filter .........................................................................................................19
2.3.2 Microcontroller ....................................................................................................22
2.3.3 RS-485 Telemetry ...............................................................................................24
2.3.4 UART Connection ...............................................................................................26
2.3.5 External Connector .............................................................................................27
2.4 Power Supplies ................................................................................................................27
2.4.1 Analog Voltage Regulators .................................................................................27
2.5 PCB Layout ......................................................................................................................28
2.5.1 Layer Stack .........................................................................................................28
2.5.2 Differential Pairs ..................................................................................................28
2.5.3 Bypass Capacitors ..............................................................................................30
3. SOFTWARE DESCRIPTION ..................................................................................................31
3.1 Menu Bar .........................................................................................................................31
3.2 About Panel .....................................................................................................................32
3.3 Setup Panel .....................................................................................................................33
3.3.1 USB Port .............................................................................................................34
3.3.2 Digital Filter .........................................................................................................35
3.3.3 Analog Front End ................................................................................................36
3.3.4 Test Bit Stream ...................................................................................................36
3.3.5 Gain/Offset ..........................................................................................................37
3.3.6 Data Capture .......................................................................................................38
3.3.7 External Macros ..................................................................................................39
3.4 Analysis Panel .................................................................................................................40
3.4.1 Test Select ..........................................................................................................41
3.4.2 Statistics ..............................................................................................................42
3.4.3 Cursor .................................................................................................................42
3.4.4 Zoom ...................................................................................................................43
3.4.5 Refresh ................................................................................................................43
3.4.6 Harmonics ...........................................................................................................43
3.4.7 Spot Noise ...........................................................................................................43

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3.4.8 Plot Error ............................................................................................................. 43
3.5 Control Panel ................................................................................................................... 44
3.5.1 DF Registers ....................................................................................................... 45
3.5.2 DF Commands .................................................................................................... 45
3.5.3 SPI ......................................................................................................................45
3.5.4 Macros ................................................................................................................ 46
3.5.5 GPIO ................................................................................................................... 46
3.5.6 Customize ........................................................................................................... 47
3.5.7 External Macros .................................................................................................. 47
4. BILL OF MATERIALS ........................................................................................................... 48
5. LAYER PLOTS ...................................................................................................................... 49
6. SCHEMATICS ....................................................................................................................... 57
LIST OF FIGURES
Figure 1. CRD5378 Block Diagram............................................................................................... 12
Figure 2. Differential Pair Routing................................................................................................. 29
Figure 3. Quad Group Routing...................................................................................................... 29
Figure 4. Bypass Capacitor Placement......................................................................................... 30
LIST OF TABLES
Table 1. Amplifier Pin 13 Jumper Setting........................................................................................7
Table 2. System Clock Input Setting............................................................................................... 7
Table 3. CS5378 PLL Mode Select Setting (R15, R41, R42) ......................................................... 7
Table 4. Input SYNC Source Selection Setting............................................................................... 7
Table 5. CS5378 SYNC Source Selection Setting.......................................................................... 7
Table 6. Pin Header Input Connections........................................................................................ 13
Table 7. Amplifier Pin 13 Resistor Settings................................................................................... 16

CRD5378
6DS639RD2
1. INITIAL SETUP
1.1 Kit Contents
The CRD5378 reference design kit includes:
• CRD5378 reference design board
• USB cable (A to mini-B)
• Software download information card
The following are required to operate CRD5378, and are not included:
• Bipolar power supply with clip lead outputs (+/- 3.3 V @ 100 mA)
• PC running Windows 2000™ or Windows XP®with an available USB port
• Internet access to download the evaluation software
1.2 Hardware Setup
To set up the CRD5378 reference design hardware:
• Verify all jumpers are in the default settings (see next section).
• With power off, connect the CRD5378 power inputs to the power supply outputs.
J26 pin 17 = -3.3 V
J26 pin 19 = +3.3 V
J26 pin 20 = 0 V
• Connect the USB cable between the CRD5378 USB connector and the PC USB port.
• Proceed to the Software Setup section to install the evaluation software and USB driver.

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DS639RD2 7
1.2.1 Default Jumper Settings
* indicates the default 0 Ωjumper installations for CRD5378.
Amplifier CS3301A CS3302A
CH1 U19 R8 + R9 *R10
Table 1. Amplifier Pin 13 Jumper Setting
Input Clock Resistor
EXTERNAL CLOCK R2
1.024 MHz R70
2.048 MHz R4
4.096 MHz R3
32.768 MHz *R60
Table 2. System Clock Input Setting
Digital Filter Clock Resistor
4.096 MHz Manchester R15 + R41 + R42
2.048 MHz Manchester R42
1.024 MHz Manchester R41
32.768 MHz R41+R42
4.096 MHz R15
2.048 MHz R15+R42
1.024 MHz R15+R41
32.768 MHz *Not Populated
Table 3. CS5378 PLL Mode Select Setting (R15, R41, R42)
Sync Source Jumper
RS-485 *R47 + *R48
Direct Output R49 + R50 + R45
Table 4. Input SYNC Source Selection Setting
Sync Source Jumper
SYNC *R71 (Not Populated)
SYNC_IO R71
Table 5. CS5378 SYNC Source Selection Setting

CRD5378
8DS639RD2
1.3 Software Setup
1.3.1 PC Requirements
The PC hardware requirements for the Cirrus Seismic Evaluation system are:
• Windows XP®, Windows 2000™, Windows NT®
• Intel Pentium 600 MHz or higher microprocessor
• VGA resolution or higher video card
• Minimum 64MB RAM
• Minimum 40MB free hard drive space
1.3.2 Seismic Evaluation Software Installation
Important: For reliable USB communication, the USBXpress®driver must be installed after the Seismic
Evaluation Software installation but before launching the application. The USBXpress driver files are in-
cluded in a sub-folder as part of the installation.
To install the Cirrus Logic Seismic Evaluation Software:
• Go to the Cirrus Logic Industrial Software web page (http://www.cirrus.com/industrialsoftware). Click
the link for “Cirrus Seismic Evaluation GUI” to get to the download page andthen click the link for “Cir-
rus Seismic Evaluation GUI Release Vxx” (xx indicates the version number).
• Read the software license terms and click “Accept” to download the “SeismicEvalGUI_vxx.zip” file to
any directory on the PC.
• Unzip the downloaded file to any directory and a “Distribution\Volume1” sub-folder containing the in-
stallation application will automatically be created.
• Open the “Volume1” sub-folder and run “setup.exe”. If the Seismic Evaluation Software has been pre-
viously installed, the uninstall wizard will automatically remove the previous version during install.
• Follow the instructions presented by the Cirrus Seismic Evaluation Installation Wizard. The default in-
stallation location is “C:\Program Files\Cirrus Seismic Evaluation”.
An application note, AN271 - Cirrus Seismic Evaluation GUI Installation Guide, is available from the Cirrus
Logic web site with step-by-step instructions on installing the Seismic Evaluation Software.
1.3.3 USBXpress®Driver Installation
Important: For reliable USB communication, the USBXpress®driver must be installed after the Seismic
Evaluation Software installation but before launching the application. The USBXpress driver files are in-
cluded in a sub-folder as part of the installation.
The Cirrus Logic Seismic Evaluation Software communicates with CRD5378 via USB using the USBX-
press driver from Silicon Laboratories (http://www.silabs.com). For convenience, the USBXpress driver
files are included as part of the installation package.
To install the USBXpress driver (after installing the Seismic Evaluation Software):
• Connect CRD5378 to the PC through an available USB port and apply power. The PC will detect
CRD5378 as an unknown USB device.

CRD5378
DS639RD2 9
• If prompted for a USB driver, skip to the next step. If not, using Windows Hardware Device Manager
go to the properties of the unknown USB API device and select “Update Driver”.
• Select “Install from a list or specific location”, then select “Include this location in the search” and then
browse to “C:\Program Files\Cirrus Seismic Evaluation\Driver\”. The PC will recognize and install the
USBXpress device driver.
• After driver installation, cycle power to CRD5378. The PC will automatically detect it and add it as a
USBXpress device in the Windows Hardware Device Manager.
An application note, AN271 - Cirrus Seismic EvaluationGUI Installation Guide, is available from the Cirrus
Logic web site with step-by-step instructions on installing the USBXpress driver.
1.3.4 Launching the Seismic Evaluation Software
Important: For reliable USB communication, the USBXpress driver must be installed after the Seismic
Evaluation Software installation but before launching the application. The USBXpress driver files are in-
cluded in a sub-folder as part of the installation.
To launch the Cirrus Seismic Evaluation Software, go to:
•Start
Ö Programs Ö Cirrus Seismic Evaluation Ö Cirrus Seismic Evaluation
or:
• C:\Program Files\Cirrus Seismic Evaluation\SeismicGUI.exe
For the most up-to-date information about the software, please refer to it’s help file:
•Within the software: Help
Ö Contents
or:
• C:\Program Files\Cirrus Seismic Evaluation\SEISMICGUI.HLP

CRD5378
10 DS639RD2
1.4 Self-Testing CRD5378
Noise and distortion self-tests can be performed once hardware and software setup is complete.
First, initialize the CRD5378 reference design:
• Launch the evaluation software and apply power to CRD5378.
• Click ‘OK’ on the About panel to get to the Setup panel.
• On the Setup panel, select Open Target on the USB Port sub-panel.
• When connected, the Board Name and MCU code version will be displayed.
1.4.1 Noise Test
Noise performance of the measurement channel can be tested as follows:
• Set the controls on the Setup panel to match the picture:

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• Once the Setup panel is set, select Configure on the Digital Filter sub-panel.
• After digital filter configuration is complete, click Capture on the Data Capture sub-panel.
• Once the data record is collected, the Analysis panel is automatically displayed.
• Select Noise FFT from the Test Select control to display the calculated noise statistics.
• Verify the noise performance (S/N) is 124 dB or better.
1.4.2 Distortion Test
• Set the controls on the Setup panel to match the picture:
• Once the Setup panel is set, select Configure on the Digital Filter sub-panel.
• After digital filter configuration is complete, click Capture on the Data Capture sub-panel.
• Once the data record is collected, the Analysis panel is automatically displayed.
• Select Signal FFT from the Test Select control to display the calculated noise statistics.
• Verify the distortion performance (S/D) is 109 dB or better.

CRD5378
12 DS639RD2
2. HARDWARE DESCRIPTION
2.1 Block Diagram
Major blocks of the CRD5378 reference design include:
• CS3302A Hydrophone Amplifier
• CS5373A ∆Σ Modulator + Test DAC
• CS5378 Digital Filter + PLL
• Precision Voltage Reference
• Microcontroller with USB
• RS-485 Transceivers
• Voltage Regulators
Figure 1. CRD5378 Block Diagram

CRD5378
DS639RD2 13
2.2 Analog Hardware
2.2.1 Analog Inputs
2.2.1.1 External Inputs - INA
External signals into CRD5378 are from two major classes of sensors, moving coil geophones and piezo-
electric hydrophones. Geophones are low-impedance sensors optimized to measure vibrations in land
applications. Hydrophones are high-impedance sensors optimized to measure pressure in marine appli-
cations. Other sensors for earthquake monitoring and military applications are considered as geophones
for this data sheet.
External signals connect to CRD5378 through a 3-pin header on the left side of the PCB. This header
makes a connection to the differential INA amplifier inputs and to either a GND or GUARD signal for con-
nection to the sensor cable shields, if present.
2.2.1.2 GUARD Output, GND Connection
The CS3302A hydrophone amplifier provides a GUARD signal output on pin 13 designed to actively drive
the cable shield of a high impedance sensor with the common mode voltage of the sensor differential sig-
nal. This GUARD output on the cable shield minimizes leakage by minimizing the voltage differential be-
tween the sensor signal and the cable shield. The CS3301A geophone amplifier does not have a GUARD
output. Instead, the CS3301A amplifier expects an MCLK clock input to pin 13, which is needed for its
chopper stabilization circuitry. When using a CS3301A amplifier, a cable shield termination to GND is pro-
vided for the sensor connection.
By default, CRD5378 uses the CS3302A amplifier. Therefore, the GUARD signal is connected to pin 3 of
the input signal header, J4.
To configure CRD5378 with the CS3301A geophone amplifier, simply make the following three changes:
1) De-solder the 0 Ωresistor at R10 to remove the GUARD signal from pin 3 of J4.
2) Populate R8 with a 0 Ωresistor to provide a cable shield termination to GND.
3) Populate R9 with a 0 Ωresistor so that the CS3301A amplifier can receive its required master clock
(MCLK) from the CS5378 digital filter.
2.2.1.3 Internal Inputs - DAC_OUT, DAC_BUF
The CS5373A test DAC has two high performance differential test outputs, a precision output (DAC_OUT)
and a buffered output (DAC_BUF). The DAC_OUT signal is wired directly to the INB inputs of the
CS3302A amplifier for testing the performance of the electronics channel. The DAC_BUF signal is wired
to the INA inputs of the amplifier and is used to test the performance of the measurement channel with a
sensor attached.
Signal Input Pin Header
CH1 INA J4
Table 6. Pin Header Input Connections

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2.2.1.4 Input Protection
Sensor inputs must have circuitry to protect the analog electronics from voltage spikes. Geophone coils
are susceptible to magnetic fields (especially from lightning) and hydrophones can produce large voltage
spikes if located near an air gun source.
Discrete switching diodes quickly clamp the analog inputs to the power supply rails when the input voltage
spikes. These diodes are reverse biased in normal operation and have low reverse bias leakage and ca-
pacitance characteristics to maintain high linearity on the analog inputs.
2.2.1.5 Input RC Filters
Following the diode clamps is an RC filter network that bandwidth limits the sensor inputs into the ampli-
fiers to 'chop-the-tops-off' residual voltage spikes not clamped by the discrete diodes. In addition, all Cir-
rus Logic component ICs have built in ESD protection diodes guaranteed to 2000 V HBM / 200 V MM
(JEDEC standard). The small physical size of these ESD diodes restricts their current capacity to 10 mA.
For land applications that use the CS3301A amplifier, the INA input has a common mode and differential
RC filter. The common mode filter sets a low-pass corner to shunt very high frequency components to
ground with minimal noise contribution. The differential filter sets a low-pass corner high enough not to
affect the magnitude response of the measurement bandwidth.
For marine applications that use the CS3302A amplifier, theinherent capacitance of the piezoelectric sen-
sor is combined with large resistors to create an analog high-pass RC filter to eliminate the low-frequency
components of ocean noise.
Specification Value
Dual Series Switching Diode - ON Semiconductor BAV99LT1
Surface Mount Package Type SOT-23
Non-Repetitive Peak Forward Current (1 µs, 1 ms, 1 s) 2.0 A, 1.0 A, 500 mA
Reverse Bias Leakage (25 C to 85 C) 0.004 µA - 0.4 µA
Reverse Bias Capacitance (0 V to 5 V) 1.5 pF - 0.54 pF

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2.2.1.6 Common Mode Bias
Differential analog signals into the CS3301A/02A amplifiers are required to be biased to the center of the
power supply voltage range, which for bipolar supplies is near ground potential. Resistors to create the
common mode bias are selected based on the sensor impedance and may need to be modified from the
CRD5378 defaults depending on the sensor to be used. Refer to the recommended operating bias con-
ditions for the selected sensor, which are available from the sensor manufacturer.
Land Common Mode Filter Specification Value
Common Mode Capacitance 10 nF + 10%
Common Mode Resistance 200 Ω
Common Mode -3 dB Corner @ 6 dB/octave 80 kHz + 10%
Land Differential Filter Specification Value
Differential Capacitance 10 nF + 10%
Differential Resistance 200 Ω + 200 Ω = 400 Ω
Differential -3 dB Corner @ 6 dB/octave 40 kHz + 10%
Marine Common Mode Filter Specification Value
Hydrophone Group Capacitance 128 nF + 10%
Differential Resistance 412 kΩ + 2 kΩ
-3 dB Corner @ 6 dB/octave 3 Hz + 10%
Specification Value
Geophone Sensor Bias Resistance 20 kΩ|| 20 kΩ= 10 kΩ
Hydrophone Sensor Bias Resistance 18 MΩ|| 18 MΩ= 9 MΩ

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16 DS639RD2
2.2.2 Differential Amplifiers
The CS3301A/02A amplifiers act as a low-noise gain stage for internal or external differential analog sig-
nals.
2.2.2.1 MCLK Input vs. GUARD Output
By default, CRD5378 uses the CS3302A hydrophone amplifier. The CS3302A amplifier is a very high in-
put impedance device and achieves a 1/f noise performance typically buried below the low-frequency
ocean noise. To minimize leakage from high impedance sensors connected to the CS3302A amplifier, pin
13 produces a GUARD signal output to actively drive a sensor cable shield with the common mode volt-
age of the sensor signal.
Comparing the CS3301A and CS3302A amplifiers, the functionality of pin 13 (MCLK input vs. GUARD
output) is the only external difference. The CS3301A amplifier is chopper-stabilized requiring a clock
source on input pin 13. In order to run thechopper circuitry synchronous to the modulator analogsampling
clock, the CS3301A amplifier pin 13 connects to the CS5378 digital filter (MCLK).
CRD5378 can be convertedto use either the CS3301A and CS3302A amplifiers by installingthe amplifier
device and populating R8, R9, and R10 with 0 Ωresistors accordingly.
Replacement amplifiers can be requested as samples from the local Cirrus Logic sales representative.
2.2.2.2 Rough-Fine Outputs - OUTR, OUTF
The analog outputs of the CS3301A/02A differential amplifiers are split into rough charge and fine charge
signals for input to the CS5373A ∆Σ modulator.
Analog Signals Description
INA Sensor analog input
INB Test DAC analog input
OUTR, OUTF Analog rough / fine outputs
GUARD CS3302A guard output (R10 = 0 Ω, R9 = NO POP)
Digital Signals Description
MUX[0..1] Input mux selection
GAIN[0..2] Gain range selection
PWDN Power down mode enable
CLK CS3301A clock input (R10 = NO POP, R9 = 0 Ω)
Amplifier CS3301A CS3302A
U19 R8 + R9 *R10
Table 7. Amplifier Pin 13 Resistor Settings

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Analog signal traces out of the CS3301A/02A amplifiers and into the CS5373A modulator are 4-wire
INR+, INF+, INF-, INR- quad groups, and are routed with INF+ and INF- as a traditional differential pair
and INR+ and INR- as guard traces outside the respective INF+ and INF- traces.
2.2.2.3 Anti-alias RC Filters
The CS5373A ∆Σ modulator is 4th order and high frequency input signals can cause instability. Simple
single-pole anti-alias RC filters are required between the CS3301A/02A amplifier outputs and the
CS5373A modulator inputs to bandwidth limit analog signals into the modulator.
For the CRD5378, the CS3301A/02A amplifier outputs are connected to external 680 Ω series resistors
and a differential anti-alias RC filter is created by connecting 20 nF of high linearity differential capacitance
(2x 10 nF C0G) between each half of the rough and fine signals.
2.2.3 Delta-Sigma Modulator
The CS5373A ∆Σ modulator performs the A/D function for differential analog signals from the
CS3301A/02A amplifier. The digital output from the modulator is an oversampled ∆Σ bit stream.
2.2.3.1 Rough-Fine Inputs - INR, INF
The modulator analog inputs are separated into rough and fine signals, each of which has an anti-alias
RC filter to limit the signal bandwidth into the modulator inputs.
Analog Signals Description
INR, INF Modulator analog rough / fine inputs
VREF Voltage reference analog inputs
Digital Signals Description
MDATA Modulator delta-sigma data output
MFLAG Modulator over-range flag output
MCLK Modulator clock input
MSYNC Modulator synchronization input

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2.2.4 Delta-Sigma Test DAC
The CS5373A test DAC creates differential analog signals for system tests. Multiple test modes are avail-
able and their use is described in the CS5373A data sheet.
2.2.4.1 Precision Output - DAC_OUT
The CS5373A test DAC has a precision output (DAC_OUT) that is routed directly to the amplifier INB in-
puts. The input impedance of the CS3301A/02A INB amplifier inputs are high enough that the precision
output can be directly connected to the INB inputs.
2.2.4.2 Buffered Output - DAC_BUF
The CS5373A test DAC has a buffered output (DAC_BUF) that is routed to the amplifier INA inputs. This
output is less sensitive to loading than the precision outputs, and can drive a sensor attached to the am-
plifier INA inputs provided the sensor meets the impedance requirements specified in the CS5373A data
sheet.
2.2.5 Voltage Reference
A voltage reference on CRD5378 creates a precision voltage from the regulated analog supplies for the
modulator and test DAC VREF inputs. Because the voltage reference output is generated relative to the
negative analog power supply, VREF+ is near GND potential for bipolar power supplies.
Analog Signals Description
OUT Precision differential analog output
BUF Buffered differential analog output
CAP Capacitor connection for internal anti-alias filter
VREF Voltage reference analog inputs
Digital Signals Description
TDATA Delta-sigma test data input
MCLK Clock input
SYNC Synchronization input
MODE[0..2] Test mode selection
ATT[0..2] Attenuation range selection
Specification Value
Precision Reference - Linear Tech LT1019AIS8-2.5
Surface Mount Package Type SO-8
Output Voltage Tolerance +/- 0.05%
Temperature Drift 10 ppm / degC
Quiescent Current 0.65 mA
Output Voltage Noise, 10 Hz - 1 kHz 4 ppmRMS
Ripple Rejection, 10 Hz - 200 Hz > 100 dB

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2.2.5.1 VREF_MOD
The voltage reference output is provided to the CS5373A ∆Σ modulator and test DAC through a low-pass
RC filter. By filtering the voltage reference to the device, high-frequency noise is eliminated and any sig-
nal-dependent sampling of VREF is isolated. The voltage reference signal is routed as a separate differ-
ential pair from the large RC filter capacitor to control the sensitive VREF source-return currents and keep
them out of the ground plane. In addition to the RC filter function, the 68 uF filter capacitor provides a large
charge-well to help settle voltage reference sampling transients.
2.3 Digital Hardware
2.3.1 Digital Filter
The CS5378 digital filter performs filtering and decimation of the ∆Σ bit stream from the CS5373A modu-
lator. It also creates a ∆Σ bit stream output to create analog test signals in the CS5373A test DAC.
The CS5378 requires several control signal inputs from the external system.
Configuration and data collection are through the SPI port.
Modulator ∆Σ data is input through the modulator interface, and test DAC ∆Σ data is generated by the test
bit stream generator.
Control Signals Description
RESETz Reset input, active low
BOOT Microcontroller / EEPROM boot mode select
TIMEB Time Break input, rising edge triggered
CLK Master clock input, 32.768 MHz
SYNC Master synchronization input, rising edge triggered
SPI1 Signals Description
DRDYz Data ready output, active low
SCK Serial clock
MISO Master in / slave out serial data
MOSI Master out /slave in serial data
SS: EECSz Serial chip select, active low
Modulator Signals Description
MCLK Modulator clock output
MSYNC Modulator synchronization output
MDATA Modulator delta-sigma data input
MFLAG Modulator over-range flag input
TBSDATA Test DAC delta-sigma data output

CRD5378
20 DS639RD2
Amplifier, modulator and test DAC pin settings are controlled through the GPIO port.
2.3.1.1 Reset Options - BOOT, PLL
Immediately following the reset signal rising edge, the CS5378 digital filter latches the states of the
GPIO[4..6]:PLL[0..2] and GPIO7:BOOT pins. The reset states of the GPIO[4..6]:PLL[0..2] pins select the
master clock input frequency and type, while the reset state of the GPIO7:BOOT pin selects how the
CS5378 digital filter receives configuration data.
At reset, the CS5378 digital filter GPIO pins default as inputs with weak pull-up resistors enabled. There-
fore, if left floating, the GPIO state will read high upon reset.
The CRD5378 provides the option to connect the GPIO[4..6]:PLL[0..2] and GPIO7:BOOT pins to 10k Ω
pull-down resistors (R15, R41, and R42) so they will read low at reset. Because the pin states are latched
only during reset, GPIO pins can be programmed and used normally after reset without affecting the PLL
and BOOT selections.
Detailed information about the PLL input clock and BOOT mode selections at reset can be found in the
CS5378 data sheet.
2.3.1.2 Configuration - SPI Port
On CRD5378, configuration of the digital filter is through the SPI port by the on-board 8051 microcontrol-
ler, which receives commands from the PC evaluation software via the USB interface. Evaluation software
commands can write/read digital filter registers, specify digital filter coefficients and start/stop digital filter
operation.
By default the BOOT signal is set low to indicateconfiguration information is written by the microcontroller.
2.3.1.3 Phase Locked Loop
To make synchronous analog measurements throughout a distributed system, a synchronous system
clock needs to be provided to each measurement node. For evaluation testing purposes, the CRD5378
can receive an external system clock by access through J1 and by non-population of R2, R3, R4, R60,
and R70. With this external clock, a synchronous local clock can be created using the CS5378 PLL. The
GPIO Signals Description
GPIO[0]:MUX[0] Amplifier input mux selection
GPIO[1..3]:MODE[0..2] Test DAC mode selection
GPIO[4..6]:GAIN[0..2] Amplifier gain / test DAC attenuation
GPIO[7]:MUX[1] Amplifier input mux selection