Cirrus Logic CobraNet Silicon Series Instructions for use

© Copyright 2004 Cirrus Logic, Inc. Oct 2004
DS651UM21
http://www.cirrus.com
Digital Audio Networking Processor
CS181xx
Preliminary Product Information This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
CobraNet
Silicon Series
CS18100, CS18101, CS18102, and CM-2
Hardware User’s Manual
Version 2.1
Replaces DS651UM20
™

2©Copyright 2004 Cirrus Logic, Inc. DS651UM21
CobraNet Hardware User’s Manual
32-bit Audio Decoder DSP Family
- NOTES -

CobraNet Hardware User’s Manual
Tableof Contents
DS651UM21 ©Copyright 2004 Cirrus Logic, Inc. 3
Version 2.1
Table of Contents
List of Figures..................................................................................................................................4
1.0 Introduction......................................................................................................................................5
2.0 Features ..........................................................................................................................................6
2.1 CobraNet ............................................................................................................................6
2.2 CobraNet Interface .............................................................................................................6
2.3 Host Interface .....................................................................................................................7
2.4 Asynchronous Serial Interface............................................................................................7
2.5 Synchronous Serial Audio Interface ...................................................................................7
2.6 Audio Clock Interface .........................................................................................................7
2.7 Audio Routing and Processing ...........................................................................................7
3.0 Hardware.........................................................................................................................................8
4.0 Pinout and Signal Descriptions........................................................................................................9
4.1 CS181xx Package Pinouts...............................................................................................10
4.1.1 CS181xx Pinout ............................................................................................10
4.1.2 CM-2 Connector Pinout.................................................................................11
4.2 Signal Descriptions...........................................................................................................12
4.2.1 Host Port Signals ..........................................................................................12
4.2.2 Asynchronous Serial Port (UART Bridge) Signals ........................................12
4.2.3 Synchronous Serial (Audio) Signals..............................................................13
4.2.4 Audio Clock Signals ......................................................................................13
4.2.5 Miscellaneous Signals...................................................................................14
4.2.6 Power and Ground Signals ...........................................................................14
4.2.7 System Signals .............................................................................................15
5.0 Synchronization.............................................................................................................................16
5.1 Synchronization Modes ....................................................................................................16
5.1.1 Internal Mode ................................................................................................17
5.1.2 Internal Mode with External Sample Synchronization...................................17
5.1.3 External Word Clock Mode ...........................................................................17
5.1.4 External Master Clock Mode.........................................................................18
5.1.5 External Master Clock Mode with External Sample Synchronization............18
6.0 Digital Audio Interface ...................................................................................................................19
6.1 Digital Audio Interface Timing...........................................................................................20
6.1.1 Normal Mode Data Timing ............................................................................21
6.1.2 I2S Mode Data Timing ..................................................................................21
6.1.3 Standard Mode Data Timing .........................................................................22
7.0 Host Management Interface (HMI) ................................................................................................23
7.1 Hardware..........................................................................................................................23
7.3 Protocol and Messages....................................................................................................26
7.3.1 Messages......................................................................................................26
7.3.1.1. Translate Address .................................................................................27
7.3.1.2. Interrupt Acknowledge...........................................................................27
7.3.1.3. Goto Packet...........................................................................................27
7.3.1.4. Goto Translation....................................................................................27
7.3.1.5. Packet Received ...................................................................................28
7.3.1.6. Packet Transmit ....................................................................................28
7.3.1.7. Goto Counters.......................................................................................28
7.3.2 Status............................................................................................................29
7.3.3 Data...............................................................................................................30
7.3.3.1. Region length ........................................................................................30
7.3.3.2. Writable Region.....................................................................................30
7.3.3.3. Translation Complete ............................................................................30

4©Copyright 2004 Cirrus Logic, Inc. DS651UM21
Version 2.1
CobraNet Hardware User’s Manual
List of Figures
7.3.3.4. Packet Transmission Complete.............................................................30
7.3.3.5. Received Packet Available....................................................................30
7.3.3.6. Message Togglebit................................................................................30
8.0 HMI Reference Code.....................................................................................................................31
8.1 HMI Definitions .................................................................................................................31
8.2 HMI Access Code.............................................................................................................32
8.3 CM-1, CM-2 Auto-detection..............................................................................................34
9.0 Mechanical Drawings and Schematics..........................................................................................35
9.1 CM-2 Mechanical Drawings..............................................................................................36
9.2 CM-2 Schematics .............................................................................................................42
9.3 CS181xx Package............................................................................................................49
9.4 Temperature Specifications..............................................................................................50
List of Figures
Figure 1. CobraNet Data Services.........................................................................................................5
Figure 2. CobraNet Interface Hardware Block Diagram.........................................................................8
Figure 3. Audio Clock Sub-system.......................................................................................................16
Figure 4. Channel Structure for Synchronous Serial Audio at 64FS
(One Sample Period) - CS18100 & CS18101..................................................................19
Figure 5. Channel Structure for Synchronous Serial Audio at 128FS
(One Sample Period) - CS18102......................................................................................19
Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1.....................................20
Figure 7. Serial Port Data Timing Overview.........................................................................................20
Figure 8. Audio Data Timing Detail - Normal Mode, 64FS - CS18100, CS18101................................21
Figure 9. Audio Data Timing Detail - Normal Mode, 128FS - CS18102...............................................21
Figure 10. Audio Data Timing Detail - I2S Mode, 64FS - CS18100, CS18101....................................21
Figure 11. Audio Data Timing Detail - I2S Mode, 128FS - CS18102...................................................21
Figure 12. Audio Data Timing Detail - Standard Mode, 64FS - CS18100, CS18101...........................22
Figure 13. Audio Data Timing Detail - Standard Mode, 128FS - CS18102..........................................22
Figure 14. Host Port Read Cycle Timing..............................................................................................25
Figure 15. Host Port Write Cycle Timing..............................................................................................25
Figure 16. CM-2 Module Assembly Drawing........................................................................................36
Figure 17. General PCB Dimensions...................................................................................................37
Figure 18. Example Configuration, Side View......................................................................................38
Figure 19. Faceplate Dimensions ........................................................................................................39
Figure 20. Case Cutout for Faceplate Mounting..................................................................................40
Figure 21. Connector Detail.................................................................................................................41
Figure 22. CM-2 RevE Schematic Page 1 of 7....................................................................................42
Figure 23. CM-2 RevE Schematic Page 2 of 7....................................................................................43
Figure 24. CM-2 RevE Schematic Page 3 of 7....................................................................................44
Figure 25. CM-2 RevE Schematic Page 4 of 7....................................................................................45
Figure 26. CM-2 RevE Schematic Page 5 of 7....................................................................................46
Figure 27. CM-2 RevE Schematic Page 6 of 7....................................................................................47
Figure 28. CM-2 RevE Schematic Page 7 of 7....................................................................................48
Figure 29. 144-Pin LQFP Package Drawing........................................................................................49

CobraNet Hardware User’s Manual
Introduction
DS651UM21 ©Copyright 2004 Cirrus Logic, Inc. 5
Version 2.1
1.0 Introduction
This document is intended to help hardware designers integrate the CobraNetTM interface
into an audio system design. It covers the CS18100, CS18101, and CS18102 members
of the CobraNetTM Silicon Series of devices as well as the CM-2 module.
CobraNet is a combination of hardware (the CobraNet interface), network protocol, and
firmware. CobraNet operates on a switched Ethernet network and provides the following
additional communications services.
• Isochronous (Audio) Data Transport
• Sample Clock Distribution
• Control and Monitoring Data Transport
The CobraNet interface performs synchronous-to-isochronous and isochronous-to-
synchronous conversions as well as the data formatting required for transporting real-time
digital audio over the network.
The CobraNet interface has provisions for carrying and utilizing control and monitoring
data such as Simple Network Management Protocol (SNMP) through the same network
connection as the audio. Standard data transport capabilities of Ethernet are shown here
as unregulated traffic. Since CobraNet is Ethernet based, in most cases, data
communications and CobraNet applications can coexist on the same physical network.
Figure 1 illustrates the different data services available through the CobraNet system.
Figure 1. CobraNet Data Services
Isochronous Data
(Audio)
Control Data
Clock
Unregulated
Traffic
Ethernet
Ethernet
Control Data
Isochronous Data
(Audio)
Unregulated
Traffic
Clock

6©Copyright 2004 Cirrus Logic, Inc. DS651UM21
Version 2.1
CobraNet Hardware User’s Manual
Features
2.0 Features
2.1 CobraNet
• Real-time Digital Audio Distribution via Ethernet
• No Overall Limit on Network Channel Capacity
• Fully IEEE 802.3 Ethernet Standards Compliant
• Fiber optic and gigabit Ethernet variants are fully supported.
• Ethernet infrastructure can be used simultaneously for audio and data
communications.
• Free CobraCAD™ Audio Network Design Tool
• High-quality Audio Sample Clock Delivery Over Ethernet
• Bit-transparent 16-, 20-, and 24-bit Audio Transport
• Professional 48kHz and 96kHz sample rate
• Select Latency as Low as 1.33ms
• Flexible Many-to-many Network Audio Routing Capabilities
• Reduced-cost, Improved-performance, Convergent Audio Distribution
Infrastructure
2.2 CobraNet Interface
• Auto-negotiating 100Mbit Full-duplex Ethernet Connections
• 16-channel Audio I/O Capability
• Implements CobraNet Protocol for real-time transport of audio over Ethernet.
• Local Management via 8-bit Parallel Host Port
• UDP/IP Network Stack with Dynamic IP Address Assignment via BOOTP or
RARP
• Remote Management via Simple Network Management Protocol (SNMP)
• Economical Three-chip Solution
• Available Module form factor allows for flexible integration into audio products.
• Non-volatile Storage of Configuration Parameters
• Safely Upgrade Firmware Over Ethernet Connection
• LED Indicators for Ethernet Link, Activity, Port Selection, and Conductor Status
• Watchdog Timer Output for System Integrity Assurance
• Comprehensive Power-on Self-test (POST)
• Error and Fault Reporting and Logging Mechanisms

CobraNet Hardware User’s Manual
Features
DS651UM21 ©Copyright 2004 Cirrus Logic, Inc. 7
Version 2.1
2.3 Host Interface
• 8-bit Data, 4-bit Address
• Virtual 24-bit Addressing with 32-bit Data
•Polled, Interrupt and DMA Modes of Operation
• Configure and Monitor CobraNet Interface
• Transmit or Receive Ethernet Packets at Near-100 Mbit Wire Speed
2.4 Asynchronous Serial Interface
• Full-duplex Capable
• 8-bit Data Format
• Supports all Standard Baud Rates
2.5 Synchronous Serial Audio Interface
• Up to Four Bi-directional Interfaces Supporting up to 32 Channels of Audio I/O
• 64FS (3.072 MHz) Bit Rate for CS18100 and CS18101
• 128FS (6.144 MHz) Bit Rate for CS18102
• Accommodates Many Synchronous Serial Formats Including I2S
• 32-bit Data Resolution on All Audio I/O
2.6 Audio Clock Interface
• 5 Host Audio-clocking Modes for Maximum Flexibility in Digital Audio Interface
Design
• Low-jitter Master Audio Clock Oscillator (24.576 MHz)
• Synchronize to Supplied Master and/or Sample Clock
• Sophisticated jitter attenuation assures network perturbations do not affect
audio performance.
2.7 Audio Routing and Processing
• Single-channel Granularity in Routing From Synchronous Serial Audio
Interface to CobraNet Network
• Two levels of inward audio routing affords flexibility in audio I/O interface design
in the host system.
• Local Audio Loopback and Output Duplication Capability
• Peak-read Audio Metering with Ballistics

8©Copyright 2004 Cirrus Logic, Inc. DS651UM21
Version 2.1
CobraNet Hardware User’s Manual
Hardware
3.0 Hardware
Figure 2 shows a high-level view of the CobraNet CM-2 interface hardware architecture.
Figure 2. CobraNet Interface Hardware Block Diagram
Flash memory holds the CobraNet firmware and management interface variable settings.
The CS181xx is the heart of the CobraNet interface. It implements the network protocol
stacks and performs the synchronous-to-isochronous and isochronous-to-synchronous
conversions. The CS181xx has a role in sample clock regeneration and performs all
interactions with the host system.
The sample clock is generated by a voltage-controlled crystal oscillator (VCXO)
controlled bythe CS181xx. The VCXO frequency is carefully adjusted to achieve lock with
the network clock.
The Ethernet controller is a standard interface chip that implements the 100-Mbit Fast
Ethernet standard. As per Ethernet requirements the interface is transformer isolated.
VCXO
Ethernet
Magnetics
Clock
Audio
Serial
Host
Control
Clock
CobraNet CM-2
Module
Flash
Memory
Ethernet
Controller
CS18101

CobraNet Hardware User’s Manual
Pinout and Signal Descriptions
DS651UM21 ©Copyright 2004 Cirrus Logic, Inc. 9
Version 2.1
4.0 Pinout and Signal Descriptions
This section details the chip pinout and signal interfaces for each module and is divided
as follows:
•"CS181xx Package Pinouts" on page 10
•"Host Port Signals" on page 12
•"Asynchronous Serial Port (UART Bridge) Signals" on page 12
•"Synchronous Serial (Audio) Signals" on page 13
•"Audio Clock Signals" on page 13
•"Miscellaneous Signals" on page 14
•"Power and Ground Signals" on page 14
•"System Signals" on page 15

10 ©Copyright 2004 Cirrus Logic, Inc. DS651UM21
Version 2.1
CobraNet Hardware User’s Manual
Pinout and Signal Descriptions
4.1 CS181xx Package Pinouts
4.1.1 CS181xx Pinout
Table 1 lists the pinout for the 144-pin LQFP CS181xx chip. The interfaces for these
signals are expanded in the following sections.
Table 1. CS181xx Pin Assignments
Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name
1VCXO_CTRL 37 DATA1 73 VDDIO 109 HADDR1
2MCLK_SEL 38 WE 74 ADDR10 110 HADDR0
3DBDA 39 DATA0 75 ADDR14 111 HDATA7
4DBCK 40 DATA15 76 GND 112 HDATA6
5NC 41 DATA14 77 ADDR13 113 VDDIO
6NC 42 DATA13 78 NC 114 HDATA5
7NC 43 DATA12 79 NC 115 HDATA4
8DAO_MCLK 44 VDDIO 80 NC 116 GND
9TEST 45 DATA11 81 NC 117 HDATA3
10 VDDD 46 DATA10 82 ADDR15 118 HDATA2
11 HS3 47 GND 83 VDDD 119 VDDD
12 NC 48 DATA9 84 ADDR16 120 HDATA1
13 GND 49 DATA8 85 ADDR17 121 HDATA0
14 DAO2_LRCLK 50 NC 86 GND 122 GND
15 DAO1_DATA3 51 NC 87 ADDR18 123 XTAL_OUT
16 DAO1_DATA2/HS2 52 NC 88 ADDR19 124 XTO
17 DAO1_DATA1/HS1 53 NC 89 OE 125 XTI
18 VDDIO 54 VDDD 90 CS1 126 GND_a
19 DAO1_DATA0/HS0 55 ADDR12 91 VDDIO 127 FILT2
20 DAO1_SCLK 56 ADDR11 92 MUTE 128 FILT1
21 GND 57 GND 93 HRESET 129 VDD_A
22 DAO1_LRCLK 58 ADDR9 94 GND 130 VDDD
23 UART_TX_OE 59 ADDR8 95 WATCHDOG 131 DAI1_DATA3
24 VDDD 60 VDDIO 96 IOWAIT 132 DAI1_DATA2
25 UART_TXD 61 ADDR7 97 REFCLK_IN 133 GND
26 UART_RXD 62 ADDR6 98 VDDD 134 DAI1_DATA1
27 GND 63 GND 99 GPIO0 135 DAI1_DATA0
28 NC 64 ADDR5 100 GPIO1 136 VDDIO
29 DATA7 65 CS2 101 GND 137 DAI1_SCLK
30 DATA6 66 VDDD 102 HACK 138 DAI1_LRCLK
31 DATA5 67 ADDR4 103 HDS 139 GND
32 DATA4 68 ADDR3 104 HEN 140 HREQ
33 VDDIO 69 GND 105 HADDR3 141 NC
34 DATA3 70 ADDR2 106 HADDR2 142 NC
35 DATA2 71 ADDR1 107 HR/W 143 IRQ1
36 GND 72 ADDR0 108 GPIO2 144 IRQ2

CobraNet Hardware User’s Manual
Pinout and Signal Descriptions
DS651UM21 ©Copyright 2004 Cirrus Logic, Inc. 11
Version 2.1
4.1.2 CM-2 Connector Pinout
Table 1 lists the pinout for the four pinout connectors on the CM-2 board (J1-J4). The
interfaces for these signals are expanded following the table.
Table 2. CM-2 Pin Assignments
Conn. Pin # Pin Name Conn. Pin # Pin Name Conn. Pin # Pin Name
J1/J2 A1 UART_RXD J1/J2 B8 GND J3/J4 A15 DAI1_DATA3
J1/J2 A2 UART_TX_OE J1/J2 B9 VCC_+3.3V J3/J4 A16 RSVD3
J1/J2 A3 HACK J1/J2 B10 GND J3/J4 A17 WATCHDOG
J1/J2 A4 HR/W J1/J2 B11 VCC_+3.3V J3/J4 A18 RSVD4
J1/J2 A5 HDS J1/J2 B12 GND J3/J4 A19 AUX_POWER2
J1/J2 A6 HREQ J1/J2 B13 VCC_+3.3V J3/J4 A20 AUX_POWER0
J1/J2 A7 HEN J1/J2 B14 GND J3/J4 B1 GND
J1/J2 A8 HADDR0 J1/J2 B15 VCC_+3.3V J3/J4 B2 VCC_+3.3V
J1/J2 A9 HADDR1 J1/J2 B16 GND J3/J4 B3 GND
J1/J2 A10 HADDR2 J1/J2 B17 VCC_+3.3V J3/J4 B4 VCC_+3.3V
J1/J2 A11 HDATA0 J1/J2 B18 RSVD1 J3/J4 B5 GND
J1/J2 A12 HDATA1 J1/J2 B19 GND J3/J4 B6 VCC_+3.3V
J1/J2 A13 HDATA2 J1/J2 B20 VCC_+3.3V J3/J4 B7 GND
J1/J2 A14 HDATA3 J3/J4 A1 RSVD2 J3/J4 B8 VCC_+3.3V
J1/J2 A15 HDATA4 J3/J4 A2 MUTE J3/J4 B9 GND
J1/J2 A16 HDATA5 J3/J4 A3 FS1 J3/J4 B10 VCC_+3.3V
J1/J2 A17 HDATA6 J3/J4 A4 MCLK_OUT J3/J4 B11 GND
J1/J2 A18 HRESET J3/J4 A5 MCLK_IN J3/J4 B12 VCC_+3.3V
J1/J2 A19 HDATA7 J3/J4 A6 REFCLK_IN J3/J4 B13 GND
J1/J2 A20 HADDR3 J3/J4 A7 DAO1_SCLK/DAI1_SCLK J3/J4 B14 VCC_+3.3V
J1/J2 B1 UART_TXD J3/J4 A8 DAO1_DATA0 J3/J4 B15 GND
J1/J2 B2 GND J3/J4 A9 DAO1_DATA1 J3/J4 B16 GND
J1/J2 B3 VCC_+3.3V J3/J4 A10 DAO1_DATA2 J3/J4 B17 VCC_+5V
J1/J2 B4 GND J3/J4 A11 DAO1_DATA3 J3/J4 B18 VCC_+5V
J1/J2 B5 VCC_+3.3V J3/J4 A12 DAI1_DATA0 J3/J4 B19 AUX_POWER3
J1/J2 B6 GND J3/J4 A13 DAI1_DATA1 J3/J4 B20 AUX_POWER1
J1/J2 B7 VCC_+3.3V J3/J4 A14 DAI1_DATA2

12 ©Copyright 2004 Cirrus Logic, Inc. DS651UM21
Version 2.1
CobraNet Hardware User’s Manual
Pinout and Signal Descriptions
4.2 Signal Descriptions
4.2.1 Host Port Signals
The host port is used to manage and monitor the CobraNet interface. Electrical operation
and protocol is detailed in the "Host Management Interface (HMI)" on page 23 of this
Manual.
4.2.2 Asynchronous Serial Port (UART Bridge) Signals
Level-shifting drive circuits are typically required between these signals and any external
connections.
Signal Description Direction CM-2
Pin # CS181xx Pin # Notes
HDATA[7:0] Host Data In/Out J1:A19,
A[17:11]
111, 112,
114, 115,
117, 118,
102, 121
Host port data.
HADDR[3:0] Host Address In J1:A20,
A[10:8] 105, 106, 109,110 Host port address.
HRW Host
Direction In J1:A4 107 Host port transfer direction.
HREQ Host Request Out J1:A6 140 Host port data request.
HACK Host Alert Out J1:A3 102 Host port interrupt request.
HDS Host Strobe In J1:A5 103 Host port strobe.
HEN Host Enable In J1:A7 104 Host Port Enable.
Signal Description Direction CM-2
Pin # CS181xx Pin # Notes
UART_RXD Asynchronous Serial
Receive Data In J1:A1 26 Pull-up to VCC if unused.
UART_TXD Asynchronous Serial
Transmit Data Out J1:B1 25
UART_TX_OE Transmit Drive Enable Out J1:A2 23 Enable transmit (active high) drive for two
wire multi-drop interface.

CobraNet Hardware User’s Manual
Pinout and Signal Descriptions
DS651UM21 ©Copyright 2004 Cirrus Logic, Inc. 13
Version 2.1
4.2.3 Synchronous Serial (Audio) Signals
The synchronous serial interfaces are used to bring digital audio into and out of the
system. Typically the synchronous serial is wired to ADCs and/or DACs. Detailed timing
and format is described in "Digital Audio Interface" on page 19.
4.2.4 Audio Clock Signals
See "Synchronization" on page 16 for an overview of synchronization modes and issues.
*An external multiplexor controlled by this pin is required for full MCLK_IN and MCLK out
implementation.
Signal Description Direction CM-2
Pin # CS181xx Pin # Notes
DAO1_SCLK Audio Bit Clock Out J3:A7 20
Synchronous serial bit clock.
64 FS for CS18100 (2x1 channel)
64 FS for CS18101 (2x4 channels)
128 FS for CS18102 (4x4 channels)
Typically tied to DAI1_SCLK.
DAO1_DATA[3:0] Audio Output
Data Out J3:A18, B18 15-17, 19 Output synchronous serial audio data DAO1_DATA[3:1] not used for CS18100.
DAI1_DATA[3:0] Audio Input Data In J3:
A[15:12] 131, 132, 134, 135 Input synchronous serial audio data DAI1_DATA[3:1] not used for CS18100.
DAI1_SCLK Audio Bit Clock In J4:A7 137 Should be tied to DAO1_SCLK.
Synchronous serial bit clock.
Signal Description Direction CM-2
Pin # CS181xx Pin # Notes
DAI1_LRCLK Sample clock
input In 138 Should be tied to DAO1_LRCLK for all devices.
DAO1_LRCLK
(FS1) Sample clock output Out J3:A3 22 FS1 (word clock) for CS18100 and CS18101.
DAO2_LRCLK
(FS1) Sample clock output Out J3:A3 14 FS1 (word clock) for CS18102.
REFCLK_IN Reference clock In J3:A6 97
Clock input for synchronizing network to an
external clock source, for redundancy control and
synchronization of FS divider chain to external
source. See "Synchronization" on page 16 for
more detail.
MCLK_IN Master audio
clock input In J3:A5 8* For systems featuring multiple CobraNet
interfaces operating off a common master clock.
See "Synchronization" on page 16 for more detail.
MCLK_OUT Master audio
clock output Out J3:A4 8* Low jitter 24.576 MHz master audio clock.

14 ©Copyright 2004 Cirrus Logic, Inc. DS651UM21
Version 2.1
CobraNet Hardware User’s Manual
Pinout and Signal Descriptions
4.2.5 Miscellaneous Signals
4.2.6 Power and Ground Signals
*Indicates specifications are estimates.
Signal Description Direction CM-2
Pin # CS181xx Pin # Notes
HRESET Reset In J1:A18 93 System reset (active low).
10 ns max rise time. 1 ms min assertion time.
WATCHDOG Watch Dog Out J3:A17 95
Toggles at 750 Hz nominal rate to indicate proper
operation. Period duration in excess of 200 ms
indicates hardware or software failure has occurred and
the interface should be reset. Note that improper
operation can also be indicated by short pulses
(<100 ns).
MUTE Interface
Ready Out J3:A2 92 Asserts (active low) during initialization and when a fault is detected or connection to the network is lost.
NC No Connect - -
28, 50-
53, 78-
81, 141,
142
Signal Description CM-2 Pin # CS181xx Pin # Specification
VCC_+3V System Digital +3.3 v
J1:B20, B17, B15,
B13, B11, B9, B7,
B5, B3
J3:B14, B12, B10,
B8, B6, B4, B2
N/A 3.3 ±0.3v, 0.6A*
VCC_+5V J3;B[18:17] N/A Backwards Compatibility
VDDD N/A
10, 24, 54, 66, 83,
98, 119, 130 +1.8 V @ 500mA* for Core Logic
VDDIO N/A
18, 33, 44, 60, 73,
91, 113, 136 +3.3 V @ 120mA* for I/O Logic
VDD_A N/A 129 Filtered +1.8 V @ 10mA*
AUX_POWER
[3-0] J3:B[20:19], A[20:19] N/A
GND Digital Ground
J1:B19, B16, B14,
B12, B10, B8, B6,
B4, B2
J3:B16, B15, B13,
B11, B9, B7, B5,
B3, B1
13, 21, 27, 36, 47,
57, 63, 69, 76, 86,
94, 101, 116, 122,
126, 133, 139

CobraNet Hardware User’s Manual
Pinout and Signal Descriptions
DS651UM21 ©Copyright 2004 Cirrus Logic, Inc. 15
Version 2.1
4.2.7 System Signals
Use these CS181xx signals in the manner strictly described in the CS181xx reference
design. Each signal is briefly described below.
Signal Description CS181xx Pin #
VCXO_CTRL A Delta-sigma DAC Output for Controlling the On-board VCXO 1
MCLK_SEL Control Signal for Selecting MCLK Sources 2
DBDA, DBCK I2C Debugger Interface 3, 4
TEST Used for testing during manufacturing. Keep grounded for normal
operation. 9
DATA[15:0] Data Bus for Flash & Ethernet Controller(s) 29-32, 34, 35, 37, 39-43,
45, 46, 48, 49
ADDR[19:0] Address Bus for Flash & Ethernet Controller(s) 55, 56, 58, 59, 61, 62, 64, 67, 68, 70-72, 74, 75, 77,
82, 84, 85, 87, 88
WE Write Enable for Flash and Ethernet Controller(s) 38
CS1 Chip Select for Flash Memory Device 90
CS2 Chip Select for Ethernet Controller(s) 65
OE Output Enable 89
IOWAIT Wait State Signal from Ethernet Controller(s) 96
GPIO[2:0] General-purpose I/O Signals 99, 100, 108
XTI Reference Clock Input / Crystal Oscillator Input 125
XTO Crystal Oscillator Output 124
XTAL_OUT A Buffered Version of XTI 123
FILT2, FILT1 PLL Loop Filter 127, 128
DAO_MCLK MCLK Input 8
HS[3:0] CS181xx Boot Mode Selection 11, 16, 17, 19

16 ©Copyright 2004 Cirrus Logic, Inc. DS651UM21
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CobraNet Hardware User’s Manual
Synchronization
5.0 Synchronization
Figure 3 shows clock related circuits for the CS181xx and board design (CM-2). This
circuitry allows the synchronization modes documented below to be achieved. Modes are
distinguished by different settings of the multiplexors and software elements.
Figure 3. Audio Clock Sub-system
5.1 Synchronization Modes
Clock synchronization mode for conductor and performer roles is independently
selectable via management interface variables syncConductorClock and
syncPerformerClock. The role (conductor or performer) is determined by the network
environment including the conductor priority setting of the device and theother devices on
the network. It is possible to ensure you will never assume the conductor role by selecting
a conductor priority of zero. However, it is not reasonable to assume that by setting a high
conductor priority, you will always assume the conductor role. For more information, refer
to CobraNet Programmer’s Reference Manual.
VCXO
24.576 MHz
±100 PPM
MCLK_OUT
MCLK_IN
MCLK_SEL
AClkConfig
Sample
Phase
Counter
Edge
Detect
RefClkEnable
RefClkPolarity
REFCLK
Phase
Detector Loop Filter
BeatReceived
Legend: External Software
Component
Hardware
Component
(CM2)
Internal
Hardware
Component
(CS181xx)
Audio
Clock
Generator
CS181xx
DAC
FS1
SCK

CobraNet Hardware User’s Manual
Synchronization
DS651UM21 ©Copyright 2004 Cirrus Logic, Inc. 17
Version 2.1
The following synchronization modes are further described below:
•"Internal Mode" on page 17
•"Internal Mode with External Sample Synchronization" on page 17
•"External Word Clock Mode" on page 17
•"External Master Clock Mode" on page 18
•"External Master Clock Mode with External Sample Synchronization" on
page 18
5.1.1 Internal Mode
All CobraNet clocks are derived from the onboard VCXO. The master clock generated by
the VCXO is available to external circuits via the master clock output.
Conductor—The VCXO is “parked” according to the syncClockTrim setting.
Performer—The VCXO is “steered” to match the clock transmitted by the Conductor.
5.1.2 Internal Mode with External Sample Synchronization
This mode is identical to internal mode except that it allows synchronization of derived
clocks (sample clock, audio bit clock) to an external source via the reference clock input.
This additional functionality is useful when adapting the CobraNet interface to a device
that already has circuitry for generating those clocks.
Conductor—The VCXO is “parked” according to the syncClockTrim setting.
Performer—The VCXO is “steered” to match the clock transmitted by the conductor.
5.1.3 External Word Clock Mode
All CobraNet clocks are derived from the onboard VCXO. The VCXO is steered from an
external clock supplied to the reference clock input. The clock supplied can be any
integral division of the sample clock in the range of 750Hz to 48kHz.
External synchronization lock range: ±5 µs. This specification indicates drift or wander
between the supplied clock and the generated network clock at the conductor. Absolute
phase difference between the supplied reference clock and generated sample clock is
dependant on network topology.
Conductor—This mode gives a means for synchronizing an entire CobraNet network to
an external clock.
Performer—The interface disregards the fine timing information delivered over the
network from the conductor. Coarse timing information from the conductor is still used;
fine timing information is instead supplied by the reference clock. The external clock
source must be synchronous with the network conductor. This mode is useful in
installations where a house sync source is readily available.

18 ©Copyright 2004 Cirrus Logic, Inc. DS651UM21
Version 2.1
CobraNet Hardware User’s Manual
Synchronization
5.1.4 External Master Clock Mode
The VCXO is disabled and MCLK_IN is used as the master clock for the node. This is a
“hard” synchronization mode. The supplied clock is used directly by the CobraNet
interface for all timing. This mode is primarily useful for devices with multiple CobraNet
interfaces sharing a common master audio clock. The supplied clock must be
24.576 MHz. The supplied clock must have a ±37 ppm precision.
Conductor—The entire network is synchronized to the supplied master clock.
Performer—The node will initially lock to the network clock and will “jam sync” via the
supplied master clock. The external clock source must be synchronous with the network
conductor.
5.1.5 External Master Clock Mode with External Sample Synchronization
This mode is identical to External Master Clock mode except that it allows
synchronization of the derived clocks (sample clock, audio bit clock) to an external source
via the reference clock input. This additional functionality is useful when adapting the
CobraNet interface to a device that already has circuitry for generating derived clocks of
its own.
Conductor—The entire network is synchronized to the supplied master clock.
Performer—The node will initially lock to the network clock and will “jam sync” via the
supplied master clock. The external clock source must be synchronous with the network
conductor.

CobraNet Hardware User’s Manual
DigitalAudio Interface
DS651UM21 ©Copyright 2004 Cirrus Logic, Inc. 19
Version 2.1
6.0 Digital Audio Interface
The CS18101, CS18102, and CM-2 support four bi-directional synchronous serial
interfaces. The CS18100 supports one bi-directional synchronous serial interface. All
interfaces operate in master mode with DAO1_SCLK as the bit clock and FS1 as the
frame clock. A sample period worth of synchronous serial data includes two (or four)
audio channels. CobraNet supports two synchronous serial bit rates: 48 Khz and 96 KHz.
However, 96 kHz sample rate is not available when using CS18102 with 16X16 channels.
Bit rate is selected by the modeRateControl variable. All synchronous serial interfaces
operate from a common clock at the same bit rate.
Figure 4. Channel Structure for Synchronous Serial Audio at 64FS (One Sample Period) - CS18100 & CS18101
Figure 5. Channel Structure for Synchronous Serial Audio at 128FS (One Sample Period) - CS18102
Default channel ordering is shown above. Note that the first channel always begins after
the rising or falling edge of FS1 (depending on the mode).
DAI1_SCLK period depends on the sample rate selected. Up to 32 significant bits are
received and buffered by the DSP for synchronous inputs. Up to 32 significant bits are
transmitted by the DSP for synchronous outputs. Bit 31 is always the most significant
(sign) bit. A 16-bit audio source must drive to bit periods 31-16 with audio data and bits
15-0 should be actively driven with either a dither signal or zeros. Cirrus Logic
recommends driving unused LS bits to zero.
12
FS1
DAO1_DATA0 / DAI1_DATA0
34
56
78
*
DAO1_DATA1 / DAI1_DATA1
*
DAO1_DATA2 / DAI1_DATA2
*
DAO1_DATA3 / DAI1_DATA3
* Not
p
resent in CS18100.
1 2
FS1
DAO1_DATA0 / DAI1_DATA0
5 6
910
13 14
DAO1_DATA1 / DAI1_DATA1
DAO1_DATA2 / DAI1_DATA2
DAO1_DATA3 / DAI1_DATA3
3 4
7 8
11 12
15 16

20 ©Copyright 2004 Cirrus Logic, Inc. DS651UM21
Version 2.1
CobraNet Hardware User’s Manual
Digital Audio Interface
Although data is always transmitted and received with a 32-bit resolution by the
synchronous serial ports, the resolution of the data transferred to/from the Ethernet may
be less. Incoming audio data is truncated to the selected resolution. Unused least
significant bits on outgoing data is zero filled.
6.1 Digital Audio Interface Timing
Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1
An DAO1_SCLK edge follows an MCLK_OUT edge by 0.0 to 5.0ns. An FS1 edge follows
a MCLK_OUT edge by 0.0 to 10.0ns.
Note: The DAO1_SCLK and FS1 might be synchronized with the either the falling edge or
the rising edge of MCLK_OUT. Which edge is impossible to predict since it depends
on power up timing.
Figure 7. Serial Port Data Timing Overview
Setup times for DAI1_DATAx and FS1 are 5.0 ns with a hold time of 0.0 ns with respect to
the DAI1_SCLK edge. Clock to output times for DAO1_DATAx is 0.0 to 12.0 ns from the
edge of DAO1_SCLK.
MCLK_OUT
DAO1_SCLK
FS1
0
–
5ns
0
–
10ns
DAI1_DATAx
DAO1_SCLK
0
–
12ns
DAO1_DATAx
≥5ns ≥0ns