Modulated signal
amplitude
16-bit amplitude scaling factor for the
modulated signal.
The maximum level should be adjusted to
prevent saturation. Saturation can easily be
checked by visualizing the input signal
using ComScope.
REG29 = LSB
REG30 = MSB
Output center
frequency (fc)
Fixed frequency offset applied to the
output samples.
32-bit signed integer (2’s complement
representation) expressed as
fc * 232 fclk_p
REG81 (LSB) – REG78 (MSB)
Spectrum
inversion
Invert Q bit
0 = off
1 = on
REG61(0)
BPSK SQPN 0 = BPSK
1 = SQPN
REG61(1)
SQPN
single double
source
0 = different data on I and Q channels
(including the case when bits of a single
input bit stream are sent alternatively to the
I Q channels). Independent symbol rates on
I Q channels. Uses two FEC encoders.
1 = identical data on I and Q channels.
Uses one FEC encoder
REG61(2)
Alternating I Q
bits
When enabled, the input data stream is
demultiplexed into the I and Q paths. The
symbol rate must be identical on both I and
Q channels. Two independent FEC
encoders are used on the I and Q paths
respectively.
Enabled(1) Disabled(0)
REG60(7)
½ symbol delay
on the Q path
A ½ symbol delay can be added to the Q
modulator path
Enabled(1) Disabled(0)
REG60(6)
Data format
converter
Data format conversion from the NRZ-L
input to NRZ-L M S format prior to the
FEC encoder.
0 = NRZ-L to NRZ-L
1 = NRZ-L to NRZ-M
2 = NRZ-L to NRZ-S
REG61(5:3)
Convolutional
FEC encoding Disable (0) Enable (1)
REG61(6)
Additive White
Gaussian Noise
gain
16-bit amplitude scaling factor for additive
white Gaussian noise.
Because of the potential for saturation,
please check for saturation when changing
this parameter. Saturation can easily be
checked by visualizing the input signal
using ComScope.
REG31 = LSB
REG32 = MSB
External
transmitter gain
control
When using an external transceiver such as
the COM-350x family, the transmitter gain
can be controlled through the
TX_GAIN_CNTRL1 analog output signal.
Range 0 – 3.3V.
REG59: LSB, REG60(3:0): MSb
TX_ENB
control
The TX_ENB signal at the interface
controls the RF transmit circuit.
0 = off
1 = on
REG60(4)
etwork Interface
Parameters Configuration
MAC addresses LSB In order to ensure the uniqueness of
MAC addresses, users can define bits
7:1 through REG236(7:1).
The MAC addresses upper bits are
automatically tied to the nearly unique
FPGA DNA_ID. MAC address bit 0 is
either 0 (LAN1) or 1 (LAN2).
REG236(7:1).
IP1 multicast address
(LAN xB connector
on backpanel)
4-byte IPv4 address used for SDDS
input stream.
Example : 0x E1 00 00 01 designates
address 225.0.0.1
Use 0.0.0.0 to signify that multicasting
is not supported.
REG33 (MSB) – REG36 (LSB)
IP1 static address
(LAN xB connector
on backpanel)
4-byte IPv4 address used for SDDS
input stream.
Example : 0x AC 10 01 80 designates
address 172.16.1.128
The new address becomes effective
immediately (no need to reset the
ComBlock).
REG37 (MSB) - REG40 (LSB)
IP2 address (LAN xA
connector on
backpanel)
4-byte IPv4 address used for receiver
output, modulator inputs and
monitoring and control.
Example : 0x AC 10 01 80 designates
address 172.16.1.128
The new address becomes effective
immediately (no need to reset the
ComBlock).
REG41 (MSB) - REG44 (LSB)
Destination IP
address
4-byte IPv4 address
Destination IP address for UDP frames
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