Computex PALMiCE3 ARM JTAG200 Manual

Oct. 30, 2018
This document consists of the following contents.
●Technical Information on JTAG / SWD / SWV / ETM ARM-related
Target Interface (Sixth Edition)
Refer this document before using PALMiCE3-ARM.
●PALMiCE3 JTAG200 model Hardware Manual (Sixth Edition)
Target interface Specifications on PALMiCE3 side.

Technical Information
ARM-related
JTAG / SWD / SWV / ETM Target Interfaces
Sixth Edition (Oct. 30, 2018)
Copyright (C)2009 Computex Co., Ltd.
Table of Contents
●Technical Information on JTAG / SWD / SWV / ETM ARM-related Target Interface
(Sixth Edition)
Document change history ............................................................................................................................................ 1
Supported connectors................................................................................................................................................... 2
Applicable products...................................................................................................................................................... 2
Technical Information reference chart 1 ..................................................................................................................... 3
Technical Information reference chart 2 ..................................................................................................................... 3
Product purchase chart................................................................................................................................................ 4
■20-pin 2.54mm-pitch connector .............................................................................................................................. 5
■20-pin 1.27mm-pitch connector .............................................................................................................................. 6
■10-pin 1.27mm-pitch connector .............................................................................................................................. 8
■38-pin Mictor connector .......................................................................................................................................... 9

1
Document change history
First Edition
Sep. 11, 2009
Initial edition
Second Edition
Nov. 13, 2009
・
Added the descriptions on CPU core "ARM" and "PALMiCE3 ARM (JTAG200)" to Technical
Information reference chart and Product purchase chart.
・Corrected the Product purchase chart.
Technical Information ④and ⑥correspond to PALMiCE3 CM3 (ETM200) only.
However, PALMiCE3 CM3(ETM200) is a product to be released in the future.
・Added the note on SRST signal in respective signal tables.
”SRST signal is an open-collector output."
Third Edition
Mar. 04, 2011
・
PALMiCE3 CM3(ETM200) has already been released (Dec. 2009).
Deleted the following description:
”To be released in the future.”
・“Supported connectors”
Added graphic images of the connectors.
・“Product purchase chart”
Added graphic images of the optional products.
・Added the note on SRST signal in respective signal tables.
・Changed the note on TRST signal in respective signal tables.
・Deleted CPU core options from Technical Information reference chart and Product purchase
chart.
For supported CPUs, refer to Product Summary of respective products up on our website.
・Deleted the description of the case where ETM is not used and half-pitch (1.27mm) connector is
used.
When you use them, please contact us.
Fourth Edition
Sep. 18, 2015
・
Added an item to Applicable products:
PALMiCE2H ARM (ETM383)
・Following addition of an item to Applicable products mentioned above, added the description on
PALMiCE2H to Technical Information reference chart and Product purchase chart.
・Following addition of an item to Applicable products mentioned above, added ⑦⑧⑨⑩ to pages
on target interface details.
・Placed specifications of the target interface on the debugger side.
PALMiCE3 PALMiCE3 JTAG200 model Hardware Manual)
PALMiCE2H Extracted from PALMiCE2H ARM User's Manual)
・Supported connectors – 38-pin Mictor connector
Changed the recommended connectors.
[Before change] 2-767004-2 / 767054-1 / 767061 (* RoHS-non-compliant products)
[After change] 2-5767004-2 / 5767054-1 / 5767061-1 (*RoHS-compliant products)
・Supported connectors
Added the note.
・Product purchase chart
Added ”PALMiCE3-ARM (JTAG200)” to ⑦to ⑩.
・Added notes on the TRST signal described in ②(Using 20-pin 2.54 mm-pitch connector +
JTAG interface).
・Added ⑥(Using 20-pin 1.27 mm-pitch connector + JTAG interface).
・According to the above addition, incremented the heading number ⑥and subsequent numbers
by one.
・In accordance with J-STICK sales termination, deleted J-STICK descriptions from the applicable
products and the product purchase chart.
Fifth Edition
Mar. 04, 2016
・
In accordance with PALMiCE3 CM3(ETM200) sales termination, deleted PALMiCE3
CM3(ETM200) descriptions from the applicable products and the product purchase chart.
・Product purchase chart
Added “PALMiCE3 CM3(JTAG200)” to ①, ②, ③, ⑥, ⑦, ⑧, ⑨, ⑩and ⑪.
・Added an item to Applicable products:
PALMiCE3 CM3(JTAG200)
・
Added a note that SWO signal is unused in
①
,
③
and
⑦
.
Sixth Edition
Oct. 30,2018
・
Updated Table of contents
・About ②, ⑥, ⑪
・Annotation added for TRST, SRST signals
・TRST signal related changes in the Target connection reference diagram
・Reference note added for RZ/A and RZ/T series /SRST, /TRST signals
・Added ⑧(Using 10-pin 1.27 mm-pitch connector + JTAG interface).
・According to the above addition, incremented the heading number ⑧and subsequent numbers
by one.

Technical Information on JTAG / SWD / SWV / ETM ARM-related Target Interface Oct. 30, 2018 (Sixth Edition)
2
Supported connectors
(For detailed dimensions of the connectors, refer to the documentations by respective manufacturers of the connectors.)
20-pin 2.54mm-pitch connector
(Top view on the target board)
Recommended connector
Manufacturer: OMRON Corporation
Model : XG4C-2031
20-pin 1.27mm-pitch connector
(Top view on the target board)
Recommended connector
Manufacturer: Samtec, Inc.
Model : FTSH-110-01-L-DV-K
10-pin 1.27mm-pitch connector
(Top view on the target board)
Recommended connector
Manufacturer: Samtec, Inc.
Model : FTSH-105-01-L-DV-K
38-pin Mictor connector
(Top view on the target board)
Recommended connector
Manufacturer: AMP
Model : Mictor connector
2-5767004-2 / 5767054-1 / 5767061-1
* Please look at the pin configuration diagram and make sure that the connector is in the right
direction before connecting.
Moreover, please check the pin number in the corresponding signal table and make sure the signal and the pin
numbers match.
Applicable products
This manual is applicable for the following products.
PALMiCE3 ARM (JTAG200)
PALMiCE3 CM3 (JTAG200)
PALMiCE2H ARM (ETM383)

Technical Information on JTAG / SWD / SWV / ETM ARM-related Target Interface Oct. 30, 2018 (Sixth Edition)
3
Technical Information reference chart 1
Depending on the target interface you use, Technical Information you should refer to will be different.
Based on the chart below, consult the applicable Technical Information.
Debugging
interface
ETM
SWV
Choose a connector to be
implemented on the target system
Technical
Information No.
JTAG USE ETM 20-pin 1.27mm-pitch connector
⑤
38-pin Mictor connector
To Technical Information reference chart 2
NOT USE ETM 20-pin 2.54mm-pitch connector
②
20-pin 1.27mm-pitch connector
⑥
10-pin 1.27mm-pitch connector
⑧
SWD USE ETM 20-pin 1.27mm-pitch connector
④
USE SWV 20-pin 2.54mm-pitch connector
①
Neither use
ETM nor SWV
20-pin 1.27mm-pitch connector
③
10-pin 1.27mm-pitch connector
⑦
*: Only those combinations available for selection are given. For other combinations, please contact us.
Technical Information reference chart 2
Debugging
interface ETM SWV
Choose a connector to
be implemented on the
target system
JTAG
USE ETM
38-pin Mictor connector
CPU core Mode Technical Information
No.
ARM7, ARM9 Normal mode
⑨
Demultiplex mode
⑩
Multiplex mode
⑪
ARM11, Cortex
⑫
*: Only those combinations available for selection are given.

Technical Information on JTAG / SWD / SWV / ETM ARM-related Target Interface Oct. 30, 2018 (Sixth Edition)
4
Product purchase chart
Depending on the target interface you use, the composition of product and optional product you should purchase will differ.
Based on the Technical Information No. (See "Technical Information reference chart" on the previous page), choose the product.
*: Only those products available for selection are given.
*1 : For the CPUs supported by respective products, refer to Product Summary of respective products up on Computex website.
Technical
Information No.
Product name *1
Required optional
product
①
PALMiCE3 ARM (JTAG200)
PALMiCE3 ARM64 (JTAG200)
PALMiCE3 CM3 (JTAG200)
②
PALMiCE3 ARM (JTAG200)
PALMiCE3 ARM64 (JTAG200)
PALMiCE3 CM3 (JTAG200)
PALMiCE2H ARM (ETM383)
＋
ADP-ETM-JTAG20
③
PALMiCE3 ARM (JTAG200)
＋
SWJ-PRB-MIL20-20HP
PALMiCE3 ARM64 (JTAG200)
＋
SWJ-PRB-MIL20-20HP
PALMiCE3 CM3 (JTAG200)
＋
SWJ-PRB-MIL20-20HP
PALMiCE2H ARM (ETM383)
④
PALMiCE2H ARM (ETM383)
⑤
⑥
PALMiCE3 ARM (JTAG200)
＋
SWJ-PRB-MIL20-20HP
PALMiCE3 ARM64 (JTAG200)
＋
SWJ-PRB-MIL20-20HP
PALMiCE3 CM3 (JTAG200)
＋
SWJ-PRB-MIL20-20HP
⑦
PALMiCE3 ARM (JTAG200)
＋
SWJ-PRB-MIL20-10HP
⑧
PALMiCE3 ARM64 (JTAG200)
＋
SWJ-PRB-MIL20-10HP
PALMiCE3 CM3 (JTAG200)
＋
SWJ-PRB-MIL20-10HP
⑨
PALMiCE2H ARM (ETM383)
⑩
PALMiCE3 ARM (JTAG200)
＋
ADP-JTAG20-ETM
⑪
PALMiCE3 CM3 (JTAG200)
＋
ADP-JTAG20-ETM
⑫
PALMiCE2H ARM (ETM383)
PALMiCE3 ARM (JTAG200)
＋
ADP-JTAG20-ETM
PALMiCE3 ARM64 (JTAG200)
＋
ADP-JTAG20-ETM
PALMiCE3 CM3 (JTAG200)
＋
ADP-JTAG20-ETM

Technical Information on JTAG / SWD / SWV / ETM ARM-related Target Interface Oct. 30, 2018 (Sixth Edition)
5
■
20-pin 2.54mm-pitch connector
Target connector specifications
(Top view on the target board)
Recommended connector
Manufacturer: OMRON Corporation
Model: XG4C-2031
(For detailed dimensions of the connector, refer to the documentation by manufacturer of the connector.)
*Please look at the pin configuration diagram above and make sure that the connector is in
the right direction before connecting.
Please check the pin number in the signal table above and make sure the signal and the pin
numbers match.
①
SWD interface
Signals
Pin
No.
Signal
Input/
Output
*1
Pin
No.
Signal
Input/
Output
*1
1
VTref
Output
2
TVDD*3
Output
3
NC
4
GND
5
NC
6
GND
7
SWDIO
Input/Output
8
GND
9
SWCLK
Input
10
GND
11
NC
12
GND
13
SWO*4
Output
14
GND
15
SRST*2
16
GND
17
NC
18
GND
19
NC
20
GND
*1: Input/output is based on the target system.
*2: SRST signal is an open-collector output.
Establish wired-OR connection to "power-on-reset" or "system
reset" on the target system, or if wired-OR circuit is not available,
connect with OR circuit.
*3: The signal is not used by Computex-made debugger; it can be left
unconnected.
*4: If the SWV(Serial Wire Viewer) is not used for debugging or the CPU
does not support the SWV, do not connect anything to the SWO
signal.
Target connection reference diagram
This interface does not use TRST. If the target CPU presents a pin specifically for TRST, pull it up with 10K ohmic value.
Keep the length of wirings from CPU to the target connector as short as possible. If the length gets long, it could possibly be a factor contributing to
malfunction.
②
JTAG interface
Signals
Target connection reference diagram
Pin
No.
Signal
Input/
Output
*1
Pin
No.
Signal
Input/
Output
*1
1
VTref
Output
2
TVDD*5
Output
3
TRST*6 *7
Input
4
GND
5
TDI
Input
6
GND
7
TMS
Input
8
GND
9
TCK
Input
10
GND
11
RTCK*2
Output
12
GND
13
TDO
Output
14
GND
15
SRST*3 *7
Input
16
GND
17
DBGRQ*4
Input
18
GND
19
DBGACK*4
Output
20
GND
*1: Input/output is based on the target system.
*2: If the CPU does not present the pin or if you do not use RTCK,
leave it as N.C..
*3: SRST signal is an open-collector output.
Establish wired-OR connection to "power-on-reset" or "system
reset" on the target system, or if wired-OR circuit is not available,
connect with OR circuit.
*4: In the CPUs that do not present this signal, leave the pin
unconnected in open state.
*5: The signal is not used by Computex-made debugger; it can be left
unconnected.
*6: In come CPUs, a pulldown many be necessary. Refer the CPU
datasheet and make the necessary pull up/pull down changes if
required.
*7: Refer to the reference diagram [Reference：RZ/A and RZ/T series
/SRST, /TRST reference diagram] for SRST and TRST signals for
Renesas electronics RZ/A and RZ/T series.
Keep the length of wirings from CPU to the target connector as short as possible. If the length gets long, it could possibly be a factor contributing to
malfunction.

Technical Information on JTAG / SWD / SWV / ETM ARM-related Target Interface Oct. 30, 2018 (Sixth Edition)
6
■
20-pin 1.27mm-pitch connector
Target connector specifications
(Top view on the target board)
Recommended connector
Manufacturer: Samtec, Inc.
Model: FTSH-110-01-L-DV-K
(For detailed dimensions of the connector, refer to the documentation by manufacturer of the connector.)
*Please look at the pin configuration diagram above and make sure that the connector is in
the right direction before connecting.
Please check the pin number in the signal table above and make sure the signal and the pin
numbers match.
③
SWD interface
Signals
Pin
No.
Signal
Input/
Output
*1
Pin
No.
Signal
Input/
Output
*1
1
Vtref
Output
2
SWDIO
Input/Output
3
GND
4
SWCLK
Input
5
GND
6
SWO*4z
Output
7
Key*3
8
NC
9
GND
10
SRST*2
Input
11
GND
12
NC
13
GND
14
NC
15
GND
16
NC
17
GND
18
NC
19
GND
20
NC
*1: Input/output is based on the target system.
*2: SRST signal is an open-collector output.
Establish wired-OR connection to "power-on-reset" or "system
reset" on the target system, or if wired-OR circuit is not available,
connect with OR circuit.
*3: "Key" is intended for protection against wrong insertion.
*4: If the SWV(Serial Wire Viewer) is not used for debugging or the
CPU does not support the SWV, do not connect anything to the
SWO signal.
Target connection reference diagram
This interface does not use TRST.
If the target CPU presents a pin specifically for TRST, pull it up with 10K ohmic value.
Keep the length of wirings from CPU to the target connector as short as possible. If the length gets long, it could possibly be a factor contributing to
malfunction.
④
SWD interface + Trace
Signals
Pin
No.
Signal
Input/
Output
*1
Pin
No.
Signal
Input/
Output
*1
1
Vtref
Output
2
SWDIO
Input/Output
3
GND
4
SWCLK
Input
5
GND
6
SWO
*2
Output
7
Key
*5
8
NC
Input
9
GND
10
SRST*3
Input
11
GND
12
TraceClk
Output
13
GND
14
TraceD0/SWO*4
Output
15
GND
16
TraceD1
Output
17
GND
18
TraceD2
Output
19
GND
20
TraceD3
Output
*1: Input/output is based on the target system.
*2: Connect the signal dedicated to SWO. The pin can be left N.C. if you
are using Pin No. 14 as SWO (See *4).
*3: SRST signal is an open-collector output.
Establish wired-OR connection to "power-on-reset" or "system reset"
on the target system, or if wired-OR circuit is not available, connect
with OR circuit.
*4: In some CPUs, SWO and TraceD0 are multiplexed.
In the case of such pin, connect SWO signal not to Pin No. 6 but to Pin
No.14 even when you intend to use Pin No. 14 as SWO, not as
TraceD0.
*5: "Key" is intended for protection against wrong insertion.
Target connection reference diagram
This interface does not use TRST.
If the target CPU presents a pin specifically for TRST, pull it up with 10K ohmic value.
Keep the length of wirings from CPU to the target connector as short as possible. If the length gets long, it could possibly be a factor contributing to
malfunction.

Technical Information on JTAG / SWD / SWV / ETM ARM-related Target Interface Oct. 30, 2018 (Sixth Edition)
7
⑤
JTAG interface + Trace
Signals
Pin
No.
Signal
Input/
Output
*1
Pin
No.
Signal
Input/
Output
*1
1
Vtref
Output
2
TMS
Input/Output
3
GND
4
TCK
Input
5
GND
6
TDO
Output
7
Key*3
8
TDI
Input
9
GND
10
SRST*2
Input
11
GND
12
TraceClk
Output
13
GND
14
TraceD0
Output
15
GND
16
TraceD1
Output
17
GND
18
TraceD2
Output
19
GND
20
TraceD3
Output
*1: Input/output is based on the target system.
*2: SRST signal is an open-collector output.
Establish wired-OR connection to "power-on-reset" or "system reset"
on the target system, or if wired-OR circuit is not available, connect
with OR circuit.
*3: "Key" is intended for protection against wrong insertion.
Target connection reference diagram
This interface does not use TRST.
If the target CPU presents a pin specifically for TRST, pull it up with 10K ohmic value.
Keep the length of wirings from CPU to the target connector as short as possible. If the length gets long, it could possibly be a factor contributing to
malfunction.
⑥
JTAG interface
Signals
Pin
No.
Signal
Input/
Output
*1
Pin
No.
Signal
Input/
Output
*1
1
Vtref
Output
2
TMS
Input/Output
3
GND
4
TCK
Input
5
GND
6
TDO
Output
7
Key
*3
8
TDI
Input
9
GND
10
SRST
*2 *6
Input
11
GND
12
NC
13
GND
14
RTCK*4
Output
15
GND
16
TRST*5 *6
Input
17
GND
18
NC
19
GND
20
NC
*1: Input/output is based on the target system.
*2: SRST signal is an open-collector output.
Establish wired-OR connection to "power-on-reset" or "system reset"
on the target system, or if wired-OR circuit is not available, connect
with OR circuit.
*3: "Key" is intended for protection against wrong insertion.
*4: If the CPU does not present the pin or if you do not use RTCK, leave
it as N.C..
*5: In come CPUs, a pulldown many be necessary. Refer the CPU
datasheet and make the necessary pull up/pull down changes if
required.
*6: Refer to the reference diagram [Reference：RZ/A and RZ/T series
/SRST, /TRST reference diagram] for SRST and TRST signals for
Renesas electronics RZ/A and RZ/T series.
Target connection reference diagram
Keep the length of wirings from CPU to the target connector as short as possible. If the length gets long, it could possibly be a factor contributing to
malfunction.

Technical Information on JTAG / SWD / SWV / ETM ARM-related Target Interface Oct. 30, 2018 (Sixth Edition)
8
■
10-pin 1.27mm-pitch connector
Target connector specifications
(Top view on the target board)
Recommended connector
Manufacturer:Samtec, Inc.
Model: FTSH-105-01-L-DV-K
(For detailed dimensions of the connector, refer to the documentation by manufacturer of the connector.)
*Please look at the pin configuration diagram above and make sure that the connector is in
the right direction before connecting.
Please check the pin number in the signal table above and make sure the signal and the pin
numbers match.
⑦
SWD interface
Signals
Pin
No.
Signal
Input/
Output
*1
Pin
No.
Signal
Input/
Output
*1
1
VTref
Output
2
SWDIO
Input/Output
3
GND
4
SWCLK
Input
5
GND
6
SWO*4
Output
7
Key*3
8
NC
Input
9
GND
10
SRST*2
Input
*1: Input/output is based on the target system.
*2: SRST signal is an open-collector output.
Establish wired-OR connection to "power-on-reset" or "system
reset" on the target system, or if wired-OR circuit is not available,
connect with OR circuit.
*3: "Key" is intended for protection against wrong insertion.
*4: If the SWV(Serial Wire Viewer) is not used for debugging or the
CPU does not support the SWV, do not connect anything to the
SWO signal.
Target connection reference diagram
This interface does not use TRST.
If the target CPU presents a pin specifically for TRST, pull it up with 10K ohmic value.
Keep the length of wirings from CPU to the target connector as short as possible. If the length gets long, it could possibly be a factor contributing to
malfunction.
⑧
JTAG interface
Signals
Pin
No.
Signal
Input/
Output
*1
Pin
No.
Signal
Input/
Output
*1
1
Vtref
Output
2
TMS
Input/Output
3
GND
4
TCK
Input
5
GND
6
TDO
Output
7
Key*3
8
TDI
Input
9
GND
10
SRST*2
Input
*1: Input/output is based on the target system.
*2: SRST signal is an open-collector output.
Establish wired-OR connection to "power-on-reset" or "system reset"
on the target system, or if wired-OR circuit is not available, connect
with OR circuit.
*3: "Key" is intended for protection against wrong insertion.
Target connection reference diagram
Keep the length of wirings from CPU to the target connector as short as possible. If the length gets long, it could possibly be a factor contributing to
malfunction.

Technical Information on JTAG / SWD / SWV / ETM ARM-related Target Interface Oct. 30, 2018 (Sixth Edition)
9
■
38-pin Mictor connector
Target connector specifications
(Top view on the target board)
Recommended connector
Manufacturer :AMP
Model : Mictor connector
2-767004-2 / 767054-1 / 767061
In mounting ETM connector, place it to the position as close as
possible to CPU so that wiring pattern length will be minimized.
Also in mounting JTAG connector, place it to the position close to
ETM connector.
In addition, you will need to
connect the Grand Bus
Leads of ETM connector to
the GND.
(For detailed dimensions of the connector, refer to the documentation by manufacturer of the connector.)
*Please look at the pin configuration diagram above and make sure that the connector is in the right direction
before connecting.
Please check the pin number in the signal table above and make sure the signal and the pin numbers
match.
⑨
JTAG interface + ETM - Normal mode
Signals
Pin
No.
Signal
Input/
Output
*1
Pin
No.
Signal
Input/
Output
*1
1
NC
2
NC
3
NC
4
NC
5
GND
6
TRACECLK
Output
7
DBGRQ*2
Input
8
DBGACK*2
Output
9
SRST*3
Input
10
EXTTRIG*5
Input
11
TDO
Output
12
VTref
Output
13
RTCK*4
Output
14
TVDD*6
Output
15
TCK
Input
16
TRACEPKT7*8*9
Output
17
TMS
Input
18
TRACEPKT6*8*9
Output
19
TDI
Input
20
TRACEPKT5*8*9
Output
21
TRST*7
Input
22
TRACEPKT4*8*9
Output
23
TRACEPKT15*8*9
Output
24
TRACEPKT3*8*9
Output
25
TRACEPKT14*8*9
Output
26
TRACEPKT2*8*9
Output
27
TRACEPKT13*8*9
Output
28
TRACEPKT1*8*9
Output
29
TRACEPKT12*8*9
Output
30
TRACEPKT0*8*9
Output
31
TRACEPKT11*8*9
Output
32
TRACESYNC
Output
33
TRACEPKT10*8*9
Output
34
PIPESTAT2*9
Output
35
TRACEPKT9*8*9
Output
36
PIPESTAT1*9
Output
37
TRACEPKT8*8*9
Output
38
PIPESTAT0*9
Output
*1: Input/output is based on the target system.
*2: In the CPUs that do not present this signal, leave the pin unconnected in open
state.
*3: SRST signal is an open-collector output.
Establish wired-OR connection to "power-on-reset" or "system reset" on the
target system, or if wired-OR circuit is not available, connect with OR circuit.
*4: If the CPU does not present the pin or if you do not use RTCK, leave it as
N.C..
*5: The signal is not used by Computex-made debugger.
*6: The signal is not used by Computex-made debugger; it can be left
unconnected.
*7: If the target CPU presents a pin specifically for TRST, pull it up with 10K
ohmic value.
*8: If the trace data is of 4-bit, connect signals TRACEPKT4 - 15, or if of 8-bit, connect
signals TRACEPKT8 - 15, to GND.
*9: For the names of signals corresponding to respective pin No., see the table of
Signals.
Target connection reference diagram
Keep the length of wirings from CPU to the target connector as short as possible. If the length gets long, it could possibly be a factor contributing to
malfunction.

Technical Information on JTAG / SWD / SWV / ETM ARM-related Target Interface Oct. 30, 2018 (Sixth Edition)
10
⑩
JTAG interface + ETM – Demultiplex mode
Signals
Pin
No.
Signal
Input/
Output
*1
Pin
No.
Signal
Input/
Output
*1
1
NC
2
NC
3
NC
4
NC
5
GND
6
TRACECLK
Output
7
DBGRQ *2
Input
8
DBGACK *2
Output
9
SRST*3
Input
10
EXTTRIG *4
Input
11
TDO
Output
12
VTref
Output
13
RTCK *5
Output
14
TVDD *6
Output
15
TCK
Input
16
NC
17
TMS
Input
18
NC
19
TDI
Input
20
NC
21
TRST *7
Input
22
NC
23
TRACEPKTB3*8
Output
24
TRACEPKTA3*8
Output
25
TRACEPKTB2*8
Output
26
TRACEPKTA2*8
Output
27
TRACEPKTB1*8
Output
28
TRACEPKTA1*8
Output
29
TRACEPKTB0*8
Output
30
TRACEPKTA0*8
Output
31
TRACESYNCB*8
Output
32
TRACESYNCA*8
Output
33
PIPESTATB2*8
Output
34
PIPESTATA2*8
Output
35
PIPESTATB1*8
Output
36
PIPESTATA1*8
Output
37
PIPESTATB0*8
Output
38
PIPESTATA0*8
Output
*1: Input/output is based on the target system.
*2: In the CPUs that do not present this signal, leave the pin unconnected in open
state.
*3: SRST signal is an open-collector output.
Establish wired-OR connection to "power-on-reset" or "system reset" on the
target system, or if wired-OR circuit is not available, connect with OR circuit.
*4: The signal is not used by Computex-made debugger.
*5: f the CPU does not present the pin or if you do not use RTCK, leave it as
N.C..
*6: The signal is not used by Computex-made debugger; it can be left
unconnected.
*7: If the target CPU presents a pin specifically for TRST, pull it up with 10K
ohmic value.
*8: For the names of signals corresponding to respective pin No., see the table of
Signals.
Target connection reference diagram
Keep the length of wirings from CPU to the target connector as short as possible. If the length gets long, it could possibly be a factor contributing to
malfunction.

Technical Information on JTAG / SWD / SWV / ETM ARM-related Target Interface Oct. 30, 2018 (Sixth Edition)
11
⑪
JTAG interface + ETM – Multiplex mode
Signals
Pin
No.
Signal
Input/
Output
*1
Pin
No.
Signal
Input/
Output
*1
1
NC
2
NC
3
NC
4
NC
5
GND
6
TRACECLK
Output
7
DBGRQ*2
Input
8
DBGACK*2
Output
9
SRST*3
Input
10
EXTTRIG*4
Input
11
TDO
Output
12
VTref
Output
13
RTCK*5
Output
14
TVDD*6
Output
15
TCK
Input
16
NC
17
TMS
Input
18
NC
19
TDI
Input
20
TRACEPKT[14,15] *8
Output
21
TRST*7
Input
22
TRACEPKT[12,13] *8
Output
23
NC
24
TRACEPKT[10,11] *8
Output
25
NC
26
TRACEPKT[8,9] *8
Output
27
NC
28
TRACEPKT[6,7] *8
Output
29
NC
30
TRACEPKT[4,5] *8
Output
31
NC
32
TRACEPKT[0,3] *8
Output
33
NC
34
PIPESTAT2+TRACEPKT2*8
Output
35
NC
36
PIPESTAT1+TRACEPKT1*8
Output
37
NC
38
PIPESTAT0+TRACESYNC
Output
*1: Input/output is based on the target system.
*2: In the CPUs that do not present this signal, leave the pin unconnected in open
state.
*3: SRST signal is an open-collector output.
Establish wired-OR connection to "power-on-reset" or "system reset" on the target
system, or if wired-OR circuit is not available, connect with OR circuit.
*4: The signal is not used by Computex-made debugger.
*5: f the CPU does not present the pin or if you do not use RTCK, leave it as N.C..
*6: The signal is not used by Computex-made debugger; it can be left unconnected.
*7: If the target CPU presents a pin specifically for TRST, pull it up with 10K ohmic
value.
*8: For the names of signals corresponding to respective pin No., see the table of
Signals.
Target connection reference diagram
Keep the length of wirings from CPU to the target connector as short as possible. If the length gets long, it could possibly be a factor contributing to
malfunction.

Technical Information on JTAG / SWD / SWV / ETM ARM-related Target Interface Oct. 30, 2018 (Sixth Edition)
12
⑫
JTAG interface + ETM / PTM
Signals
Pin
No.
Signal
Input/
Output
*1
Pin
No.
Signal
Input/
Output
*1
1
NC
2
NC
3
NC
4
NC
5
GND
6
TRACECLK
Output
7
DBGRQ*2
Input
8
DBGACK*2
Output
9
SRST*3 *8
Input
10
EXTTRIG*4
Input
11
TDO
Output
12
VTref
Output
13
RTCK*5
Output
14
TVDD*6
Output
15
TCK
Input
16
TRACEDATA[7] *9
Output
17
TMS
Input
18
TRACEDATA[6] *9
Output
19
TDI
Input
20
TRACEDATA[5] *9
Output
21
TRST*7 *8
Input
22
TRACEDATA[4] *9
Output
23
TRACEDATA[15]*9
Output
24
TRACEDATA[3] *9
Output
25
TRACEDATA[14]*9
Output
26
TRACEDATA[2] *9
Output
27
TRACEDATA[13]*9
Output
28
TRACEDATA[1] *9
Output
29
TRACEDATA[12]*9
Output
30
Logic0
Output
31
TRACEDATA[11] *9
Output
32
Logic0
Output
33
TRACEDATA[10]*9
Output
34
Logic1
Output
35
TRACEDATA[9] *9
Output
36
TRACECTL
Output
37
TRACEDATA[8] *9
Output
38
TRACEDATA[0] *9
Output
*1: Input/output is based on the target system.
*2: In the CPUs that do not present this signal, leave the pin unconnected in
open state.
*3: SRST signal is an open-collector output.
Establish wired-OR connection to "power-on-reset" or "system reset" on
the target system, or if wired-OR circuit is not available, connect with OR
circuit.
*4: The signal is not used by Computex-made debugger.
*5: If the CPU does not present the pin or if you do not use RTCK, leave it
as N.C..
*6: The signal is not used by Computex-made debugger; it can be left
unconnected.
*7: In come CPUs, a pulldown many be necessary. Refer the CPU datasheet
and make the necessary pull up/pull down changes if required.
*8: Refer to the reference diagram [Reference：RZ/A and RZ/T series /SRST,
/TRST reference diagram] for SRST and TRST signals for Renesas
electronics RZ/A and RZ/T series.
*9: For the names of signals corresponding to respective pin No., see the
table of Signals.
Target connection reference diagram
Keep the length of wirings from CPU to the target connector as short as possible. If the length gets long, it could possibly be a factor contributing to
malfunction.

Technical Information on JTAG / SWD / SWV / ETM ARM-related Target Interface Oct. 30, 2018 (Sixth Edition)
13
Reference
：
RZ/A and RZ/T series /SRST, /TRST reference diagram
It may be required to control the RES and TRST CPU pins so that they are in low state at power on. Refer the
CPU datasheet for details.

Technical Information on JTAG / SWD / SWV / ETM ARM-related Target Interface Oct. 30, 2018 (Sixth Edition)
Technical Information on JTAG / SWD / SWV / ETM ARM-related Target Interface (Sixth Edition)
Go through the required procedures as stated under Foreign Exchange and Foreign Trade Control Law in exporting (including the case where
travellers directly carry) this product or providing this product for residents outside Japan.
No part of this manual, whether in whole or in part, may be adapted, copied or reproduced without prior permission.
The content of and the specifications of this product are subject to change without prior notice.
Computex Co., Ltd. shall not be held liable for any loss or damage arising from the use of this product although all possible measures have been
taken by Computex Co., Ltd. in good faith to ensure the quality of the product.
Contact us for any questions, feedback, comments, requests or anything of concern to you (or in the event of malfunction) regarding this product or
misprinting or missing information within this manual.
Other names of CPUs etc. mentioned in this manual are trademarks or registered trademarks of their respective manufacturers.
PALMiCE, J-STICK and COMPUTEX are registered trademarks of Computex Co., Ltd. in Japan.

PALMiCE3 JTAG200 model
Hardware Manual
(Sixth Edition)
Copyright (C) 2009 Computex Co., Ltd.

Precautions For Use
Read the following thoroughly before attempting to use the product.
In the event of exporting the product (including taking it outside of Japan) or supplying the software to
third parties not resident in Japan, make sure that all procedures as stipulated by the Foreign Exchange
and Foreign Trade Act are strictly observed.
The product, the product manual and the software may not be used or reproduced in whole or in part
without prior permission.
Product details and specifications are subject to modification without prior notice for the purpose of
improving reliability, functionality and design.
Note that although a great deal of care has been taken in manufacturing the product, the company does
not guarantee the results of its use.
The product has been manufactured with no intention of it being used for any purpose that requires
extremely high levels of reliability and safety in functions and performance (such as in military
equipment, nuclear power equipment, aerodynamic or space exploration equipment, traffic equipment,
incinerator control equipment, medical equipment, power generation control equipment, equipment
installed on the seabed, safety devices or similar equipment) in which malfunctions or incorrect
operations may result in direct threats or damage to human lives or that may result in serious threats to
society in general. Note that the company refutes all responsibility for damages incurred through these
uses.
Do not install the product in locations subject to excessive amounts of water, humidity, dust, oily vapor,
etc., as it may result in the outbreak of fire, malfunctions or electric shock. Make sure that the correct
power supply and voltage as listed is used.
All copyrights pertaining to CSIDE are the sole property of Computex Co., Ltd..
CSIDE, PALMiCE, and COMPUTEX are registered trademarks of Computex Co., Ltd. in Japan.
All other company names, product names, etc., listed within the product manual are trademarks and
registered trademarks of each individual manufacturer

Table of Contents
Chapter 1 Getting Started............................................................... 1
1.1 Introduction.............................................................................................................................................. 1
1.2 Product Composition Contents ................................................................................................ 2
1.3 Connection structure........................................................................................................................ 3
Chapter 2 PALMiCE3 JTAG200 Hardware
Specifications............ 4
2.1 PALMiCE3 JTAG200 model hardware specifications ........................................... 4
2.2 JTAG200 model specifications................................................................................................ 4
2.3 Name and function of each part............................................................................................. 5
2.3.1 Hardware revision................................................................................................................ 6
How revision sticker reads......................................................................................................................................................... 6
2.4 External probe........................................................................................................................................ 7
Chapter 3 Target Interface Specifications ........................... 8
3.1 Introduction.............................................................................................................................................. 8
3.2 Target interface .................................................................................................................................... 8
3.2.1 Shape of the connector for debugger................................................................. 8
3.2.2 Dimension of the target cable..................................................................................... 8
3.2.3 Specifications of target interface signals ........................................................... 8
3.2.4 The target interface on PALMiCE3 side............................................................. 9

PALMiCE3 JTAG200 model Hardware Manual Chapter 1 Getting Started 1
Chapter 1
Getting Started
1.1
Introduction
PALMiCE3 JTAG200 model is an on-chip debugger that supports ARM-made core CPUs.
Its main features are as follows:
Provides multi-core support
No power supply to PALMiCE3 is required (with VBus support)
Allows downloading to external flash memory and its debugging
Supports on-chip flash memory
Versatile
Supports USB Standard Revision2.0 high-speed and full-speed
Allows downloading of the latest CSIDE from the Internet
Designed with palm-sized, light, and compact body