Cray CRAY-1 Quick user guide

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c:
RESEARCH
J
INC.
CRAY-1®
COMPUTER SYSTEMS
HARDWARE REFERENCE MANUAL
HR-0004
Copyright© 1976, 1977, 1978, 1979, 1980, 1982 by
CRAY RESEARCH, INC. This manual or parts thereof
may not be reproduced in any form without permission
of CRAY RESEARCH, INC.

RECORD OF REVISION
RESEARCH. INC.
PUBLICATION NUMBER HR-0004
Each time this manual is revised and reprinted, all chan~es issued against the previous version in the form of change packets are
incorporated into the new version and the new version IS assigned an alphabetic level. Between reprints, changes may be issued
against
the current version in the form of change packets. Each change packet is assigned a numeric designator starting with
01 for the first change packet of each revision level. '
Every page changed
by a reprint or by a change packet has the revision level and change packet number in the lower righthand
corner. Changes
to part of a page are noted by a change bar along the margin of the page. A change bar in the margin opposite
the page
number indicates that the entire page is new; a dot in the same place indicates that information has been moved from
one page to another, but has not otherwise changed.
Requests
for copies of Cray Research, I nco publications and comments about these publications should be directed to:
CRAY RESEARCH, INC.,
1440 Northland Drive.
Mendota Heights, Minnesota 55120
Revision Description
January 1976 -Original printing
A r,1ay 1976 -Repri nt wi th revi sion
A-01 September 1976 -Corrections to pages 3-20, 3-27, 4-9, 4-10,
4-28, 4-36, 4-43, 4-55, and 4-57.
B October
1976 -Reprint with revision. Addition of floating
point range error detection, vector floating point error, and
error correction.
3-01 February 1977 - Changes to exchange pckage, additions to
instructions 152 and 153, corrections to syndrom bit
description, corrections to instruction summary, appendix D.
B-02 July 1977 -Corrections and changes to pages xi, 2-3, 3-19 -.....-/
through 3-28.1, 3-31, 3-34, 3-36, 3-38, 4-14 through 4-17, 4-54,
4-68, 5-1, 5-3, 5-4, 5-6, 6-2, A-4, 0-1 through n-4.
C November 1977 -This printing obsoletes revision B. Features
added include 8-bank phasing and I/O master clear procedure.
Chart tape
reflects only changes introduced with this revision.
C-01 Apri 1 1978 - Thi s change packet changes the nomencl ature for tv/O
flags in the exchange package (page 3-37) and corrects technical
errors on pages 2-11, 4-71, 5-6, 6-5, and A-3.
C-02 July 1978 -This change packet documents changes to the physical
description of the
CRAY-1 Computer System. Changes are all in
section 2.
o August 1978 -This printing is exactly the same as revision C
with change packets C-Ol and C-02 incorporated.
HR-0004
i i F

Revision Description
E May 15, 1979 -Reprint with reV1Slon. This printing corrects
the description of the multiply algorithm and adds descriptions
of various standard options (i.e., vector population
instructions, programmable clock interrupt, and monitor mode
interrupt). In addition, sections 5 and 6 have been reHritten.
Revision E obsoletes versions C and Dof this publication.
E-Ol May, 1980 -This change packet documents changes to the multiply
functional
unit that supports symmetrical multiply, documents
CAL instruction changes, and corrects miscellaneous technical
errors. Changes are noted by change bars.
F
May, 1982 -This reprint with revision incorporates revision E
with E-Ol. With this printing, the publication number has been
changed to HR-0004. No other changes have been made.
HR-0004
i i .i

I
CONTENTS
1.
2.
INTRODUCTION . . . . .
COMPUTATION SECTION
MEMORY SECTION . . . .
INPUT/OUTPUT SECTION
VECTOR PROCESSING . .
PHYSICAL ORGANIZATION
INTRODUCTION .
MAINFRft}1E . .
Modul es . .
Clock . .
Power supplies
PRIMARY POWER SYSTEM .
COOLING . . . . . . .
MAINTENANCE CONTROL UNIT
FRONT-END COMPUTER . . . . . .
EXTERNAL INTERFACE . . .
MASS STORAGE SUBSYSTEM .
3. COMPUTATION SECTION
INTRODUCTION . . . .
REGISTER CONVENTIONS .
OPERATING REGISTERS
Vregi sters . .
V
register reservations
Vector control registers
VL register
VM register
S registers
T regi
sters
A registers . . . . . . . . . . . . . . . . . .
B registers
2240004
iii
· 1-1
· . 1-4
· . 1-5
· . 1-5
· . 1-6
· 2-1
· . 2-1
· 2-1
· 2-1
2-4
2-5
2-5
· 2-6
2-6
2-7
· 2-7
· . 2-8
· 3-1
. . . . . 3-1
· . 3-3
· . 3-3
· . 3-4
3-5
· . 3-6
· . 3-6
· 3-6
· . 3-7
... 3-8
... 3-8
· . 3-9
E

I
FUNCTIONAL UNITS . . . . . . . . · . 3-10
Address functional units
Address add unit
Address multiply unit·
Scalar functional units
Scalar add unit
Scalar shift unit
Scalar logical unit
Population/leading zero count unit
Vector functional units ....... .
· . 3-11
· . 3-11
3-11
3-12
· . 3-12
· 3-12
· . 3-13
· . . 3-13
· 3-13
Vector functional unit reservation .. ·3-13
Recursive
characteristic of vector functional units 3-14
Vector
add unit . . . . . . . . . . . . . . 3-17
Vector shift unit
Vector logical unit
Vector population count unit.
Floating point functional units.
Floating point add unit
Floating point multiply unit.
Reciprocal approximation unit
· .. 3-17
· 3-17
· 3-18
· . 3-18
· . 3-18
· . 3-19
ARITHMETIC OPERATIONS
· . 3-19
· 3-20
.. 3-20
Integer arithmetic
Floating point arithmetic.
Normalized floating point
Floating point range errors .....
Floating point add unit
Floating point multiply unit.
· 3-21
· 3-22
3-22
.
...... 3-23
.. 3-23
Floating
point reciprocal approximation unit.
3-23
Double precision numbers.
Addition algorithm
Multiplication algorithm
Division algorithm
LOGICAL OPERATIONS
2240004
iv
· 3-24
3-24
· 3-25
· .. 3-30
· 3-31
E

INSTRUCTION
ISSUE AND CONTROL
P register
CIP register
NIP register
LIP register
Instruction buffers
EXCHANGE MECHANISM
XA regi ster . .
M
register .
F
register ..
Exchange package
Memory error data
Active exchange package
. .
.
Exchange sequence . . . . . . . . . . . . . . . .
Initiated by dead start sequence .....
Initiated by interrupt flag set
Initiated by program exit ....
Exchange sequence issue conditions ...
Exchange package management
MEMORY FIELD PROTECTION
BA regi ster
LA regi ster . .
DEAD START SEQUENCE
4. INSTRUCTIONS ...
INSTRUCTION FORMAT .
Arithmetic, logical format
Shift, mask format
Immediate constant format.
Memory transfer format
Branch format . . . .
SPECIAL REGISTER VALUES
2240004
v
.
.
3-32
3-32
3-33
3-33
. 3-34
3-34
. . . . 3-37
· . . 3-37
· 3-37
· . 3-39
· 3-40
· 3-41
3-42
· . . 3-42
· . 3-43
· .. 3-43
· . 3-43
3-44
3-45
· . 3-46
· . 3-47
· . 3-47
· . 3-47
4-1
· .. 4-1
· 4-1
· 4-2
· .. 4-2
· 4-3
· 4-4
· 4-5
E

I
I
INSTRUCTION ISSUE
INSTRUCTION DESCRIPTIONS
2240004
000000 Error exit
001 ij k
0014jk
0020xk
0021xx
0022xx
003xjx
004xxx
005xjk
006i j km
007ijkm
010ijkm
011 ij km
012ijkm
013ijkm
014ijkm
015ijkm
016ijkm
017ijkm
020ijkm
021 ij km
022i j k
023ijx
024ijk
025i j k
026i jO
026ij1
027i jx
030i j k
031 ij k
032i j k
033i j k
Monitor functions
Programmable clock interrupt functions
Transmit
(Ak) to VL
Set floating point mode flag in M register.
Clear floating point mode flag in M register.
Transmit (Sj) to vector mask
Normal exit
Branch to (Bjk)
Branch to ij km .
Return
jump to ijkm; set Boo to (P)
Branch to ijkm if (Ao) = 0 .
Branch to ijkm if (Ao) to.
Branch to ijkm if (Ao) positive
Branch to ijkm if (Ao) negative
Branch to ijkm if (So) = 0 .
Branch to ijkm if (So) t 0
Branch to ijkm if (So) positive
Branch to ijkm if (So) negative
Transmit
jkm to Ai
Transmit complement of jkm to Ai
Transmit jk to Ai
Transmit (Sj) to Ai
Transmit (Bjk) to Ai
Transmit (Ai) to Bjk
Population count of (Sj) to Ai
Population count parity of (Sj) to Ai
Leading zero count of (Sj) to Ai
Integer sum of (Aj) and (Ak) to Ai
Integer difference of (Aj) and (Ak) to Ai
Integer product of (Aj) and (Ak) to Ai
Transmit I/O status to Ai
vi
· 4-5
4-6
· 4-7
4-8
· 4-10
· 4-12
4-13
4-13
4-14
4-15
· 4-16
4-17
· 4-18
4-19
· 4-19
· 4-19
. . 4-19
4-20
· 4-20
. 4-20
4-20
4-21
· 4-21
4-22
· 4-23
· 4-24
· 4-24
· 4-25
4-25
4-26
· 4-27
· 4-27
· 4-28
4-29
E

2240004
034i j k
035i j k
036ijk
037i j k
040ijkm
041 ij km
042ijk
043i j k
044i j k
045i j k
046i j k
047i j k
050i j k
051 ij k
052i j k
053i j k
054i j k
055i j k
056ijk
057ijk
060ijk
061 ij k
062ijk
063i j k
064i j k
065ijk
066i j k
067ijk
070ijx
Block transfer (Ai) words from memory starting at
address (Ao) to B registers starting at register jk 4-31
Block transfer (Ai) words from B registers starting
at register jk to memory starting at address (Ao) 4-31
Block transfer (Ai) words from memory starting at
address (Ao) to T registers starting at register jk 4-31
Block transfer (Ai) words from T registers starting
at register jk to memory starting at address (Ao) 4-31
Transmit
jkm to Si
· 4-33
Transmit complement of jkm to Si
· 4-33
Form 64 -jk bits of one's mask in Si from right . 4-34
Form jk bits of one's mask in Si from left .... 4-34
Logical product of (Sj) to
(Sk) to Si ....... 4-35
Logical product of (Sj)
and complement of (Sk) to Si 4-35
Logical
difference of (Sj) and (Sk) to Si . . 4-35
Logical equivalence
of (Sk) and co~plement of (Sk)
to Si . . . . . .. .............. 4-35
Scalar merge ................... 4-35
Logical
sum of (Sj) and (Sk) to Si . 4-35
Shift (Si) left jk places to So 4-38
Shift
(S i )
Shift
(Si )
Shift
(S i )
right 64 - jk places to S
left jk places to Si
right 64 - jk places to Si
4-38
... 4-38
4-38
Shift
(S i )
Shift
(Sj)
and (Sj) left by (Ak) places to Si .
and (Si) right by (Ak) places to Si
.. 4-39
.. 4-39
Integer
sum of (Sj) and (Sk) to Si
Integer difference of (Sj) and (Sk) to Si .
Floating
sum of (Sj) and (Sk) to Si ....
· 4-40
· 4-40
4-41
Floating
difference of (Sj) and (Sk) to Si . 4-41
Floating product of (Sj)
and (Sk) to Si ...... 4-42
Half-precision rounded
floating product of (Sj) and
(Sk) to Si .................... 4-42
Rounded floating product of (Sj) and (Sk) to Si .. 4-42
Reciprocal
iteration; 2 - (Sj) * (Sk) to Si .... 4-42
Floating reciprocal approximation of (Sj) to
Si .. 4-44
vii
E

2240004
071 ijk
072ixx
073ixx
074ijk
075i j k
076i j k
077 ij k
10hijkm
11hi j km
12hijkm
13hijkm
140ijk
141 ijk
142i j k
143i j k
144ijk
145ijk
146ijk
147i j k
150ijk
151ijk
152ijk
153ijk
154i j k
155ijk
Transmit
(Ak) or normalized floating point constant
to
Si . . . . . . . . . . . . . . . 4-45
Transmit (RTC) to Si ..... . .... 4-47
Transmit (VM) to Si . . . .. 4-47
Transmit (Tjk) to Si
Transmit (Si) to Tjk
Transmit (Vj element (Ak)) to Si
Transmit (Sj) to Vi element (Ak)
Read from ((Ah) + jkm) to Ai
Store (Ai) to (Ah) + jkm
Read from ((Ah) + jkm) to Si
Store (Si) to (Ah) + jkm ...
· . 4-47
. . . . 4-47
4-48
· . 4-48
. 4-49
... 4-49
4-49
· . 4-49
Logical products of (Sj)
and (Vk elements) to
Vie 1 eme nts . . . . . . . . . . . . . . . . .. 4- 51
Logical products of (Vj elements) and (Vk elements)
to
Vi elements . . . . . . . . . . . . .. 4-51
Logical sums of (Sj) and (Vk elements) to Vi
elements . . . . . . ...... 4-51
Logical sums of (Vj elements) and (Vk elements) to
Vi elements.. .... . . . . . 4-51
Logical differences of (Sj) and (Vk elements) to
Vi elements. . . . . . . . . . . . . . . .. . 4-51
Logical differences of (Vj elements) and (Vk
elements to Vi elements. . . . . . . . . . . 4-51
If VM bit = 1, transmit (Sj) to Vi elements
If VM bit = 0, transmit (Vk elements) to Vi
If VM bit = 1, transmit (Vj elements) to Vi
If VM bit = 0, transmit (Vk elements) to Vi
Single shifts of (Vj elements) left by (Ak)
to Vi elements . . . . . . ...
Single shifts of (Vj elements) right by (Ak)
to Vi elements ............. .
elements4-51
elements
elements4-51
places 4-55
places 4-55
Double shifts of (Vj elements) left by (Ak) places
to
Vi elements .. . . . . . . . . .. . ... 4-56
Double shifts of (Vj elements) right by (Ak) places
to
Vi elements .................. 4-56
Integer
sums (Sj) and (Vk elements) to Vi elements. 4-61
Integer sums (Vj elements) and (Vk elements) to
Vi elements .................... 4-61
viii
E

156i j k
157ijk
160i j k
161 ijk
162ijk
163ijk
164i j k
165ijk
166i j k
167ijk
170i j k
171 ijk
172i j k
173ijk
174ijO
I 174ij1
174ij2
175xj k
176ixk
177xj k
2240004
Integer differences of (Sj) and (Vk elements) to
Vi elements . . . . . . . . . . . . . . . .. . 4-61
Integer
differences of (Vj elements) and (Vk
elements) to Vi elements . . . . . . 4-61
Floating products of (Sj)
and (Vk elements) to
Vi elements . . . . . . . . . . . . . . . . . 4-63
Floating products of
(Vj elements) and (Vk
elements) to Vi elements ............. 4-63
Half-precision rounded
floating products of (Sj)
and (Vk elements) to Vi elements .. . . . . 4-63
Half-precision rounded
floating products of (Vj
elements) and (Vk elements) to Vi elements . 4-63
Rounded floating products of(Sj) and (Vk elements
to
Vi elements . . . . . . . . . . . . . . 4-63
Rounded floating products 0 f (V j elements) and
(Vk elements) to Vi elements . . .. . 4-63
Reciprocal
iterations; 2 - (Sj) * (Vk elements) to
Vi el ements .................... 4-63
Reciprocal
iterations; 2 - (Vj elements) * (Vk
elements) to Vi elements . . . . . 4-63
Floating
sums of (Sj) and (Vk elements) to Vi
elements .. . . . . . . . . . . . . . . . . . . . 4-66
Floating
sums of (Vj elements) and (Vk elements)
to
Vi elements .................. 4-66
Floating
differences of (Sj) and (Vk elements) to
Vi elements . . . . .. ..... . 4-66
Floating
differences of (Vj elements) and (Vk
elements) to Vi elements ... . . . . .. .. 4-66
Floating point reciprocal approximations of
(Vj elements) to Vi elements ........... 4-68
Population counts of (Vj elements) to Vi elements
Population count parities of (Vj elements) to Vi
elements . . . . . . . . . . . . . . . . . . . . . 4-70
Test (Vj elements) and enter test results into VM;
the type of test made is defined by k ....... 4-71
Transmit
(VL) words from memory to Vi elements
starting at memory address (Ao) and incrementing
by (Ak) for successive addresses ......... 4-73
Transmit
(VL) words from Vj elements to memory
starting at memory address (Ao) and incrementing
by (Ak) for successive addresses ......... 4-73
i x E

I
I
I
5. MEMORY SECTION
INTRODUCTION .
MEMORY CYCLE TIME
MEMORY ACCESS
MEMORY ORGANIZATION
MEMORY ADDRESSING
SPEED CONTROL
8-BANK PHASING OPTION
MEMORY PARITY ERROR CORREC7ION
6. INPUT/OUTPUT SECTION
I/O CHANNELS •. .
I/O instructions
Basic channel operation
Input channel
programming
Output channel programming
16-bit asynchronous channels
Input channels
Output channels
16-bit high-speed asynchronous channels
Input channels
Output channels
16-bit synchronous channels .
Input channels
Output channels
PROGRAMMED MASTER CLEAR TO ~XTERNAL
MEMORY ACCESS
I/O lockout. . .
Memory bank conflicts
I/O memory conflicts
I/O memory request conditions
I/O memory addressing
REAL-TIME CLOCK .
PROGRAMMABLE CLOCK OPTION
2240004
x
5-1
5-1
5-1
5-1
5-3
5-4
5-4
5-5
5-5
6-1
6-1
6-1
6-2
6-3
6-7
6-7
6-7
6-9
6-10
6-10
6-12
6-13
6-13
6-15
6-17
6-19
6-21
6-21
6-21
6-22
6-22
6-22
6-23
E

,
Interrupt interval register ........ .
Interrupt countdown counter . . . . . . . .. ..... .
Clear programmable clock interrupt request ........ .
APPENDIXES
A SUMMARY OF TIMING INFORMATION
B MODULE TYPES . . . . . .
C SOFTWARE CONSIDERATIONS
o INSTRUCTION SUMMARY
2240004 xi
6-23
6-24
6-24
A-I
B-1
C-l
0-1
E

FIGURES
1-1
2-1
2-2
2-3
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
4-1
4-2
4-3
4-4
4-5
4-6
I
5-1
5-2
I 5-3
6-1
6-2
2240004
Basic computer system ........ .
Physical organization of the mainframe
General chassis layout
Clock pulse waveform
Computation section ...
Integer data formats
Floating point data format
49-bit floating point addition
Floating point multiply
pyramid ........ .
Relationship of
instruction buffers and registers ..
Instruction buffers ..... .
Exchange package . . . . . . . .
General format for
instructions .
Format for arithmetic and logical instructions
Format for shift and mask instructions
1-2
· . 2-2
· . 2-3
2-7
3-2
· .. 3-20
· . 3-21
· 3-24
· 3-26
· . 3-32
· .. 3-34
3-38
4-1
· 4-2
· 4-2
Format for immediate constant instructions
Format for memory transfer instructions ..
...... 4-3
Two-parcel format for branch
instructions .
Memory address; 16 banks
Memory data path with SECDED .....
Error correction matrix ....
Basic I/O program flow chart
Channel I/O control . . . . . .
xii
. . . . 4-4
· 4-4
· 5-4
5-6
· .. 5-7
· 6-4
6-20
E

TABLES
1-1 Characteristics of CRAY-1 Computer System .....
2-1
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
2240004
Characteristics of a 00-19 Disk Storage Unit
Vector
Memory rate * 80 x 10
6 references per second .
Channel word assembly/disassembly ............ .
16-bit asynchronous input channel
signa
1 exchange . . . . . . . . . . . . . . . . . . . . . .
16-bit asynchronous output channel
signa
1 exchange . . . . . . . . . . . . . . . . . . . . . .
16-bit high-speed asynchronous input
channel signal exchange
...... .
16-bit high-speed asynchronous output
channel signal exchange
.....
16-bit synchronous input channel
signal exchange
........ .
16-bit synchronous output channel
signal exchange
............. .
xiii
1-3
2-13
5-4
6-2
6-8
6-9
6-11
6-12
6-14
6-16
E

SECTION 1
INTRODUCTION

INTRODUCTION 1
The CRAY-1 Computer System is a powerful general-purpose computer capable
of extremely high processing
rates. These rates are achieved by combining
scalar and vector capabilities into a single central processor which is
joined to a large, fast, bi-polar memory. Vector processing by performing
iterative operations on sets of ordered data provide results at rates
greatly exceeding result rates of conventional scalar processing. Scalar
operations
complement the vector capability by providing solutions to
problems not
readily adapted to vector techniques.
Figure 1-1 represents the basic organization of a
CRAY-1 system. The
central processor unit (CPU) is a single integrated processing unit
consisting of a computation section, a memory section, and an input/
output section. The memory is expandable from 0.25 million 64-bit words
to a maximum of 1.0 million words. The 12 input channels and 12
output channels in the input/output section connect to a maintenance
control
unit (MCU), a mass storage subsystem, and a variety of front-end
systems or peripheral equipment.
The MCU provides for system initializa-
tion and for monitoring system performance. The mass storage subsystem
provides secondary storage
and consists of one to eleven Cray Research
OCU-2 Disk Controllers, each with one to four 00-19 Disk Storage Units.
Each 00-19 has a capacity of 2.424 x 10
9
bits.
I/O channels can be connected to independent processors referred to as
front-end computers or
I/O stations or can be connected to peripheral
equipment according to the requirements of the individual
installation.
At least one front-end system is considered standard to collect data
and present it to the CRAY-1 for processing and to receive output from
the CRAY-1 for distribution to slower devices.
Table
1-1 summarizes the characteristics of the system. The following
paragraphs provide
an additional introduction to the three sections of
the
CPU; later sections of this manual describe the features in detail.
2240004
1-1
E

I
r--- - - - --- - --- -- -- - -- -- ---- - - --- - - --1
I
I
I
L ______ _
/
MCU
2240004
-
'"
COMPUTATION SECTION
• Registers
• Functional units
• Instruction buffers
MEMORY SECTION
0.25 Mor 0.5 Mor 1 M
64-bit bi-polar words
I/O SECTION
•
12 input channels
•
12 output channels I
I
/,''' I I , \ , \ \
'\
-1-1 -f -i --- I I \ \ \ \
-+Ir-\"-~
CPU I
______ ..J
I I
I I
/ I
/ I I
/ I
1 I
/ / I
/ I I
I
I
i
I
I
I
I I \ \ \ \ \
I \ \ \ \ \ \
I \ \
I , \
I , \
I \ \
\ \ \ \ \
\ \ \ \
\ '. \ \
\ \ \ \
\ \ \ \
L I J I I , \ \ \ \
\.
MASS STORAGE SUBSYSTEM, FRONT-END COMPUTERS,
I/O STATIONS, AND PERIPHERAL EQUIPMENT
Figure 1-1. Basic computer system
1-2
E