Cypress CYW43340 User manual

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PRELIMINARY CYW43340
Single-Chip, Dual-Band (2.4 GHz/5 GHz)
IEEE 802.11 a/b/g/n MAC/Baseband/
Radio with Integrated Bluetooth 5.0
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-14943 Rev. *N Revised Wednesday, March 24, 2021
General Description
The Cypress CYW43340 single–chip quad–radio device provides the highest level of integration for wearables, Internet of Things and
gateway applications, with integrated dual band (2.4 GHz / 5 GHz) IEEE 802.11 a/b/g and single–stream IEEE 802.11n MAC/
baseband/radio, and Bluetooth 5.0. The CYW43340 includes integrated power amplifiers and LNAs for the 2.4 GHz and 5 GHz WLAN
bands, and an integrated 2.4 GHz T/R switch. This greatly reduces the external part count, PCB footprint, and cost of the solution.
Using advanced design techniques and process technology to reduce active and idle power, the CYW43340 is designed to address
the needs of mobile devices that require minimal power consumption and compact size. It includes a power management unit which
simplifies the system power topology and allows for operation directly from a mobile platform battery while maximizing battery life.
The CYW43340 implements the highly sophisticated Enhanced Collaborative Coexistence algorithms and hardware mechanisms,
allowing for an extremely collaborative Bluetooth coexistence scheme along with coexistence support for external radios (such as
cellular and LTE, GPS, WiMAX, and Ultra–Wideband) and a single shared 2.4 GHz antenna for Bluetooth and WLAN. As a result,
enhanced overall quality for simultaneous voice, video, and data transmission in an IoT or wearable application is achieved.
For the WLAN section, two host interface options are included: an SDIO v2.0 interface and a High-Speed Inter-Chip (HSIC) interface
(a USB 2.0 derivative for short-distance on-board connections). An independent, high-speed UART is provided for the Bluetooth host
interface.
Features
IEEE 802.11x Key Features
■Dual–band 2.4 GHz and 5 GHz IEEE 802.11
a/b/g/n
■Single–stream IEEE 802.11n support for 20 MHz and 40 MHz
channels provides PHY layer rates up to 150 Mbps for typical
upper–layer throughput in excess of 90 Mbps.
■Supports a single 2.4 GHz antenna shared between WLAN and
Bluetooth.
■Shared Bluetooth and 2.4 GHz WLAN receive signal path elimi-
nates the need for an external power splitter while maintaining
excellent sensitivity for both Bluetooth and WLAN.
■Internal fractional nPLL allows support for a wide range of
reference clock frequencies
■Supports IEEE 802.15.2 external coexistence interface to
optimize bandwidth utilization with other co–located wireless
technologies such as GPS, WiMAX, or UWB
■Supports standard SDIO v2.0 host interfaces.
■Alternative host interface supports HSIC v1.0 (short–distance
USB device)
■Integrated ARM® Cortex–M3™ processor and on–chip
memory for complete WLAN subsystem functionality,
minimizing the need to wake up the applications processor for
standard WLAN functions. This allows for further minimization
of power consumption, while maintaining the ability to field
upgrade with future features. On–chip memory includes 512
KB SRAM and 640 KB ROM.
■OneDriver™ software architecture for easy migration from
existing embedded WLAN and Bluetooth devices as well as
future devices.
Bluetooth Key Features
■Qualified for Bluetooth Core Specification 5.0:
❐QDID: 108508
❐Declaration ID: D035926
■Bluetooth Class 1 or Class 2 transmitter operation
■Supports extended Synchronous Connections (eSCO), for
enhanced voice quality by allowing for retransmission of
dropped packets.
■Adaptive Frequency Hopping (AFH) for reducing radio
frequency interference
■Interface support: Host Controller Interface (HCI) using a high-
speed UART interface and PCM for audio data
■Low power consumption improves battery life of handheld
devices.
■Supports multiple simultaneous Advanced Audio Distribution
Profiles (A2DP) for stereo sound.
■Automatic frequency detection for standard crystal and TCXO
values
General Features
■Supports battery voltage range from 2.9V to 4.8V supplies with
internal switching regulator.
■Programmable dynamic power management
■3072-bit OTP for storing board parameters
■Routable on low–cost 1x1 PCB stack–ups
■141-ball WLBGA package(5.67 mm × 4.47 mm, 0.4 mm pitch)
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Document Number: 002-14943 Rev. *N Page 2 of 96
PRELIMINARY CYW43340
■Security:
❐WPA™ and WPA2™ (Personal) support for powerful encryp-
tion and authentication
❐AES in WLAN hardware for faster data encryption and IEEE
802.11i compatibility
❐Reference WLAN subsystem provides Cisco® Compatible
Extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0)
❐Reference WLAN subsystem provides Wi–Fi Protected Set-
up (WPS)
■Worldwide regulatory support: Global products supported with
worldwide homologated design
Figure 1. Functional Block Diagram
VIO VBAT
CYW43340
WLAN
HostI/F
Bluetooth
HostI/F
WL_REG_ON
SDIO*
WL_IRQ
BT_REG_ON
UART
BT_DEV_WAKE
BT_HOST_WAKE
CLK_REQ
HSIC
PCM/I2S
2.4GHzWLAN+BluetoothTx/Rx CBF
FEMor
T/R
Switch
5GHzWLANTx
5GHzWLANRx
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Document Number: 002-14943 Rev. *N Page 3 of 96
PRELIMINARY CYW43340
Contents
1. Introduction ................................................................... 4
1.1 Overview ............................................................... 4
1.2 Features ................................................................ 5
1.3 Standards Compliance .......................................... 6
2. Power Supplies and Power Management ...................7
2.1 Power Supply Topology ........................................ 7
2.2 WLAN Power Management ................................... 9
2.3 PMU Sequencing .................................................. 9
2.4 Power-Off Shutdown ........................................... 10
2.5 Power-Up/Power-Down/Reset Circuits ...............10
3. Frequency References ............................................... 11
3.1 Crystal Interface and Clock Generation .............. 11
3.2 TCXO ..................................................................11
3.3 Frequency Selection ............................................ 13
3.4 External 32.768 kHz Low-Power Oscillator ......... 14
4. Bluetooth Subsystem Overview ................................15
4.1 Features .............................................................. 15
4.2 Bluetooth Radio ................................................... 16
5. Bluetooth Baseband Core ......................................... 17
5.1 Bluetooth 5.0 Features ........................................ 17
5.2 Link Control Layer ............................................... 17
5.3 Test Mode Support .............................................. 17
5.4 Bluetooth Power Management Unit ..................... 18
5.5 Adaptive Frequency Hopping ..............................21
5.6 Advanced Bluetooth/WLAN Coexistence ............21
5.7 Fast Connection (Interlaced Page and Inquiry
Scans) ................................................................ 21
6. Microprocessor and Memory Unit for Bluetooth ..... 22
6.1 RAM, ROM, and Patch Memory ..........................22
6.2 Reset ................................................................... 22
7. Bluetooth Peripheral Transport Unit ........................ 23
7.1 PCM Interface ..................................................... 23
7.2 UART Interface .................................................... 30
7.3 I2S Interface ........................................................ 31
8. WLAN Global Functions ............................................ 34
8.1 WLAN CPU and Memory Subsystem .................. 34
8.2 One-Time Programmable Memory ......................34
8.3 GPIO Interface .................................................... 34
8.4 External Coexistence Interface ...........................34
8.5 UART Interface .................................................... 35
8.6 JTAG Interface .................................................... 35
9. WLAN Host Interfaces ................................................ 36
9.1 SDIO v2.0 ............................................................ 36
9.2 HSIC Interface ..................................................... 38
10. Wireless LAN MAC and PHY ...................................39
10.1 MAC Features ................................................... 39
10.2 WLAN PHY Description ..................................... 42
11. WLAN Radio Subsystem .......................................... 44
11.1 Receiver Path .................................................... 44
11.2 Transmit Path .................................................... 44
11.3 Calibration ......................................................... 44
12. Pinout and Signal Descriptions .............................. 45
12.1 Signal Assignments ........................................... 45
12.2 Signal Descriptions ............................................ 45
12.3 I/O States .......................................................... 54
13. DC Characteristics ................................................... 57
13.1 Absolute Maximum Ratings ............................... 57
13.2 Environmental Ratings ...................................... 57
13.3 Electrostatic Discharge Specifications .............. 58
13.4 Recommended Operating Conditions and DC
Characteristics .................................................... 58
14. Bluetooth RF Specifications .................................... 60
15. WLAN RF Specifications .......................................... 67
15.1 Introduction ........................................................ 67
15.2 2.4 GHz Band General RF Specifications ......... 68
15.3 WLAN 2.4 GHz Receiver Performance
Specifications ..................................................... 68
15.4 WLAN 2.4 GHz Transmitter Performance
Specifications ..................................................... 72
15.5 WLAN 5 GHz Receiver Performance
Specifications ..................................................... 73
15.6 WLAN 5 GHz Transmitter Performance
Specifications ..................................................... 75
15.7 General Spurious Emissions Specifications ...... 76
16. Internal Regulator Electrical Specifications .......... 77
16.1 Core Buck Switching Regulator ......................... 77
16.2 3.3V LDO (LDO3P3) .........................................78
16.3 2.5V LDO (LDO2P5) .........................................79
16.4 HSICDVDD LDO ............................................... 79
16.5 CLDO ................................................................ 80
16.6 LNLDO .............................................................. 81
17. System Power Consumption ...................................82
17.1 WLAN Current Consumption ............................. 82
17.2 Bluetooth and BLE Current Consumption ......... 83
18. Interface Timing and AC Characteristics ............... 84
18.1 SDIO Timing ...................................................... 84
18.2 HSIC Interface Specifications ............................86
18.3 JTAG Timing ..................................................... 86
19. Power-Up Sequence and Timing ............................. 87
19.1 Sequencing of Reset and Regulator Control
Signals ................................................................ 87
20. Package Information ................................................ 90
20.1 Package Thermal Characteristics ..................... 90
20.2 Junction Temperature Estimation and PSIJT
Versus THETAJC ................................................ 90
20.3 Environmental Characteristics ........................... 90
21. Mechanical Information ........................................... 91
22. Ordering Information ................................................ 93
23. Additional Information ............................................. 93
23.1 Acronyms and Abbreviations ............................. 93
23.2 IoT Resources ................................................... 93
Document History ........................................................... 94
Sales, Solutions, and Legal Information ...................... 96
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Document Number: 002-14943 Rev. *N Page 4 of 96
PRELIMINARY CYW43340
1. Introduction
1.1 Overview
The Cypress CYW43340 single-chip device provides the highest level of integration for wearables, audio and IoT applications, with
integrated IEEE 802.1 a/b/g/n MAC/baseband/radio, and Bluetooth 5.0. It provides a small form-factor solution with minimal external
components to drive down cost, flexibility in size, form, and function. Comprehensive power management circuitry and software ensure
the system can meet the needs of highly mobile devices that require minimal power consumption and reliable operation.
Figure 2 shows the interconnect of all the major physical blocks in the CYW43340 and their associated external interfaces, which are
described in greater detail in the following sections.
Figure 2. Block Diagram
Chip
Common
BT RF
Modem
AXI Backplane
ARMCM3
AXI2AHB
AHB2AXI
SDIOD
USB20D
HSIC
DOT11MAC (D11)
1x1 11N PHY
2.4 GHz / 5 GHz Dualband Radio
SoCSRAM
RAM512KB
ROM640KB
AHB Bus Matrix
UART
ARMCM3
WLAN
Master
Slave
FM
Receiver
RAM
ROM
I2S
PCM
Port Control
RX/TX
LCU
APU
BlueRF
BLE
AXI2APB
DMA
JTAG
Master
AHB2APB
Timers
GPIO
WD
Pause
Registers
Shared LNA
Control
WLAN BT Access
ARM CM0
RAM
ROM
SWP DIG
AHB
Bridge
Analog PMU
PMU
Controller
CLB
JTAG
From
WLAN
BT
To
WLAN
BT
PMU
XTAL/Radio/Pads etc
WLAN
BT/FM
GCI
From
WLAN
BT
To
WLAN
BT
FLL
Clk rst
To
CLB
To
CLB
To
GCI
LTE LTE
CLB
UPI
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Document Number: 002-14943 Rev. *N Page 5 of 96
PRELIMINARY CYW43340
1.2 Features
The CYW43340 supports the following WLAN and Bluetooth features:
■IEEE 802.11a/b/g/n dual-band radio with internal Power Amplifiers, LNAs, and T/R switches
■Bluetooth 5.0 with integrated Class 1 PA
■Concurrent Bluetooth, and WLAN operation
■On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality
■Single- and dual-antenna support
❐Single antenna with shared LNA
❐Simultaneous BT/WLAN receive with single antenna
■WLAN host interface options:
❐SDIO v2.0, including default and high-speed timing.
❐HSIC (USB device interface for short distance on-board applications)
■BT host digital interface (can be used concurrently with above interfaces):
❐UART (up to 4 Mbps)
■ECI—enhanced coexistence support, ability to coordinate BT SCO transmissions around WLAN receives
■I2S/PCM for BT audio
■HCI high-speed UART (H4, H5) transport support
■Wideband speech support (16 bits linear data, MSB first, left justified at 4K samples/s for transparent air coding, both through I2S
and PCM interface)
■Bluetooth SmartAudio® technology improves voice and music quality to headsets
■Bluetooth low power inquiry and page scan
■Bluetooth Low Energy (BLE) support
■Bluetooth Packet Loss Concealment (PLC)
■Bluetooth Wideband Speech (WBS)
■Audio rate-matching algorithms
■Multiple simultaneous A2DP audio stream
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Document Number: 002-14943 Rev. *N Page 6 of 96
PRELIMINARY CYW43340
1.3 Standards Compliance
The CYW43340 supports the following standards:
■Bluetooth 5.0 (including Bluetooth Low Energy)
■IEEE 802.11n—Handheld Device Class (Section 11)
■IEEE 802.11a
■IEEE 802.11b
■IEEE 802.11g
■IEEE 802.11d
■IEEE 802.11h
■IEEE 802.11i
The CYW43340 will support the following future drafts/standards:
■IEEE 802.11r—Fast Roaming (between APs)
■IEEE 802.11k—Resource Management
■IEEE 802.11w—Secure Management Frames
■IEEE 802.11 Extensions:
❐IEEE 802.11e QoS Enhancements (as per the WMM® specification is already supported)
❐IEEE 802.11h 5 GHz Extensions
❐IEEE 802.11i MAC Enhancements
❐IEEE 802.11r Fast Roaming Support
❐IEEE 802.11k Radio Resource Measurement
The CYW43340 supports the following security features and proprietary protocols:
■Security:
❐WEP
❐WPA™ Personal
❐WPA2™ Personal
❐WMM
❐WMM-PS (U-APSD)
❐WMM-SA
❐WAPI
❐AES (Hardware Accelerator)
❐TKIP (host-computed)
❐CKIP (SW Support)
■Proprietary Protocols:
❐CCXv2
❐CCXv3
❐CCXv4
❐CCXv5
■IEEE 802.15.2 Coexistence Compliance—on silicon solution compliant with IEEE 3 wire requirements
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Document Number: 002-14943 Rev. *N Page 7 of 96
PRELIMINARY CYW43340
2. Power Supplies and Power Management
2.1 Power Supply Topology
One Buck regulator, multiple LDO regulators, and a Power Management Unit (PMU) are integrated into the CYW43340. All regulators
are programmable via the PMU. These blocks simplify power supply design for Bluetooth, and WLAN in embedded designs.
A single VBAT (2.9–4.8V) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in
the CYW43340.
Two control signals, BT_REG_ON and WL_REG_ON, are used to power-up the regulators and take the respective section out of
reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only
when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO may be turned off/on based on the dynamic
demands of the digital baseband.
The CYW43340 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNDLO
regulators. When in this state, LPLDO1 and LPLDO2 (which are low-power linear regulators that are supplied by the system VIO
supply) provide the CYW43340 with all the voltages it requires, further reducing leakage currents.
2.1.1 CYW43340 PMU Features
■VBAT to 1.35Vout (372 mA maximum) Core-Buck (CBUCK) switching regulator
■VBAT to 3.3Vout (450 mA maximum) LDO3P3 (external-capacitor)
■VBAT to 2.5Vout (70 mA maximum) LDO2P5 (external-capacitor)
■1.35V to 1.2Vout (100 mA maximum) LNLDO (external-capacitor)
■1.35V to 1.2Vout (150 mA maximum) CLDO (external-capacitor)
■1.35V to 1.2Vout (80 mA maximum) HSICDVDD LDO (external-capacitor)
■Additional internal LDOs (not externally accessible)
Figure 3 on page 8 shows the regulators and a typical power topology.
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Document Number: 002-14943 Rev. *N Page 8 of 96
PRELIMINARY CYW43340
Figure 3. Typical Power Topology
LNLDO
Max 100 mA
CLDO
Max 150 mA
Internal
LNLDO
Internal
LNLDO
Internal
LNLDO
Internal
LNLDO
VDDIO_RF for RF Switches
BT Class 1 PA
VIO 1.8–3.3V
OTP (3.3V)
1.2V 1.2V
1.35V
1.2V
Loads Not
to Power
Supply Noise
to Power Supply
Noise
Shaded areas are internal to the CYW43340.
VBAT
2.9–4.8V
WL_REG_ON
BT_REG_ON
VIO 1.8–3.3V
WLBGA conĮ
shown.
Internal
LNLDO
Internal
LNLDO HSIC-AVDD (DFLL)
WL RF – AFE WL RF – TX WL RF – VCO, LOGEN
WL RF – LNA WL RF – Rx, Rcal FM LNA, Mixer
XO WL RF – Synth/RF PLL WL RF – BG WL OTP (1.2V)
BT RF WL BB PLL WL Digital and Mem
BT Digital and Mem
Always On/State Ret. Island
CLPO/Ext. LPO Buīer HSIC-DVDD/SDIO
VDDIO (sdio/spi, uart, coex, gpio, jtag, bt-pcm, bt-uart
OTP (3.3V) iPA, iPAD
LDO2P5
Max. 70 mA
2.5V
Core Buck
Regulator
Max. 372 mA
Internal
LPLDO1
Internal
LPLDO2
LDO3P3
Max. 450 mA
3.3V
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Document Number: 002-14943 Rev. *N Page 9 of 96
PRELIMINARY CYW43340
2.2 WLAN Power Management
The CYW43340 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the
chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current
and supply voltages. Additionally, the CYW43340 integrated RAM is a high Vt memory with dynamic clock control. The dominant
supply current consumed by the RAM is leakage current only. Additionally, the CYW43340 includes an advanced WLAN power
management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW43340 into various
power management states appropriate to the current environment and activities that are being performed. The power management
unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a
table that describes the relationship between resources and the time needed to enable and disable them. Power up sequences are
fully programmable. Configurable, free-running counters (running at 32.768 kHz LPO clock) in the PMU sequencer are used to turn
on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode.
Slower clock speeds are used wherever possible.
The CYW43340 WLAN power states are described as follows:
■Active mode— All WLAN blocks in the CYW43340 are powered up and fully functional with active carrier sensing and frame
transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock
speeds are dynamically adjusted by the PMU sequencer.
■Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW43340 remains
powered up in an IDLE state. All main clocks (PLL, crystal oscillator or TCXO) are shut down to reduce active power to the minimum.
The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to
wake up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current.
■Deep-sleep mode—Most of the chip including both analog and digital domains and most of the regulators are powered off. Logic
states in the digital core are saved and preserved into a retention memory in the always-ON domain before the digital core is powered
off. Upon a wake-up event triggered by the PMU timers, an external interrupt or a host resume through the HSIC or SDIO bus, logic
states in the digital core are restored to their pre-deep-sleep settings to avoid lengthy HW re-initialization.
■Power-down mode—The CYW43340 is effectively powered off by shutting down all internal regulators. The chip is brought out of
this mode by external logic re-enabling the internal regulators.
2.3 PMU Sequencing
The PMU sequencer is responsible for minimizing system power consumption. It enables and disables various system resources
based on a computation of the required resources and a table that describes the relationship between resources and the time needed
to enable and disable them.
Resource requests may come from several sources: clock requests from cores, the minimum resources defined in the Resource Min
register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of
resources required to produce the requested clocks.
Each resource is in one of four states: enabled, disabled, transition_on, and transition_off and has a timer that contains 0 when the
resource is enabled or disabled and a non-zero value in the transition states. The timer is loaded with the time_on or time_off value
of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements on each 32.768 kHz
PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is
0, the resource can go immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can go
immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or
the timer load-decrement sequence.
During each clock cycle, the PMU sequencer performs the following actions:
1. Computes the required resource set based on requests and the resource dependency table.
2. Decrements all timers whose values are non zero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource
and inverts the ResourceState bit.
3. Compares the request with the current resource status and determines which resources must be enabled or disabled.
4. Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered up dependents.
5. Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.
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