Cypress CYW43340 User manual

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PRELIMINARY CYW43340
Single-Chip, Dual-Band (2.4 GHz/5 GHz)
IEEE 802.11 a/b/g/n MAC/Baseband/
Radio with Integrated Bluetooth 5.0
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-14943 Rev. *N Revised Wednesday, March 24, 2021
General Description
The Cypress CYW43340 single–chip quad–radio device provides the highest level of integration for wearables, Internet of Things and
gateway applications, with integrated dual band (2.4 GHz / 5 GHz) IEEE 802.11 a/b/g and single–stream IEEE 802.11n MAC/
baseband/radio, and Bluetooth 5.0. The CYW43340 includes integrated power amplifiers and LNAs for the 2.4 GHz and 5 GHz WLAN
bands, and an integrated 2.4 GHz T/R switch. This greatly reduces the external part count, PCB footprint, and cost of the solution.
Using advanced design techniques and process technology to reduce active and idle power, the CYW43340 is designed to address
the needs of mobile devices that require minimal power consumption and compact size. It includes a power management unit which
simplifies the system power topology and allows for operation directly from a mobile platform battery while maximizing battery life.
The CYW43340 implements the highly sophisticated Enhanced Collaborative Coexistence algorithms and hardware mechanisms,
allowing for an extremely collaborative Bluetooth coexistence scheme along with coexistence support for external radios (such as
cellular and LTE, GPS, WiMAX, and Ultra–Wideband) and a single shared 2.4 GHz antenna for Bluetooth and WLAN. As a result,
enhanced overall quality for simultaneous voice, video, and data transmission in an IoT or wearable application is achieved.
For the WLAN section, two host interface options are included: an SDIO v2.0 interface and a High-Speed Inter-Chip (HSIC) interface
(a USB 2.0 derivative for short-distance on-board connections). An independent, high-speed UART is provided for the Bluetooth host
interface.
Features
IEEE 802.11x Key Features
■Dual–band 2.4 GHz and 5 GHz IEEE 802.11
a/b/g/n
■Single–stream IEEE 802.11n support for 20 MHz and 40 MHz
channels provides PHY layer rates up to 150 Mbps for typical
upper–layer throughput in excess of 90 Mbps.
■Supports a single 2.4 GHz antenna shared between WLAN and
Bluetooth.
■Shared Bluetooth and 2.4 GHz WLAN receive signal path elimi-
nates the need for an external power splitter while maintaining
excellent sensitivity for both Bluetooth and WLAN.
■Internal fractional nPLL allows support for a wide range of
reference clock frequencies
■Supports IEEE 802.15.2 external coexistence interface to
optimize bandwidth utilization with other co–located wireless
technologies such as GPS, WiMAX, or UWB
■Supports standard SDIO v2.0 host interfaces.
■Alternative host interface supports HSIC v1.0 (short–distance
USB device)
■Integrated ARM® Cortex–M3™ processor and on–chip
memory for complete WLAN subsystem functionality,
minimizing the need to wake up the applications processor for
standard WLAN functions. This allows for further minimization
of power consumption, while maintaining the ability to field
upgrade with future features. On–chip memory includes 512
KB SRAM and 640 KB ROM.
■OneDriver™ software architecture for easy migration from
existing embedded WLAN and Bluetooth devices as well as
future devices.
Bluetooth Key Features
■Qualified for Bluetooth Core Specification 5.0:
❐QDID: 108508
❐Declaration ID: D035926
■Bluetooth Class 1 or Class 2 transmitter operation
■Supports extended Synchronous Connections (eSCO), for
enhanced voice quality by allowing for retransmission of
dropped packets.
■Adaptive Frequency Hopping (AFH) for reducing radio
frequency interference
■Interface support: Host Controller Interface (HCI) using a high-
speed UART interface and PCM for audio data
■Low power consumption improves battery life of handheld
devices.
■Supports multiple simultaneous Advanced Audio Distribution
Profiles (A2DP) for stereo sound.
■Automatic frequency detection for standard crystal and TCXO
values
General Features
■Supports battery voltage range from 2.9V to 4.8V supplies with
internal switching regulator.
■Programmable dynamic power management
■3072-bit OTP for storing board parameters
■Routable on low–cost 1x1 PCB stack–ups
■141-ball WLBGA package(5.67 mm × 4.47 mm, 0.4 mm pitch)
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Document Number: 002-14943 Rev. *N Page 2 of 96
PRELIMINARY CYW43340
■Security:
❐WPA™ and WPA2™ (Personal) support for powerful encryp-
tion and authentication
❐AES in WLAN hardware for faster data encryption and IEEE
802.11i compatibility
❐Reference WLAN subsystem provides Cisco® Compatible
Extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0)
❐Reference WLAN subsystem provides Wi–Fi Protected Set-
up (WPS)
■Worldwide regulatory support: Global products supported with
worldwide homologated design
Figure 1. Functional Block Diagram
VIO VBAT
CYW43340
WLAN
HostI/F
Bluetooth
HostI/F
WL_REG_ON
SDIO*
WL_IRQ
BT_REG_ON
UART
BT_DEV_WAKE
BT_HOST_WAKE
CLK_REQ
HSIC
PCM/I2S
2.4GHzWLAN+BluetoothTx/Rx CBF
FEMor
T/R
Switch
5GHzWLANTx
5GHzWLANRx
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Document Number: 002-14943 Rev. *N Page 3 of 96
PRELIMINARY CYW43340
Contents
1. Introduction ................................................................... 4
1.1 Overview ............................................................... 4
1.2 Features ................................................................ 5
1.3 Standards Compliance .......................................... 6
2. Power Supplies and Power Management ...................7
2.1 Power Supply Topology ........................................ 7
2.2 WLAN Power Management ................................... 9
2.3 PMU Sequencing .................................................. 9
2.4 Power-Off Shutdown ........................................... 10
2.5 Power-Up/Power-Down/Reset Circuits ...............10
3. Frequency References ............................................... 11
3.1 Crystal Interface and Clock Generation .............. 11
3.2 TCXO ..................................................................11
3.3 Frequency Selection ............................................ 13
3.4 External 32.768 kHz Low-Power Oscillator ......... 14
4. Bluetooth Subsystem Overview ................................15
4.1 Features .............................................................. 15
4.2 Bluetooth Radio ................................................... 16
5. Bluetooth Baseband Core ......................................... 17
5.1 Bluetooth 5.0 Features ........................................ 17
5.2 Link Control Layer ............................................... 17
5.3 Test Mode Support .............................................. 17
5.4 Bluetooth Power Management Unit ..................... 18
5.5 Adaptive Frequency Hopping ..............................21
5.6 Advanced Bluetooth/WLAN Coexistence ............21
5.7 Fast Connection (Interlaced Page and Inquiry
Scans) ................................................................ 21
6. Microprocessor and Memory Unit for Bluetooth ..... 22
6.1 RAM, ROM, and Patch Memory ..........................22
6.2 Reset ................................................................... 22
7. Bluetooth Peripheral Transport Unit ........................ 23
7.1 PCM Interface ..................................................... 23
7.2 UART Interface .................................................... 30
7.3 I2S Interface ........................................................ 31
8. WLAN Global Functions ............................................ 34
8.1 WLAN CPU and Memory Subsystem .................. 34
8.2 One-Time Programmable Memory ......................34
8.3 GPIO Interface .................................................... 34
8.4 External Coexistence Interface ...........................34
8.5 UART Interface .................................................... 35
8.6 JTAG Interface .................................................... 35
9. WLAN Host Interfaces ................................................ 36
9.1 SDIO v2.0 ............................................................ 36
9.2 HSIC Interface ..................................................... 38
10. Wireless LAN MAC and PHY ...................................39
10.1 MAC Features ................................................... 39
10.2 WLAN PHY Description ..................................... 42
11. WLAN Radio Subsystem .......................................... 44
11.1 Receiver Path .................................................... 44
11.2 Transmit Path .................................................... 44
11.3 Calibration ......................................................... 44
12. Pinout and Signal Descriptions .............................. 45
12.1 Signal Assignments ........................................... 45
12.2 Signal Descriptions ............................................ 45
12.3 I/O States .......................................................... 54
13. DC Characteristics ................................................... 57
13.1 Absolute Maximum Ratings ............................... 57
13.2 Environmental Ratings ...................................... 57
13.3 Electrostatic Discharge Specifications .............. 58
13.4 Recommended Operating Conditions and DC
Characteristics .................................................... 58
14. Bluetooth RF Specifications .................................... 60
15. WLAN RF Specifications .......................................... 67
15.1 Introduction ........................................................ 67
15.2 2.4 GHz Band General RF Specifications ......... 68
15.3 WLAN 2.4 GHz Receiver Performance
Specifications ..................................................... 68
15.4 WLAN 2.4 GHz Transmitter Performance
Specifications ..................................................... 72
15.5 WLAN 5 GHz Receiver Performance
Specifications ..................................................... 73
15.6 WLAN 5 GHz Transmitter Performance
Specifications ..................................................... 75
15.7 General Spurious Emissions Specifications ...... 76
16. Internal Regulator Electrical Specifications .......... 77
16.1 Core Buck Switching Regulator ......................... 77
16.2 3.3V LDO (LDO3P3) .........................................78
16.3 2.5V LDO (LDO2P5) .........................................79
16.4 HSICDVDD LDO ............................................... 79
16.5 CLDO ................................................................ 80
16.6 LNLDO .............................................................. 81
17. System Power Consumption ...................................82
17.1 WLAN Current Consumption ............................. 82
17.2 Bluetooth and BLE Current Consumption ......... 83
18. Interface Timing and AC Characteristics ............... 84
18.1 SDIO Timing ...................................................... 84
18.2 HSIC Interface Specifications ............................86
18.3 JTAG Timing ..................................................... 86
19. Power-Up Sequence and Timing ............................. 87
19.1 Sequencing of Reset and Regulator Control
Signals ................................................................ 87
20. Package Information ................................................ 90
20.1 Package Thermal Characteristics ..................... 90
20.2 Junction Temperature Estimation and PSIJT
Versus THETAJC ................................................ 90
20.3 Environmental Characteristics ........................... 90
21. Mechanical Information ........................................... 91
22. Ordering Information ................................................ 93
23. Additional Information ............................................. 93
23.1 Acronyms and Abbreviations ............................. 93
23.2 IoT Resources ................................................... 93
Document History ........................................................... 94
Sales, Solutions, and Legal Information ...................... 96
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Document Number: 002-14943 Rev. *N Page 4 of 96
PRELIMINARY CYW43340
1. Introduction
1.1 Overview
The Cypress CYW43340 single-chip device provides the highest level of integration for wearables, audio and IoT applications, with
integrated IEEE 802.1 a/b/g/n MAC/baseband/radio, and Bluetooth 5.0. It provides a small form-factor solution with minimal external
components to drive down cost, flexibility in size, form, and function. Comprehensive power management circuitry and software ensure
the system can meet the needs of highly mobile devices that require minimal power consumption and reliable operation.
Figure 2 shows the interconnect of all the major physical blocks in the CYW43340 and their associated external interfaces, which are
described in greater detail in the following sections.
Figure 2. Block Diagram
Chip
Common
BT RF
Modem
AXI Backplane
ARMCM3
AXI2AHB
AHB2AXI
SDIOD
USB20D
HSIC
DOT11MAC (D11)
1x1 11N PHY
2.4 GHz / 5 GHz Dualband Radio
SoCSRAM
RAM512KB
ROM640KB
AHB Bus Matrix
UART
ARMCM3
WLAN
Master
Slave
FM
Receiver
RAM
ROM
I2S
PCM
Port Control
RX/TX
LCU
APU
BlueRF
BLE
AXI2APB
DMA
JTAG
Master
AHB2APB
Timers
GPIO
WD
Pause
Registers
Shared LNA
Control
WLAN BT Access
ARM CM0
RAM
ROM
SWP DIG
AHB
Bridge
Analog PMU
PMU
Controller
CLB
JTAG
From
WLAN
BT
To
WLAN
BT
PMU
XTAL/Radio/Pads etc
WLAN
BT/FM
GCI
From
WLAN
BT
To
WLAN
BT
FLL
Clk rst
To
CLB
To
CLB
To
GCI
LTE LTE
CLB
UPI
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Document Number: 002-14943 Rev. *N Page 5 of 96
PRELIMINARY CYW43340
1.2 Features
The CYW43340 supports the following WLAN and Bluetooth features:
■IEEE 802.11a/b/g/n dual-band radio with internal Power Amplifiers, LNAs, and T/R switches
■Bluetooth 5.0 with integrated Class 1 PA
■Concurrent Bluetooth, and WLAN operation
■On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality
■Single- and dual-antenna support
❐Single antenna with shared LNA
❐Simultaneous BT/WLAN receive with single antenna
■WLAN host interface options:
❐SDIO v2.0, including default and high-speed timing.
❐HSIC (USB device interface for short distance on-board applications)
■BT host digital interface (can be used concurrently with above interfaces):
❐UART (up to 4 Mbps)
■ECI—enhanced coexistence support, ability to coordinate BT SCO transmissions around WLAN receives
■I2S/PCM for BT audio
■HCI high-speed UART (H4, H5) transport support
■Wideband speech support (16 bits linear data, MSB first, left justified at 4K samples/s for transparent air coding, both through I2S
and PCM interface)
■Bluetooth SmartAudio® technology improves voice and music quality to headsets
■Bluetooth low power inquiry and page scan
■Bluetooth Low Energy (BLE) support
■Bluetooth Packet Loss Concealment (PLC)
■Bluetooth Wideband Speech (WBS)
■Audio rate-matching algorithms
■Multiple simultaneous A2DP audio stream
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Document Number: 002-14943 Rev. *N Page 6 of 96
PRELIMINARY CYW43340
1.3 Standards Compliance
The CYW43340 supports the following standards:
■Bluetooth 5.0 (including Bluetooth Low Energy)
■IEEE 802.11n—Handheld Device Class (Section 11)
■IEEE 802.11a
■IEEE 802.11b
■IEEE 802.11g
■IEEE 802.11d
■IEEE 802.11h
■IEEE 802.11i
The CYW43340 will support the following future drafts/standards:
■IEEE 802.11r—Fast Roaming (between APs)
■IEEE 802.11k—Resource Management
■IEEE 802.11w—Secure Management Frames
■IEEE 802.11 Extensions:
❐IEEE 802.11e QoS Enhancements (as per the WMM® specification is already supported)
❐IEEE 802.11h 5 GHz Extensions
❐IEEE 802.11i MAC Enhancements
❐IEEE 802.11r Fast Roaming Support
❐IEEE 802.11k Radio Resource Measurement
The CYW43340 supports the following security features and proprietary protocols:
■Security:
❐WEP
❐WPA™ Personal
❐WPA2™ Personal
❐WMM
❐WMM-PS (U-APSD)
❐WMM-SA
❐WAPI
❐AES (Hardware Accelerator)
❐TKIP (host-computed)
❐CKIP (SW Support)
■Proprietary Protocols:
❐CCXv2
❐CCXv3
❐CCXv4
❐CCXv5
■IEEE 802.15.2 Coexistence Compliance—on silicon solution compliant with IEEE 3 wire requirements
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Document Number: 002-14943 Rev. *N Page 7 of 96
PRELIMINARY CYW43340
2. Power Supplies and Power Management
2.1 Power Supply Topology
One Buck regulator, multiple LDO regulators, and a Power Management Unit (PMU) are integrated into the CYW43340. All regulators
are programmable via the PMU. These blocks simplify power supply design for Bluetooth, and WLAN in embedded designs.
A single VBAT (2.9–4.8V) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in
the CYW43340.
Two control signals, BT_REG_ON and WL_REG_ON, are used to power-up the regulators and take the respective section out of
reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only
when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO may be turned off/on based on the dynamic
demands of the digital baseband.
The CYW43340 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNDLO
regulators. When in this state, LPLDO1 and LPLDO2 (which are low-power linear regulators that are supplied by the system VIO
supply) provide the CYW43340 with all the voltages it requires, further reducing leakage currents.
2.1.1 CYW43340 PMU Features
■VBAT to 1.35Vout (372 mA maximum) Core-Buck (CBUCK) switching regulator
■VBAT to 3.3Vout (450 mA maximum) LDO3P3 (external-capacitor)
■VBAT to 2.5Vout (70 mA maximum) LDO2P5 (external-capacitor)
■1.35V to 1.2Vout (100 mA maximum) LNLDO (external-capacitor)
■1.35V to 1.2Vout (150 mA maximum) CLDO (external-capacitor)
■1.35V to 1.2Vout (80 mA maximum) HSICDVDD LDO (external-capacitor)
■Additional internal LDOs (not externally accessible)
Figure 3 on page 8 shows the regulators and a typical power topology.
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Document Number: 002-14943 Rev. *N Page 8 of 96
PRELIMINARY CYW43340
Figure 3. Typical Power Topology
LNLDO
Max 100 mA
CLDO
Max 150 mA
Internal
LNLDO
Internal
LNLDO
Internal
LNLDO
Internal
LNLDO
VDDIO_RF for RF Switches
BT Class 1 PA
VIO 1.8–3.3V
OTP (3.3V)
1.2V 1.2V
1.35V
1.2V
Loads Not
to Power
Supply Noise
to Power Supply
Noise
Shaded areas are internal to the CYW43340.
VBAT
2.9–4.8V
WL_REG_ON
BT_REG_ON
VIO 1.8–3.3V
WLBGA conĮ
shown.
Internal
LNLDO
Internal
LNLDO HSIC-AVDD (DFLL)
WL RF – AFE WL RF – TX WL RF – VCO, LOGEN
WL RF – LNA WL RF – Rx, Rcal FM LNA, Mixer
XO WL RF – Synth/RF PLL WL RF – BG WL OTP (1.2V)
BT RF WL BB PLL WL Digital and Mem
BT Digital and Mem
Always On/State Ret. Island
CLPO/Ext. LPO Buīer HSIC-DVDD/SDIO
VDDIO (sdio/spi, uart, coex, gpio, jtag, bt-pcm, bt-uart
OTP (3.3V) iPA, iPAD
LDO2P5
Max. 70 mA
2.5V
Core Buck
Regulator
Max. 372 mA
Internal
LPLDO1
Internal
LPLDO2
LDO3P3
Max. 450 mA
3.3V
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Document Number: 002-14943 Rev. *N Page 9 of 96
PRELIMINARY CYW43340
2.2 WLAN Power Management
The CYW43340 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the
chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current
and supply voltages. Additionally, the CYW43340 integrated RAM is a high Vt memory with dynamic clock control. The dominant
supply current consumed by the RAM is leakage current only. Additionally, the CYW43340 includes an advanced WLAN power
management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW43340 into various
power management states appropriate to the current environment and activities that are being performed. The power management
unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a
table that describes the relationship between resources and the time needed to enable and disable them. Power up sequences are
fully programmable. Configurable, free-running counters (running at 32.768 kHz LPO clock) in the PMU sequencer are used to turn
on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode.
Slower clock speeds are used wherever possible.
The CYW43340 WLAN power states are described as follows:
■Active mode— All WLAN blocks in the CYW43340 are powered up and fully functional with active carrier sensing and frame
transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock
speeds are dynamically adjusted by the PMU sequencer.
■Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW43340 remains
powered up in an IDLE state. All main clocks (PLL, crystal oscillator or TCXO) are shut down to reduce active power to the minimum.
The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to
wake up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current.
■Deep-sleep mode—Most of the chip including both analog and digital domains and most of the regulators are powered off. Logic
states in the digital core are saved and preserved into a retention memory in the always-ON domain before the digital core is powered
off. Upon a wake-up event triggered by the PMU timers, an external interrupt or a host resume through the HSIC or SDIO bus, logic
states in the digital core are restored to their pre-deep-sleep settings to avoid lengthy HW re-initialization.
■Power-down mode—The CYW43340 is effectively powered off by shutting down all internal regulators. The chip is brought out of
this mode by external logic re-enabling the internal regulators.
2.3 PMU Sequencing
The PMU sequencer is responsible for minimizing system power consumption. It enables and disables various system resources
based on a computation of the required resources and a table that describes the relationship between resources and the time needed
to enable and disable them.
Resource requests may come from several sources: clock requests from cores, the minimum resources defined in the Resource Min
register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of
resources required to produce the requested clocks.
Each resource is in one of four states: enabled, disabled, transition_on, and transition_off and has a timer that contains 0 when the
resource is enabled or disabled and a non-zero value in the transition states. The timer is loaded with the time_on or time_off value
of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements on each 32.768 kHz
PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is
0, the resource can go immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can go
immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or
the timer load-decrement sequence.
During each clock cycle, the PMU sequencer performs the following actions:
1. Computes the required resource set based on requests and the resource dependency table.
2. Decrements all timers whose values are non zero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource
and inverts the ResourceState bit.
3. Compares the request with the current resource status and determines which resources must be enabled or disabled.
4. Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered up dependents.
5. Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.
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Document Number: 002-14943 Rev. *N Page 10 of 96
PRELIMINARY CYW43340
2.4 Power-Off Shutdown
The CYW43340 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices
in the system, remain operational. When the CYW43340 is not needed in the system, VDDIO_RF and VDDC are shut down while
VDDIO remains powered. This allows the CYW43340 to be effectively off while keeping the I/O pins powered so that they do not draw
extra current from any other devices connected to the I/O.
During a low-power shut-down state, provided VDDIO remains applied to the CYW43340, all outputs are tristated, and most inputs
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths
or create loading on any digital signals in the system, and enables the CYW43340 to be fully integrated in an embedded device and
take full advantage of the lowest power-savings modes.
Two signals on the CYW43340, the frequency reference input (WRF_XTAL_CAB_OP) and the LPO_IN input, are designed to be high-
impedance inputs that do not load down the driving signal even if the chip does not have VDDIO power applied to it.
When the CYW43340 is powered on from this state, it is the same as a normal power-up and the device does not retain any information
about its state from before it was powered down.
2.5 Power-Up/Power-Down/Reset Circuits
The CYW43340 has two signals (see Table 2) that enable or disable the Bluetooth and WLAN circuits and the internal
regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required
power-up sequences, see Section 19.: “Power-Up Sequence and Timing,” on page 87.
Table 2. Power-Up/Power-Down/Reset Control Signals
Signal Description
WL_REG_ON This signal is used by the PMU (with BT_REG_ON) to power up the WLAN section. It is also OR-gated with the
BT_REG_ON input to control the internal CYW43340 regulators. When this pin is high, the regulators are enabled
and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and
WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 k pull-down resistor that
is enabled by default. It can be disabled through programming.
BT_REG_ON This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal
CYW43340 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has
an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming.
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Document Number: 002-14943 Rev. *N Page 11 of 96
PRELIMINARY CYW43340
3. Frequency References
An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency
reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. In addition, a low-power oscillator
(LPO) is provided for lower power mode timing.
Note: The crystal and TCXO implementations have different power supplies (WRF_XTAL_VDD1P2 for crystal,
WRF_TCXO_VDD for TCXO).
3.1 Crystal Interface and Clock Generation
The CYW43340 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator
including all external components is shown in Figure 4. Consult the reference schematics for the latest configuration.
Figure 4. Recommended Oscillator Configuration
A fractional-N synthesizer in the CYW43340 generates the radio frequencies, clocks, and data/packet timing, enabling it to operate
using a wide selection of frequency references.
For SDIO and HSIC applications the default frequency reference is a 37.4 MHz crystal or TCXO. The signal characteristics for the
crystal interface are listed in Table 3 on page 12.
Note: Although the fractional-N synthesizer can support alternative reference frequencies, frequencies other than the
default require support to be added in the driver, plus additional extensive system testing. Contact Cypress for further
details.
3.2 TCXO
As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the Phase
Noise requirements listed in Ta bl e 3 . When the clock is provided by an external TCXO, there are two possible connection methods,
as shown in Figure 5 and Figure 6:
1. If the TCXO is dedicated to driving the CYW43340, it should be connected to the WRF_XTAL_OP pin through an external 1000
pF coupling capacitor, as shown in Figure 5. The internal clock buffer connected to this pin will be turned OFF when the CYW43340
goes into sleep mode. When the clock buffer turns ON and OFF there will be a small impedance variation. If the TCXO is to be
shared with another device, such as a GPS receiver, and impedance variation is not allowed, a dedicated external clock buffer will
be needed. Power must be supplied to the WRF_XTAL_VDD1P2 pin.
2. For 2.4 GHz operation only, an alternative is to DC-couple the TCXO to the WRF_TCXO_CK pin, as shown in Figure 6. Use this
method when the same TCXO is shared with other devices and a change in the input impedance is not acceptable because it may
cause a frequency shift that cannot be tolerated by the other device sharing the TCXO. This pin is connected to a clock buffer
powered from WRF_TCXO_VDD. If the power supply to this buffer is always on (even in sleep mode), the clock buffer is always
on, thereby ensuring a constant input impedance in all states of the device. The maximum current drawn from WRF_TCXO_VDD
is approximately 500 µA.
12–27pF
12–27pF
WRF_XTAL_ON
WRF_XTAL_OP
C
C
Xohms*
*Resistorvalue
determinedbycrystal
drivelevel.Seereference
schematicsfordetails.
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Document Number: 002-14943 Rev. *N Page 12 of 96
PRELIMINARY CYW43340
Figure 5. Recommended Circuit to Use with an External Dedicated TCXO
Figure 6. Recommended Circuit to Use with an External Shared TCXO
Table 3. Crystal Oscillator and External Clock – Requirements and Performance
Parameter Conditions/Notes CrystalaExternal Frequency
Referenceb,c
Min Typ Max Min Typ Max Units
Frequency – Between 19.2 MHz and 52 MHzd,e
Crystal load capacitance – – 12 ––––pF
ESR – ––60–––Ω
Drive level External crystal requirement 200f–––––µW
Input impedance
(WRF_XTAL_OP)
Resistive 30k 100k – 30k 100k – Ω
Capacitive ––7.5––7.5pF
Input impedance
(WRF_TCXO_IN)
Resistive –––30k100k–Ω
Capacitive –––––4pF
WRF_XTAL_OP
Input low level
DC-coupled digital signal –––0–0.2V
WRF_XTAL_OP
Input high level
DC-coupled digital signal –––1.0–1.26V
WRF_XTAL_OP
input voltage
AC-coupled analog signal
(see Figure 5)
–––400–1200mV
p-p
WRF_TCXO_IN
Input voltage
DC-coupled analog signal
(see Figure 6)
–––400–1980mV
p-p
TCXO
NC
1000pF
WRF_XTAL_OP
WRF_XTAL_ON
WRF_TCXO_CK
WRF_TCXO_VDD
TCXO
NC
WRF_TCXO_CK
WRF_XTAL_ON
WRF_XTAL_OP
Tootherdevices
WRF_TCXO_VDD
Toalwayspresent1.8Vsupply
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Document Number: 002-14943 Rev. *N Page 13 of 96
PRELIMINARY CYW43340
3.3 Frequency Selection
Any frequency within the ranges specified for the crystal and TCXO reference may be used. These include not only the standard
handset reference frequencies of 19.2, 19.44, 19.68, 19.8, 20, 26, 37.4, and 52 MHz, but also other frequencies in this range, with
approximately 80 Hz resolution. The CYW43340 must have the reference frequency set correctly in order for any of the UART or PCM
interfaces to function correctly, since all bit timing is derived from the reference frequency.
Note: The fractional-N synthesizer can support many reference frequencies. However, frequencies other than the default
require support to be added in the driver plus additional, extensive system testing. Contact Cypress for further details.
The reference frequency for the CYW43340 may be set in the following ways:
■Set the xtalfreq=xxxxx parameter in the nvram.txt file (used to load the driver) to correctly match the crystal frequency.
■Auto-detect any of the standard handset reference frequencies using an external LPO clock.
For applications such as handsets and portable smart communication devices, where the reference frequency is one of the standard
frequencies commonly used, the CYW43340 automatically detects the reference frequency and programs itself to the correct
reference frequency. In order for auto frequency detection to work correctly, the CYW43340 must have a valid and stable 32.768 kHz
LPO clock that meets the requirements listed in Table 4 on page 14 and is present during power-on reset.
Frequency tolerance over
the lifetime of the
equipment, including
temperature
Without trimming –20 – 20 –20 – 20 ppm
Duty cycle 37.4 MHz clock –––405060%
Phase Noise
(802.11b/g)
37.4 MHz clock at 10 kHz offset––––––131dBc/Hz
37.4 MHz clock at 100 kHz or greater
offset
––––––138dBc/Hz
Phase Noise
(802.11a)
37.4 MHz clock at 10 kHz offset––––––139dBc/Hz
37.4 MHz clock at 100 kHz or greater
offset
––––––146dBc/Hz
Phase Noise
(802.11n, 2.4 GHz)
37.4 MHz clock at 10 kHz offset––––––136dBc/Hz
37.4 MHz clock at 100 kHz or greater
offset
––––––143dBc/Hz
Phase Noise
(802.11n, 5 GHz)
37.4 MHz clock at 10 kHz offset––––––144dBc/Hz
37.4 MHz clock at 100 kHz or greater
offset
––––––151dBc/Hz
a.(Crystal)UseWRF_XTAL_OPandWRF_XTAL_ON,internalpowertopinWRF_XTAL_VDD1P2.
b.(TCXO)See“TCXO”onpage 11foralternativeconnectionmethods.
c.Foraclockreferenceotherthan37.4MHz,20×log10(f/37.4)dBshouldbeaddedtothelimits,wheref=thereferenceclockfrequencyinMHz.
d.BT_TM6shouldbetiedlowfora52MHzclockreference.Forotherfrequencies,BT_TM6shouldbetiedhigh.Notethat52MHzisnotanauto-detected
frequencyusingtheLPOclock.
e.Thefrequencystepsizeisapproximately80Hzresolution.
f.Thecrystalshouldbecapableofhandlinga200uWdrivelevelfromtheCYW43340.
Table 3. Crystal Oscillator and External Clock – Requirements and Performance (Cont.)
Parameter Conditions/Notes CrystalaExternal Frequency
Referenceb,c
Min Typ Max Min Typ Max Units
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Document Number: 002-14943 Rev. *N Page 14 of 96
PRELIMINARY CYW43340
3.4 External 32.768 kHz Low-Power Oscillator
The CYW43340 uses a secondary low frequency clock for low-power-mode timing. Either the internal low-precision LPO or an external
32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process, voltage,
and temperature, which is adequate for some applications. However, a trade-off caused by this wide LPO tolerance is a small current
consumption increase during WLAN power save mode that is incurred by the need to wake up earlier to avoid missing beacons.
Whenever possible, the preferred approach for WLAN is to use a precision external 32.768 kHz clock that meets the requirements
listed in Table 4.
Note: BT operations require the use of an external LPO that meets the requirements listed in Table 4 .
Table 4. External 32.768 kHz Sleep Clock Specifications
Parameter LPO Clock Units
Nominal input frequency 32.768 kHz
Frequency accuracy ±200 ppm
Duty cycle 30–70 %
Input signal amplitude 200–1800 mV, p-p
Signal type Square-wave or sine-wave –
Input impedancea
a.Whenpowerisappliedorswitchedoff.
>100k
<5
Ω
pF
Clock jitter (during initial start-up) <10,000 ppm
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Document Number: 002-14943 Rev. *N Page 15 of 96
PRELIMINARY CYW43340
4. Bluetooth Subsystem Overview
The Cypress CYW43340 is a Bluetooth 5.0-compliant, baseband processor/2.4 GHz transceiver.
The CYW43340 is the optimal solution for any Bluetooth voice and/or data application. The Bluetooth subsystem presents a standard
Host Controller Interface (HCI) via a high speed UART and PCM for audio. The CYW43340 is qualified for Bluetooth 5.0 and supports
all Bluetooth 4.0 features including BR/EDR and LE.
The CYW43340 Bluetooth radio transceiver provides enhanced radio performance to meet the most stringent mobile phone
temperature applications and the tightest integration into mobile handsets and portable devices. It is fully compatible with any of the
standard TCXO frequencies and provides full radio compatibility to operate simultaneously with GPS, WLAN, and cellular radios.
The Bluetooth transmitter also features a Class 1 power amplifier with Class 2 capability.
4.1 Features
Major Bluetooth features of the CYW43340 include:
■Supports key features of upcoming Bluetooth standards
■Qualified for Bluetooth Core Specification 5.0 and supports all Bluetooth 4.0 features
■UART baud rates up to 4 Mbps
■Supports all Bluetooth 4.0 packet types
■Supports maximum Bluetooth data rates over HCI UART
■Multipoint operation with up to seven active slaves
❐Maximum of seven simultaneous active ACL links
❐Maximum of three simultaneous active SCO and eSCO connections with scatternet support
■Trigger Broadcom fast connect (TBFC)
■Narrowband and wideband packet loss concealment
■Scatternet operation with up to four active piconets with background scan and support for scatter mode
■High-speed HCI UART transport support with low-power out-of-band BT_DEV_WAKE and BT_HOST_WAKE signaling (see “Host
Controller Power Management” on page 18)
■Channel quality driven data rate and packet type selection
■Standard Bluetooth test modes
■Extended radio and production test mode features
■Full support for power savings modes
❐Bluetooth clock request
❐Bluetooth standard sniff
❐Deep-sleep modes and software regulator shutdown
■TCXO input and auto-detection of all standard handset clock frequencies. Also supports a low-power crystal, which can be used
during power save mode for better timing accuracy.
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Document Number: 002-14943 Rev. *N Page 16 of 96
PRELIMINARY CYW43340
4.2 Bluetooth Radio
The CYW43340 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has
been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz
unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification and EDR specification and meets or exceeds the
requirements to provide the highest communication link quality of service.
4.2.1 Transmit
The CYW43340 features a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block
and upconverted to the 2.4 GHz ISM band in the transmitter path. The transmitter path consists of signal filtering, I/Q upconversion,
output power amplifier, and RF filtering. The transmitter path also incorporates /4–DQPSK for 2 Mbps and 8–DPSK for 3 Mbps to
support EDR. The transmitter section is compatible to the Bluetooth Low Energy specification. The transmitter PA bias can also be
adjusted to provide Bluetooth class 1 or class 2 operation.
4.2.2 Digital Modulator
The digital modulator performs the data modulation and filtering required for the GFSK, /4–DQPSK, and 8–DPSK signal. The fully
digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much
more stable than direct VCO modulation schemes.
4.2.3 Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit-
synchronization algorithm.
4.2.4 Power Amplifier
The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. This provides
greater flexibility in front-end matching and filtering. Due to the linear nature of the PA combined with some integrated filtering, external
filtering is required to meet the Bluetooth and regulatory harmonic and spurious requirements. For integrated mobile handset appli-
cations in which Bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near thermal noise levels
for spurious and radiated noise emissions. The transmitter features a sophisticated on-chip transmit signal strength indicator (TSSI)
block to keep the absolute output power variation within a tight range across process, voltage, and temperature.
4.2.5 Receiver
The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit
synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel
filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology with built-in out-of-band attenuation
enables the CYW43340 to be used in most applications with minimal off-chip filtering. For integrated handset operation, in which the
Bluetooth function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the
receiver by the cellular transmit signal.
4.2.6 Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit
synchronization algorithm.
4.2.7 Receiver Signal Strength Indicator
The radio portion of the CYW43340 provides a Receiver Signal Strength Indicator (RSSI) signal to the baseband, so that the controller
can take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the
transmitter should increase or decrease its output power.
4.2.8 Local Oscillator Generation
Local Oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels.
The LO generation subblock employs an architecture for high immunity to LO pulling during PA operation. The CYW43340 uses an
internal RF and IF loop filter.
4.2.9 Calibration
The CYW43340 radio transceiver features an automated calibration scheme that is fully self contained in the radio. No user interaction
is required during normal operation or during manufacturing to provide the optimal performance. Calibration optimizes the perfor-
mance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters,
matching between key components, and key gain blocks. This takes into account process variation and temperature variation.
Calibration occurs transparently during normal operation during the settling time of the hops and calibrates for temperature variations
as the device cools and heats during normal operation in its environment.
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Document Number: 002-14943 Rev. *N Page 17 of 96
PRELIMINARY CYW43340
5. Bluetooth Baseband Core
The Bluetooth Baseband Core (BBC) implements all of the time critical functions required for high-performance Bluetooth operation.
The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,
handles data flow control, schedules SCO/ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages
data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these
functions, it independently handles HCI event types, and HCI command types.
The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of the TX/
RX data before sending over the air:
■Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC),
data decryption, and data dewhitening in the receiver.
■Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the
transmitter.
5.1 Bluetooth 5.0 Features
The BBC is qualified for Bluetooth Core Specification 5.0 and supports all Bluetooth 4.0 features, with the following benefits:
■Dual-mode classic Bluetooth and classic Low Energy (BT and BLE) operation.
■Low Energy Physical Layer
■Low Energy Link Layer
■Enhancements to HCI for Low Energy
■Low Energy Direct Test mode
■AES encryption
Note: The CYW43340 is compatible with the Bluetooth Low Energy operating mode, which provides a dramatic
reduction in the power consumption of the Bluetooth radio and baseband. The primary application for this mode is to
provide support for low data rate devices, such as sensors and remote controls.
5.2 Link Control Layer
The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU).
This layer consists of the command controller that takes commands from the software, and other controllers that are activated or
configured by the command controller, to perform the link control tasks. Each task performs a different state in the Bluetooth Link
Controller.
■Major states:
❐Standby
❐Connection
■Substates:
❐Page
❐Page Scan
❐Inquiry
❐Inquiry Scan
❐Sniff
❐BLE Adv
❐BLE Scan/Initiation
5.3 Test Mode Support
The CYW43340 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0.
This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.
In addition to the standard Bluetooth Test Mode, the CYW43340 also supports enhanced testing features to simplify RF debugging
and qualification and type-approval testing. These features include:
■Fixed frequency carrier wave (unmodulated) transmission
❐Simplifies some type-approval measurements (Japan)
❐Aids in transmitter performance analysis
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Document Number: 002-14943 Rev. *N Page 18 of 96
PRELIMINARY CYW43340
■Fixed frequency constant receiver mode
❐Receiver output directed to I/O pin
❐Allows for direct BER measurements using standard RF test equipment
❐Facilitates spurious emissions testing for receive mode
■Fixed frequency constant transmission
❐Eight-bit fixed pattern or PRBS-9
❐Enables modulated signal measurements with standard RF test equipment
5.4 Bluetooth Power Management Unit
The Bluetooth Power Management Unit (PMU) provides power management features that can be invoked by either software through
power management registers or packet handling in the baseband core. The power management functions provided by the CYW43340
are:
■RF Power Management
■Host Controller Power Management
■BBC Power Management
5.4.1 RF Power Management
The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz trans-
ceiver. The transceiver then processes the power-down functions accordingly.
5.4.2 Host Controller Power Management
When running in UART mode, the CYW43340 may be configured so that dedicated signals are used for power management hand-
shaking between the CYW43340 and the host. The basic power saving functions supported by those hand-shaking signals include
the standard Bluetooth defined power savings modes and standby modes of operation.
Tabl e 5 describes the power-control hand-shake signals used with the UART interface.
Table 5. Power Control Pin Description
Signal Type Description
BT_DEV_WAKE I Bluetooth device wake-up: Signal from the host to the CYW43340 indicating that the host requires
attention.
■Asserted: The Bluetooth device must wake-up or remain awake.
■Deasserted: The Bluetooth device may sleep when sleep criteria are met.
The polarity of this signal is software configurable and can be asserted high or low.
BT_HOST_WAKE O Host wake up. Signal from the CYW43340 to the host indicating that the CYW43340 requires attention.
■Asserted: host device must wake-up or remain awake.
■Deasserted: host device may sleep when sleep criteria are met.
The polarity of this signal is software configurable and can be asserted high or low.
CLK_REQ O The CYW43340 asserts CLK_REQ when Bluetooth, or WLAN directs the host to turn on the reference
clock. The CLK_REQ polarity is active-high. Add an external 100 kΩ pull-down resistor to ensure the
signal is deasserted when the CYW43340 powers up or resets when VDDIO is present.
Note: Pad function Control Register is set to 0 for these pins.
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Document Number: 002-14943 Rev. *N Page 19 of 96
PRELIMINARY CYW43340
Figure 7. Startup Signaling Sequence
5.4.3 BBC Power Management
Thefollowingarelow-poweroperationsfortheBBC:
■Physical layer packet-handling turns the RF on and off dynamically within transmit/receive packets.
■Bluetooth-specified low-power connection modes: sniff, hold, and park. While in these modes, the CYW43340 runs on the low-power
oscillator and wakes up after a predefined time period.
■A low-power shutdown feature allows the device to be turned off while the host and any other devices in the system remain operational.
When the CYW43340 is not needed in the system, the RF and core supplies are shut down while the I/O remains powered. This
allows the CYW43340 to effectively be off while keeping the I/O pins powered so they do not draw extra current from any other
devices connected to the I/O.
During the low-power shut-down state, provided VDDIO remains applied to the CYW43340, all outputs are tristated, and most input
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths
or create loading on any digital signals in the system and enables the CYW43340 to be fully integrated in an embedded device to take
full advantage of the lowest power-saving modes.
Two CYW43340 input signals are designed to be high-impedance inputs that do not load the driving signal even if the chip does not
have VDDIO power supplied to it: the frequency reference input (WRF_TCXO_IN) and the 32.768 kHz input (LPO). When the
CYW43340 is powered on from this state, it is the same as a normal power-up, and the device does not contain any information about
its state from the time before it was powered down.
VDDIO
LPO
BT_UART_RTS_N
CLK_REQ
BT_GPIO_1
(BT_HOST_WAKE)
BT_REG_ON
BT_UART_CTS_N
Host I/Os ĐŽŶĮŐƵƌĞĚ
Host I/Os
ƵŶconĮŐƵƌĞĚ
BTH IOs ĐŽŶĮŐƵƌĞĚ
BTH IOs
ƵncoŶĮŐƵƌĞĚ
T2
TƐĞƩůĞ
TƐĞƩůĞ
T1
EŽƚĞƐ
T1is ƚŚĞ ƟŵĞ foƌƚŚĞ BTH ĚĞǀŝĐĞ to ƐĞƩůĞ its IOs aŌĞƌ a ƌĞƐĞƚ ĂŶĚƌĞĨ ĐůŬ ƐĞƩůŝŶŐ ƟŵĞĞůapsĞĚ.
T2is ƚŚĞ ƟŵĞ foƌƚŚĞ BT ĚĞǀŝĐĞ to ĐŽŵƉůĞtĞŝŶŝƟĂůŝnjĂƟon ĂŶĚ ĚƌŝǀĞ BT_UART_RTS_N ůŽǁ
TƐĞƩůĞ is thĞƟŵĞ foƌƚŚĞ ƌĞf cůŬ siŐŶaůĨƌŽŵ thĞhost to bĞŐƵaƌaŶƚĞĞĚ to haǀĞ ƐĞƩůĞĚ.
DƌiǀĞn
PƵůůĞĚ
/ŶĚiĐĂƚĞƐ that BTH
ĚĞǀicĞis ƌĞĂĚLJ.
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