Cypress CYW4343W User manual

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CYW4343W
Single-Chip 802.11 b/g/n MAC/Baseband/Radio
with Bluetooth 4.1
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-14797 Rev. *I Revised March 28, 2017
The Cypress CYW4343W is a highly integrated single-chip solution and offers the lowest RBOM in the industry for wearables, Internet
of Things (IoT) gateways, home automation, and a wide range of other portable devices. The chip includes a 2.4 GHz WLAN IEEE
802.11 b/g/n MAC/baseband/radio and Bluetooth 4.1 support. In addition, it integrates a power amplifier (PA) that meets the output
power requirements of most handheld systems, a low-noise amplifier (LNA) for best-in-class receiver sensitivity, and an internal
transmit/receive (iTR) RF switch, further reducing the overall solution cost and printed circuit board area.
The WLAN host interface supports SDIO v2.0 mode, providing a raw data transfer rate up to 200 Mbps when operating in 4-bit mode
at a 50 MHz bus frequency. An independent, high-speed UART is provided for the Bluetooth host interface.Using advanced design
techniques and process technology to reduce active and idle power, the CYW4343W is designed to address the needs of highly mobile
devices that require minimal power consumption and compact size. It includes a power management unit that simplifies the system
power topology and allows for operation directly from a rechargeable mobile platform battery while maximizing battery life.
The CYW4343W implements the world’s most advanced Enhanced Collaborative Coexistence algorithms and hardware mechanisms,
allowing for an extremely collaborative WLAN and Bluetooth coexistence.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Features
IEEE 802.11x Key Features
■Single-band 2.4 GHz IEEE 802.11b/g/n.
■Support for 2.4 GHz Cypress TurboQAM® data rates (256-
QAM) and 20 MHz channel bandwidth.
■Integrated iTR switch supports a single 2.4 GHz antenna
shared between WLAN and Bluetooth.
■Supports explicit IEEE 802.11n transmit beamforming
■Tx and Rx Low-density Parity Check (LDPC) support for
improved range and power efficiency.
■Supports standard SDIO v2.0 host interface.
■Supports Space-Time Block Coding (STBC) in the receiver.
■Integrated ARM Cortex-M3 processor and on-chip memory for
complete WLAN subsystem functionality, minimizing the need
to wake up the applications processor for standard WLAN
functions. This allows for further minimization of power
consumption, while maintaining the ability to field-upgrade with
future features. On-chip memory includes 512 KB SRAM and
640 KB ROM.
■OneDriver™ software architecture for easy migration from
existing embedded WLAN and Bluetooth devices as well as to
future devices.
Bluetooth Features
■Complies with Bluetooth Core Specification Version 4.1 with
provisions for supporting future specifications.
■Bluetooth Class 1 or Class 2 transmitter operation.
■Supports extended Synchronous Connections (eSCO), for
enhanced voice quality by allowing for retransmission of
dropped packets.
■Adaptive Frequency Hopping (AFH) for reducing radio
frequency interference.
■Interface support — Host Controller Interface (HCI) using a
high-speed UART interface and PCM for audio data.
■Low-power consumption improves battery life of handheld
devices.
■Supports multiple simultaneous Advanced Audio Distribution
Profiles (A2DP) for stereo sound.
■Automatic frequency detection for standard crystal and TCXO
values.
Broadcom Part Number Cypress Part Number
BCM4343W CYW4343W
BCM4343WKUBG CYW4343WKUBG

Document Number: 002-14797 Rev. *I Page 2 of 103
CYW4343W
General Features
■Supports a battery voltage range from 3.0V to 4.8V with an
internal switching regulator.
■Programmable dynamic power management.
■4 Kbit One-Time Programmable (OTP) memory for storing
board parameters.
■Can be routed on low-cost 1 x 1 PCB stack-ups.
■74-ball[4343W+43CS4343W1]74-ball 63-ball WLBGA
package (4.87 mm × 2.87 mm, 0.4 mm pitch).
■153-bump WLCSP package (115 μm bump diameter, 180 μm
bump pitch).
■Security:
❐WPA and WPA2 (Personal) support for powerful encryption
and authentication.
❐AES in WLAN hardware for faster data encryption and IEEE
802.11i compatibility.
❐Reference WLAN subsystem provides Cisco Compatible Ex-
tensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0).
❐Reference WLAN subsystem provides Wi–Fi Protected Set-
up (WPS).
■Worldwide regulatory support: Global products supported with
worldwide homologated design.
Figure 1. CYW4343W System Block Diagram
VDDIO VBAT
2.4 GHz WLAN +
Bluetooth TX/RX
WLAN
Host I/F
Bluetooth
Host I/F
WL_REG_ON
SDIO
WL_IRQ
BT_REG_ON
UART
BT_DEV_WAKE
BT_HOST_WAKE
BPF
CLK_REQ
PCM
CYW4343W

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Contents
1. Overview ............................................................ 5
1.1 Overview ............................................................. 5
1.2 Features .............................................................. 6
1.3 Standards Compliance ........................................ 7
2. Power Supplies and Power Management ....... 8
2.1 Power Supply Topology ...................................... 8
2.2 CYW4343W PMU Features ................................ 8
2.3 WLAN Power Management ............................... 11
2.4 PMU Sequencing .............................................. 11
2.5 Power-Off Shutdown ......................................... 12
2.6 Power-Up/Power-Down/Reset Circuits ............. 12
3. Frequency References ................................... 13
3.1 Crystal Interface and Clock Generation ............ 13
3.2 TCXO ................................................................ 13
3.3 External 32.768 kHz Low-Power Oscillator ....... 15
4. WLAN System Interfaces ............................... 16
4.1 SDIO v2.0 .......................................................... 16
4.1.1 SDIO Pin Descriptions ........................... 16
5. Wireless LAN MAC and PHY.......................... 17
5.1 MAC Features ................................................... 17
5.1.1 MAC Description .................................... 17
Figure 9..PSM ...................................................... 18
Figure 9..WEP ...................................................... 18
Figure 9..TXE ....................................................... 18
Figure 9..RXE ...................................................... 18
Figure 9..IFS ........................................................ 19
Figure 9..TSF ....................................................... 19
Figure 9..NAV ...................................................... 19
Figure 9..MAC-PHY Interface .............................. 19
5.2 PHY Description ................................................ 19
5.2.1 PHY Features ........................................ 20
6. WLAN Radio Subsystem ................................ 21
6.1 Receive Path ..................................................... 22
6.2 Transmit Path .................................................... 22
6.3 Calibration ......................................................... 22
7. Bluetooth Subsystem Overview .................... 23
7.1 Features ............................................................ 23
7.2 Bluetooth Radio ................................................. 24
7.2.1 Transmit ................................................. 24
7.2.2 Digital Modulator .................................... 24
7.2.3 Digital Demodulator and Bit
Synchronizer .......................................... 24
7.2.4 Power Amplifier ..................................... 24
7.2.5 Receiver ................................................ 25
7.2.6 Digital Demodulator and Bit Synchronizer 25
7.2.7 Receiver Signal Strength Indicator ........ 25
7.2.8 Local Oscillator Generation ....................25
7.2.9 Calibration ..............................................25
8. Bluetooth Baseband Core.............................. 26
8.1 Bluetooth 4.1 Features .......................................26
8.2 Link Control Layer ..............................................26
8.3 Test Mode Support .............................................27
8.4 Bluetooth Power Management Unit ...................27
8.4.1 RF Power Management ..........................27
8.4.2 Host Controller Power Management ......27
8.5 BBC Power Management ...................................29
8.5.1 Wideband Speech ..................................29
8.6 Packet Loss Concealment .................................29
8.6.1 Codec Encoding .....................................30
8.6.2 Multiple Simultaneous A2DP Audio
Streams ..................................................30
8.7 Adaptive Frequency Hopping .............................30
8.8 Advanced Bluetooth/WLAN Coexistence ...........30
8.9 Fast Connection (Interlaced Page and Inquiry
Scans) ................................................................30
9. Microprocessor and Memory Unit for Bluetooth
31
9.1 RAM, ROM, and Patch Memory .........................31
9.2 Reset ..................................................................31
10.Bluetooth Peripheral Transport Unit............. 32
10.1 PCM Interface ....................................................32
10.1.1 Slot Mapping ...........................................32
10.1.2 Frame Synchronization ...........................32
10.1.3 Data Formatting ......................................32
10.1.4 Wideband Speech Support .....................32
10.1.5 PCM Interface Timing .............................33
10.1.5.Short Frame Sync, Master Mode ...............33
Table 7..Short Frame Sync, Slave Mode ..............34
Table 8..Long Frame Sync, Master Mode .............35
Table 9..Long Frame Sync, Slave Mode ...............36
10.2 UART Interface ..................................................37
10.3 I2S Interface .......................................................38
10.3.1 I2S Timing ...............................................39
11.CPU and Global Functions ............................ 41
11.1 WLAN CPU and Memory Subsystem ................41
11.2 One-Time Programmable Memory .....................41
11.3 GPIO Interface ...................................................41
11.4 External Coexistence Interface ..........................41
11.4.1 2-Wire Coexistence ................................42
11.4.2 3-Wire and 4-Wire Coexistence
Interfaces ................................................42
11.5 JTAG Interface ..................................................43
11.6 UART Interface .................................................43

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12.WLAN Software Architecture......................... 44
12.1 Host Software Architecture ............................... 44
12.2 Device Software Architecture ............................ 44
12.3 Remote Downloader ......................................... 44
12.4 Wireless Configuration Utility ............................ 44
13.Pinout and Signal Descriptions..................... 45
13.1 Ball Map ............................................................ 45
13.2 WLBGA Ball List in Ball Number Order with X-Y
Coordinates ....................................................... 47
13.3 WLCSP Bump List in Bump Order with X-Y
Coordinates ....................................................... 49
13.4 WLBGA Ball List Ordered By Ball Name ........... 54
13.5 WLCSP Bump List Ordered By Name .............. 55
13.6 Signal Descriptions ........................................... 57
13.7 WLAN GPIO Signals and Strapping Options .... 65
13.8 Chip Debug Options .......................................... 65
13.9 I/O States .......................................................... 66
14.DC Characteristics.......................................... 68
14.1 Absolute Maximum Ratings .............................. 68
14.2 Environmental Ratings ...................................... 68
14.3 Electrostatic Discharge Specifications .............. 69
14.4 Recommended Operating Conditions and DC
Characteristics .................................................. 69
15.WLAN RF Specifications ................................ 71
15.1 2.4 GHz Band General RF Specifications ......... 71
15.2 WLAN 2.4 GHz Receiver Performance
Specifications .................................................... 72
15.3 WLAN 2.4 GHz Transmitter Performance
Specifications .................................................... 75
15.4 General Spurious Emissions Specifications ...... 77
16.Bluetooth RF Specifications.......................... 78
17.Internal Regulator Electrical Specifications. 84
17.1 Core Buck Switching Regulator .........................84
17.2 3.3V LDO (LDO3P3) ..........................................85
17.3 CLDO .................................................................86
17.4 LNLDO ...............................................................87
18.System Power Consumption ......................... 88
18.1 WLAN Current Consumption ..............................88
18.1.1 2.4 GHz Mode ........................................88
18.2 Bluetooth Current Consumption .........................89
19.Interface Timing and AC Characteristics ..... 90
19.1 SDIO Default Mode Timing ................................90
19.2 SDIO High-Speed Mode Timing .........................91
19.3 JTAG Timing ......................................................92
20.Power-Up Sequence and Timing ................... 93
20.1 Sequencing of Reset and Regulator Control
Signals ...............................................................93
20.1.1 Description of Control Signals ................93
20.1.2 Control Signal Timing Diagrams .............94
21.Package Information ...................................... 96
21.1 Package Thermal Characteristics ......................96
21.1.1 Junction Temperature Estimation and
PSI Versus Thetajc ..................................96
22.Mechanical Information.................................. 97
23.Ordering Information.................................... 101
24.Additional Information ................................. 101
24.1 Acronyms and Abbreviations ...........................101
24.2 IoT Resources ..................................................101
Document History Page............................................... 102
Sales, Solutions, and Legal Information .................... 103

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1. Overview
1.1 Overview
The Cypress CYW4343W provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE 802.11 b/g/n. It provides a small form-factor
solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. The CYW4343W is
designed to address the needs of highly mobile devices that require minimal power consumption and reliable operation.
Figure 2 shows the interconnection of all the major physical blocks in the CYW4343W and their associated external interfaces, which are described in greater detail in
subsequent sections.
Figure 2. CYW4343W Block Diagram
Commonand
RadioDigital
SW REG
LDOx2
LPO
XTALOSC.
BPF
WLAN
SDIO
JTAG*
ARM
CM3
Backplane
BT‐WLAN
ECI
WDT
OTP
GPIO
UART
JTA G *
RAM
ROM
PM U
Control
MAC
LNPPHY
Radio
BTClockControl
Sleep‐
tim e
Keeping
Clock
Management PM U PM U
Ctrl
POR
IF
PLL
BTPHY
Modem
Digital
Demod.
&Bit
Sync
Digital
Mod.
BPL
Buffer
APU
BTClock/
Hopper
LCU
RX/TX
Buffer
WiMaxCoex
PTU
UART
Debug
UART
I2S/PCM
GPIO
Wake/
SleepCtrl
I/OPortControl
AHBBusMatrix
Cortex
M3
ETM
JTAG*
SDP
RAM
ROM
Patch
InterCtrl
DMA
BusArb
ARMIP
WDTim er
SW Tim er
GPIO
Ctrl
APB
RF
PA
Digital
I/O
SDIO
Debug
IEEE802.11a/b/g/n
GPIO
UART
2.4GHz
2.4GHz
PA
SharedLN A
Power
Supply
SleepCLK
XTAL
WiMax
Coex.
BlueRF
Inte rfa ce
LPO XO
Bu ffer
XTAL
VBAT
VREGs
BT_REG_ON
AHBtoAPB
Bridge
AHB
SupportedoverSDIOorBTPCM
JT AG supportedoverSDIOorBTPCM
*ViaGPIOc o n fig u ra tio n ,JT A G issupportedoverSDIOorBTPCM
POR WL_REG_ON

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1.2 Features
The CYW4343W supports the following WLAN and Bluetooth features:
■IEEE 802.11b/g/n single-band radio with an internal power amplifier, LNA, and T/R switch
■Bluetooth v4.1 with integrated Class 1 PA
■Concurrent Bluetooth, and WLAN operation
■On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality
■Simultaneous BT/WLAN reception with a single antenna
■WLAN host interface options:
❐SDIO v2.0, including default and high-speed timing.
■BT UART (up to 4 Mbps) host digital interface that can be used concurrently with the above WLAN host interfaces.
■ECI—enhanced coexistence support, which coordinates BT SCO transmissions around WLAN receptions.
■I2S/PCM for BT audio
■HCI high-speed UART (H4 and H5) transport support
■Wideband speech support (16 bits, 16 kHz sampling PCM, through I2S and PCM interfaces)
■Bluetooth SmartAudio®technology improves voice and music quality to headsets.
■Bluetooth low power inquiry and page scan
■Bluetooth Low Energy (BLE) support
■Bluetooth Packet Loss Concealment (PLC)

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1.3 Standards Compliance
The CYW4343W supports the following standards:
■Bluetooth 2.1 + EDR
■Bluetooth 3.0
■Bluetooth 4.1 (Bluetooth Low Energy)
■IEEE 802.11n—Handheld Device Class (Section 11)
■IEEE 802.11b
■IEEE 802.11g
■IEEE 802.11d
■IEEE 802.11h
■IEEE 802.11i
The CYW4343W will support the following future drafts/standards:
■IEEE 802.11r — Fast Roaming (between APs)
■IEEE 802.11k — Resource Management
■IEEE 802.11w — Secure Management Frames
■IEEE 802.11 Extensions:
■IEEE 802.11e QoS Enhancements (as per the WMM®specification is already supported)
■IEEE 802.11i MAC Enhancements
■IEEE 802.11r Fast Roaming Support
■IEEE 802.11k Radio Resource Measurement
The CYW4343W supports the following security features and proprietary protocols:
■Security:
❐WEP
❐WPA™Personal
❐WPA2™Personal
❐WMM
❐WMM-PS (U-APSD)
❐WMM-SA
❐WAPI
❐AES (Hardware Accelerator)
❐TKIP (host-computed)
❐CKIP (SW Support)
■Proprietary Protocols:
❐CCXv2
❐CCXv3
❐CCXv4
❐CCXv5
■IEEE 802.15.2 Coexistence Compliance — on silicon solution compliant with IEEE 3-wire requirements.

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2. Power Supplies and Power Management
2.1 Power Supply Topology
One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW4343W. All regulators
are programmable via the PMU. These blocks simplify power supply design for Bluetooth and WLAN functions in embedded designs.
A single VBAT (3.0V to 4.8V DC maximum) and VDDIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided
by the regulators in the CYW4343W.
Two control signals, BT_REG_ON and WL_REG_ON, are used to power up the regulators and take the respective circuit blocks out
of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down
only when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO can be turned on and off based on the
dynamic demands of the digital baseband.
The CYW4343W allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO
regulators. When in this state, LPLDO1 provides the CYW4343W with all required voltage, further reducing leakage currents.
Note: VBAT should be connected to the LDO_VDDBAT5V and SR_VDDBAT5V pins of the device.
Note: VDDIO should be connected to the SYS_VDDIO and WCC_VDDIO pins of the device.
2.2 CYW4343W PMU Features
The PMU supports the following:
■VBAT to 1.35Vout (170 mA nominal, 370 mA maximum) Core-Buck (CBUCK) switching regulator
■VBAT to 3.3Vout (250 mA nominal, 450 mA maximum 800 mA peak maximum) LDO3P3
■1.35V to 1.2Vout (100 mA nominal, 150 mA maximum) LNLDO
■1.35V to 1.2Vout (80 mA nominal, 200 mA maximum) CLDO with bypass mode for deep sleep
■Additional internal LDOs (not externally accessible)
■PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode.
■PMU input supplies automatic sensing and fast switching to support A4WP operations.
Figure 3 and Figure 4 show the typical power topology of the CYW4343W.

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Figure 3. Typical Power Topology (1 of 2)
MiniPMU
VSEL1
WLRF—LOGEN
WLRF—RXLNA
WLRF—ADCREF
WLRF—TX
WLRF—AFEandTIA
WLRF—XTAL
InternalVCOLDO
80mA(N M OS)
InternalRXLDO
10mA(N M OS)
InternalADCLDO
10mA(N M OS)
InternalTXLDO
80mA(PM O S)
InternalAFELDO
80mA(N M OS)
LNLDO
(100mA)
1.2V
1.2V
1.2V
1.2V
CLLDO
Peak:200mA
Avg:80mA
(Bypassindeep‐
sleep)
CoreBuck
Regulator
Peak:370mA
Avg:170mA
LPLDO1
(5mA)
2.2uH
0603
1.35V
1.1V
1.2V
1.2V
SR_VDDBAT5V
VDD1P35
LDO_VDD_1P5
4.7uF
0402
SR_PVSS
SR_VLX
WPTLDO
(40mA) 1.3V
SYS_VDDIO (40mA)
o_wpt_resetb
o_wl_resetbWL_REG_ON
WPT_1P8 (40mA)
o_bt_resetbBT_REG_ON
WCC_VDDIO
WCC_VDDIO (40mA)
PMU_VSS
GND
SR_VBAT5V
VBAT
Int_SR_VBAT
1.2V
VBAT:
Operational: 3.0—4.8V
Performance: 3.0—4.8V
AbsoluteMaximum: 5.5V
VDDIO
Operational: 1.8—3.3V
SYS_VDDIO
WPT_1P8
600@
100MHz
2.2uF
0402
0.1uF
0201
WLRF_XTAL_
VDD1P2
WLRF—TXMixerandPA
(notallversions)
WLRF—RFPLLPFDandMMD
10mAaverage,
>10mAatstart‐up
VOUT_LNLDO
2.2uF
0402
VDDC1
VDDC2
(AVS)
VOUT_CLDO
1.3V,1.2V,
or0.95V
WLAN/BT/CLB/Top,AlwaysOn
WLOTP
WLDigitalandPHY
WLVDDM(SROM s&AOS)
BTVDDM
BTDigital
MiniPMUisplaced
inWLradio
VBAT
Supplyball Supplybump/pad
Groundball Groundbump/pad
Externaltochip
Powerswitch
Nopowerswitch
Nodedicatedpowerswitch,butinternalpower‐
downmodesandblock‐specificpowerswitches
BT/WLANreset
balls
(320mA)
SW1
CYW4343W

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Figure 4. Typical Power Topology (2 of 2)
1.8V,2.5V,and3.3V
1uF
0201
4.7uF
0402
LDO3P3with
Back‐Power
Protection
(Peak450‐800mA
200mAAverage)
VOUT_3P3
3.3V
LDO_
VDDBAT5V
WPT_3P3
VBAT WLRF_PA_VDD
SW2
Peak:92mA
Average:75mA
Resistance:1ohm
BT_PAVDD
2.5VCap‐less
LNLDO
(10mA)
WLRF—PA(2.4GHz)
WLOTP3.3V
WLRF—ADC,AFE,LOGEN,
LNA,NMOSMini‐PMULDOs
BTClass1PA
Peak:70mA
Average:15mA
6.4mA
480to800mA
Supplyball
Externaltochip
Powerswitch
Nopowerswitch
Nodedicatedpowerswitch,butinternalpower‐
downmodesandblock‐specificpowerswitches
PlacedinsideWLRadio
1uF
0201
22
ohm
WLBBPLL/DFLL
6.4mA
CYW4343W

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2.3 WLAN Power Management
The CYW4343W has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the
chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current
and supply voltages. Additionally, the CYW4343W integrated RAM is a high volatile memory with dynamic clock control. The dominant
supply current consumed by the RAM is leakage current only. Additionally, the CYW4343W includes an advanced WLAN power
management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW4343W into various
power management states appropriate to the operating environment and the activities that are being performed. The power
management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required
resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power-up
sequences are fully programmable. Configurable, free-running counters (running at the 32.768 kHz LPO clock) in the PMU sequencer
are used to turn on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for
the current mode. Slower clock speeds are used wherever possible.
The CYW4343W WLAN power states are described as follows:
■Active mode— All WLAN blocks in the CYW4343W are powered up and fully functional with active carrier sensing and frame
transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock
speeds are dynamically adjusted by the PMU sequencer.
■Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW4343W remains
powered up in an IDLE state. All main clocks (PLL, crystal oscillator) are shut down to reduce active power to the minimum. The
32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake
up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current.
■Deep-sleep mode—Most of the chip, including analog and digital domains, and most of the regulators are powered off. Logic states
in the digital core are saved and preserved to retention memory in the always-on domain before the digital core is powered off. To
avoid lengthy hardware reinitialization, the logic states in the digital core are restored to their pre-deep-sleep settings when a wake-
up event is triggered by an external interrupt, a host resume through the SDIO bus, or by the PMU timers.
■Power-down mode—The CYW4343W is effectively powered off by shutting down all internal regulators. The chip is brought out of
this mode by external logic re-enabling the internal regulators.
2.4 PMU Sequencing
The PMU sequencer is used to minimize system power consumption. It enables and disables various system resources based on a
computation of required resources and a table that describes the relationship between resources and the time required to enable and
disable them.
Resource requests can derive from several sources: clock requests from cores, the minimum resources defined in the ResourceMin
register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of
resources required to produce the requested clocks.
Each resource is in one of the following four states:
■enabled
■disabled
■transition_on
■transition_off
The timer value is 0 when the resource is enabled or disabled and nonzero during state transition. The timer is loaded with the time_on
or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements
on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If
the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that
the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either
the immediate transition or the timer load-decrement sequence.
During each clock cycle, the PMU sequencer performs the following actions:
■Computes the required resource set based on requests and the resource dependency table.
■Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource
and inverts the ResourceState bit.
■Compares the request with the current resource status and determines which resources must be enabled or disabled.
■Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents.
■Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.

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2.5 Power-Off Shutdown
The CYW4343W provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices
in the system, remain operational. When the CYW4343W is not needed in the system, VDDIO_RF and VDDC are shut down while
VDDIO remains powered. This allows the CYW4343W to be effectively off while keeping the I/O pins powered so that they do not
draw extra current from any other devices connected to the I/O.
During a low-power shutdown state, provided VDDIO remains applied to the CYW4343W, all outputs are tristated, and most input
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths
or create loading on any digital signals in the system, and enables the CYW4343W to be fully integrated in an embedded device and
to take full advantage of the lowest power-savings modes.
When the CYW4343W is powered on from this state, it is the same as a normal power-up, and the device does not retain any
information about its state from before it was powered down.
2.6 Power-Up/Power-Down/Reset Circuits
The CYW4343W has two signals (see Ta b l e 2) that enable or disable the Bluetooth and WLAN circuits and the internal regulator
blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences,
see Section 20.: “Power-Up Sequence and Timing” .
Table 2. Power-Up/Power-Down/Reset Control Signals
Signal Description
WL_REG_ON
This signal is used by the PMU (with BT_REG_ON) to power-up the WLAN section. It is also OR-gated with the
BT_REG_ON input to control the internal CYW4343W regulators. When this pin is high, the regulators are enabled
and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and
WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 kpull-down resistor that is
enabled by default. It can be disabled through programming.
BT_REG_ON
This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal
CYW4343W regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has
an internal 200 kpull-down resistor that is enabled by default. It can be disabled through programming.

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3. Frequency References
An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency
reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. No software settings are required to
differentiate between the two. In addition, a low-power oscillator (LPO) is provided for lower power mode timing.
3.1 Crystal Interface and Clock Generation
The CYW4343W can use an external crystal to provide a frequency reference. The recommended configuration for the crystal
oscillator, including all external components, is shown in Figure 5. Consult the reference schematics for the latest configuration.
Figure 5. Recommended Oscillator Configuration
The CYW4343W uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing so that it can
operate using numerous frequency references. The frequency reference can be an external source such as a TCXO or a crystal
interfaced directly to the CYW4343W.
The default frequency reference setting is a 37.4 MHz crystal or TCXO. The signal requirements and characteristics for the crystal
interface are shown in Table 3.
Note: Although the fractional-N synthesizer can support many reference frequencies, frequencies other than the default require
support to be added in the driver, plus additional extensive system testing. Contact Broadcom for further details.
3.2 TCXO
As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the phase
noise requirements listed in Ta b le 3.
If the TCXO is dedicated to driving the CYW4343W, it should be connected to the WLRF_XTAL_XOP pin through an external capacitor
with value ranges from 200 pF to 1000 pF as shown in Figure 6.
Figure 6. Recommended Circuit to Use with an External Dedicated TCXO
12 – 27 pF
12 – 27 pF
WLRF_XTAL_XON
WLRF_XTAL_XOP
C
C
R
Note: Resistor value determined by crystal drive level.
See reference schematics for details.
TCXO
NC
200 pF – 1000 pF
WLRF_XTAL_XOP
WLRF_XTAL_XON

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Table 3. Crystal Oscillator and External Clock Requirements and Performance
Parameter Conditions/Notes Crystal External Frequency
Reference
Min. Typ. Max. Min. Typ. Max. Units
Frequency – – 37.4a
a. The frequency step size is approximately 80 Hz. The CYW4343W does not auto-detect the reference clock frequency; the frequency is
specified in the software and/or NVRAM file.
–––– MHz
Crystal load capacitance – – 12 – – – – pF
ESR – – – 60 – – – Ω
Drive level External crystal must be able to tolerate
this drive level. 200 – – – – – μW
Input Impedance (WLRF_X-
TAL_XOP)
Resistive – – – 10k 100k – Ω
Capacitive – – – – – 7 pF
WLRF_XTAL_XOP input
voltage AC-coupled analog signal – – – 400b
b. To use 256-QAM, a 800 mV minimum voltage is required.
– 1260 mVp-p
WLRF_XTAL_XOP input low
level DC-coupled digital signal – – – 0 – 0.2 V
WLRF_XTAL_XOP input high
level DC-coupled digital signal – – – 1.0 – 1.26 V
Frequency tolerance
Initial + over temperature – –20 – 20 –20 – 20 ppm
Duty cycle 37.4 MHz clock – – – 40 50 60 %
Phase Noisec, d, e
(IEEE 802.11 b/g)
c. For a clock reference other than 37.4 MHz, 20 × log10(f/37.4) dB should be added to the limits, where f = the reference clock frequency in
MHz.
d. Phase noise is assumed flat above 100 kHz.
e. The CYW4343W supports a 26 MHz reference clock sharing option. See the phase noise requirement in the table.
37.4 MHz clock at 10 kHz offset – – – – – –129 dBc/Hz
37.4 MHz clock at 100 kHz offset – – – – – –136 dBc/Hz
Phase Noisec, d, e
(IEEE 802.11n, 2.4 GHz)
37.4 MHz clock at 10 kHz offset – – – – – –134 dBc/Hz
37.4 MHz clock at 100 kHz offset – – – – – –141 dBc/Hz
Phase Noisec, d, e
(256-QAM)
37.4 MHz clock at 10 kHz offset – – – – – –140 dBc/Hz
37.4 MHz clock at 100 kHz offset – – – – – –147 dBc/Hz

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3.3 External 32.768 kHz Low-Power Oscillator
The CYW4343W uses a secondary low-frequency sleep clock for low-power mode timing. Either the internal low-precision LPO or an
external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process,
voltage, and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a
small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons.
Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in Table
4.
Note: The CYW4343W will auto-detect the LPO clock. If it senses a clock on the EXT_SLEEP_CLK pin, it will use that clock. If it
doesn't sense a clock, it will use its own internal LPO.
■To use the internal LPO: Tie EXT_SLEEP_CLK to ground. Do not leave this pin floating.
■To use an external LPO: Connect the external 32.768 kHz clock to EXT_SLEEP_CLK.
Table 4. External 32.768 kHz Sleep-Clock Specifications
Parameter LPO Clock Units
Nominal input frequency 32.768 kHz
Frequency accuracy ±200 ppm
Duty cycle 30–70 %
Input signal amplitude 200–3300 mV, p-p
Signal type Square wave or sine wave –
Input impedancea
a. When power is applied or switched off.
>100 kΩ
<5 pF
Clock jitter <10,000 ppm

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4. WLAN System Interfaces
4.1 SDIO v2.0
The CYW4343W WLAN section supports SDIO version 2.0. for both 1-bit (25 Mbps) and 4-bit modes (100 Mbps), as well as high
speed 4-bit mode (50 MHz clocks—200 Mbps). It has the ability to map the interrupt signal on a GPIO pin. This out-of-band interrupt
signal notifies the host when the WLAN device wants to turn on the SDIO interface. The ability to force control of the gated clocks
from within the WLAN chip is also provided.
SDIO mode is enabled using the strapping option pins. See Table 20 for details.
Three functions are supported:
■Function 0 standard SDIO function. The maximum block size is 32 bytes.
■Function 1 backplane function to access the internal System-on-a-Chip (SoC) address space. The maximum block size is 64 bytes.
■Function 2 WLAN function for efficient WLAN packet transfer through DMA. The maximum block size is 512 bytes.
4.1.1 SDIO Pin Descriptions
Figure 7. Signal Connections to SDIO Host (SD 4-Bit Mode)
Figure 8. Signal Connections to SDIO Host (SD 1-Bit Mode)
Table 5. SDIO Pin Descriptions
SD 4-Bit Mode SD 1-Bit Mode
DATA0 Data line 0 DATA Data line
DATA1 Data line 1 or Interrupt IRQ Interrupt
DATA2 Data line 2 NC Not used
DATA3 Data line 3 NC Not used
CLK Clock CLK Clock
CMD Command line CMD Command line
SDHost
CMD
DAT[3:0]
CLK
CYW4343W
SDHost
CMD
CLK
DATA
IRQ
CYW4343W

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5. Wireless LAN MAC and PHY
5.1 MAC Features
The CYW4343W WLAN MAC supports features specified in the IEEE 802.11 base standard, and amended by IEEE 802.11n. The
salient features are listed below:
■Transmission and reception of aggregated MPDUs (A-MPDU).
■Support for power management schemes, including WMM power-save, power-save multipoll (PSMP) and multiphase PSMP
operation.
■Support for immediate ACK and Block-ACK policies.
■Interframe space timing support, including RIFS.
■Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges.
■Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification.
■Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time (TBTT)
generation in hardware.
■Hardware off-load for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, WAPI, and support for key management.
■Support for coexistence with Bluetooth and other external radios.
■Programmable independent basic service set (IBSS) or infrastructure basic service set functionality
■Statistics counters for MIB support.
5.1.1 MAC Description
The CYW4343W WLAN MAC is designed to support high throughput operation with low-power consumption. It does so without
compromising on Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In addition, several
power-saving modes that have been implemented allow the MAC to consume very little power while maintaining network-wide timing
synchronization. The architecture diagram of the MAC is shown in Figure 9.
Figure 9. WLAN MAC Architecture
EmbeddedCPUInterface
HostRegisters,DMAEngines
TX‐FIFO
32KB
WEP
WEP,TKIP,AES
TXE
TXA‐MPDU
RXE
PMQ PSM
SharedMemory
6KB
PSM
UCODE
Memory
EXT‐IHR
IFS
Backoff,BTCX
TSF
NAV
IHR
BUS
SHM
BUS
MAC ‐PHYInterface
RX‐FIFO
10KB
RXA‐MPDU

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The following sections provide an overview of the important modules in the MAC.
PSM
The programmable state machine (PSM) is a microcoded engine that provides most of the low-level control to the hardware to
implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow-control operations, which are predom-
inant in implementations of communication protocols. The instruction set and fundamental operations are simple and general, which
allows algorithms to be optimized until very late in the design process. It also allows for changes to the algorithms to track evolving
IEEE 802.11 specifications.
The PSM fetches instructions from the microcode memory. It uses the shared memory to obtain operands for instructions, as a data
store, and to exchange data between both the host and the MAC data pipeline (via the SHM bus). The PSM also uses a scratch-pad
memory (similar to a register bank) to store frequently accessed and temporary variables.
The PSM exercises fine-grained control over the hardware engines by programming internal hardware registers (IHR). These IHRs
are collocated with the hardware functions they control and are accessed by the PSM via the IHR bus.
The PSM fetches instructions from the microcode memory using an address determined by the program counter, an instruction literal,
or a program stack. For ALU operations, the operands are obtained from shared memory, scratch-pad memory, IHRs, or instruction
literals, and the results are written into the shared memory, scratch-pad memory, or IHRs.
There are two basic branch instructions: conditional branches and ALU-based branches. To better support the many decision points
in the IEEE 802.11 algorithms, branches can depend on either readily available signals from the hardware modules (branch condition
signals are available to the PSM without polling the IHRs) or on the results of ALU operations.
WEP
The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform the encryption and decryption, as
well as the MIC computation and verification. The accelerators implement the following cipher algorithms: legacy WEP, WPA TKIP,
and WPA2 AES-CCMP.
Based on the frame type and association information, the PSM determines the appropriate cipher algorithm to be used. It supplies
the keys to the hardware engines from an on-chip key table. The WEP interfaces with the transmit engine (TXE) to encrypt and
compute the MIC on transmit frames and the receive engine (RXE) to decrypt and verify the MIC on receive frames. WAPI is also
supported.
TXE
The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit frames
in the TXFIFO. It interfaces with WEP module to encrypt frames and transfers the frames across the MAC-PHY interface at the
appropriate time determined by the channel access mechanisms.
The data received from the DMA engines are stored in transmit FIFOs. The MAC supports multiple logical queues to support traffic
streams that have different QoS priority requirements. The PSM uses the channel access information from the IFS module to schedule
a queue from which the next frame is transmitted. Once the frame is scheduled, the TXE hardware transmits the frame based on a
precise timing trigger received from the IFS module.
The TXE module also contains the hardware that allows the rapid assembly of MPDUs into an A-MPDU for transmission. The hardware
module aggregates the encrypted MPDUs by adding appropriate headers and pad delimiters as needed.
RXE
The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMA engine to drain the received frames
from the RX FIFO. It transfers bytes across the MAC-PHY interface and interfaces with the WEP module to decrypt frames. The
decrypted data is stored in the RX FIFO.
The RXE module contains programmable filters that are programmed by the PSM to accept or filter frames based on several criteria
such as receiver address, BSSID, and certain frame types.
The RXE module also contains the hardware required to detect A-MPDUs, parse the headers of the containers, and disaggregate
them into component MPDUS.

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IFS
The IFS module contains the timers required to determine interframe space timing including RIFS timing. It also contains multiple
back-off engines required to support prioritized access to the medium as specified by WMM.
The interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These timers
provide precise timing to the TXE to begin frame transmission. The TXE uses this information to send response frames or perform
transmit frame-bursting (RIFS or SIFS separated, as within a TXOP).
The back-off engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or
pause the back-off counters. When the back-off counters reach 0, the TXE gets notified so that it may commence frame transmission.
In the event of multiple back-off counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies
provided by the PSM.
The IFS module also incorporates hardware that allows the MAC to enter a low-power state when operating under the IEEE power-
saving mode. In this mode, the MAC is in a suspended state with its clock turned off. A sleep timer, whose count value is initialized
by the PSM, runs on a slow clock and determines the duration over which the MAC remains in this suspended state. Once the timer
expires, the MAC is restored to its functional state. The PSM updates the TSF timer based on the sleep duration, ensuring that the
TSF is synchronized to the network.
The IFS module also contains the PTA hardware that assists the PSM in Bluetooth coexistence functions.
TSF
The timing synchronization function (TSF) module maintains the TSF timer of the MAC. It also maintains the target beacon trans-
mission time (TBTT). The TSF timer hardware, under the control of the PSM, is capable of adopting timestamps received from beacon
and probe response frames in order to maintain synchronization with the network.
The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer, such as uplink and downlink
transmission times used in PSMP.
NAV
The network allocation vector (NAV) timer module is responsible for maintaining the NAV information conveyed through the duration
field of MAC frames. This ensures that the MAC complies with the protection mechanisms specified in the standard.
The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based on received frames.
This timing information is provided to the IFS module, which uses it as a virtual carrier-sense indication.
MAC-PHY Interface
The MAC-PHY interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition, there is a programming
interface, which can be controlled either by the host or the PSM to configure and control the PHY.
5.2 PHY Description
The CYW4343W WLAN digital PHY is designed to comply with IEEE 802.11b/g/n single stream to provide wireless LAN connectivity
supporting data rates from 1 Mbps to 96 Mbps for low-power, high-performance handheld applications.
The PHY has been designed to meet specification requirements in the presence of interference, radio nonlinearity, and impairments.
It incorporates efficient implementations of the filters, FFT, and Viterbi decoder algorithms. Efficient algorithms have been designed
to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition
and tracking, and channel estimation and tracking. The PHY receiver also contains a robust IEEE 802.11b demodulator. The PHY
carrier sense has been tuned to provide high throughput for IEEE 802.11g/IEEE 802.11b hybrid networks with Bluetooth coexistence.