DG FPGA Manual

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FPGA Setup for NVMe-IP (for Gen4)/
NVMeG3-IP/NVMeG4-IP demo Rev4.3 13-Sep-21
This document describes the FPGA and environment setup for running NVMe-IP, NVMe-IP for
Gen4, NVMeG3-IP, or NVMeG4-IP demo on FPGAdevelopment board by using the PCIe adapter
board (AB18-PCIeX16, AB17-M2FMC, AB16-PCIeXOVR, or customized AB18-PCIeX16 adapter
board) with NVMe SSD. User controls the test operation via Serial console.
1 Environment Requirement
To run the demo on FPGA development board, please prepare following environment.
1) Supported FPGA Development board:
NVMe-IP for Gen4: Alveo-U50
NVMe-IP : AC701, ZC706, VC707, KCU105, KCU116, ZCU106, or VCU118
NVMeG3-IP : KCU105, KCU116, ZCU102, ZCU106, or VCU118
NVMeG4-IP : KCU116, ZCU102, ZCU106 or VCU118
2) PC installing Xilinx programmer software (Vivado) and Serial console software such as
HyperTerminal or TeraTerm
3) The PCIe adapter board (AB18-PCIeX16, AB17-M2FMC, AB16-PCIeXOVR, or
customized AB18-PCIeX16 adapter board) provided by Design Gateway
https://dgway.com/ABseries_E.html
Note: Customized AB18-PCIeX16 adapter board is the AB18 board which needs to
modified by the user to use Alveo-U50 connecting with NVMe SSD via PCIe connector.
The details of the board modification are described in Topic 3 (Customized AB18 board).
4) Xilinx power adapter for FPGA board, except Alveo-U50
5) ATX power supply for AB18-PCIeX16 adapter board or Customized AB18 board for
Alveo-U50
6) NVMe SSD connecting with PCIe adapter board
7) USB cable for JTAG programming and Serial console
7-series board : One micro USB cable and one mini USB cable
UltraScale/UltraScale+ board : Two USB cables
Alveo board : Alveo programming cable with micro USB cable

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Figure 1-1 NVMe-IP demo environment setup on VC707 (PCIe Gen2)
Figure 1-2 NVMe-IP demo environment setup on ZC706 (PCIe Gen2)

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Figure 1-3 NVMe-IP demo environment setup on AC701 (PCIe Gen2)

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Figure 1-4 NVMe-IP/NVMeG3-IP demo environment setup on KCU105 with AB18 (PCIe Gen3)
Figure 1-5 NVMe-IP demo environment setup on KCU105 with AB17 (PCIe Gen3)

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Figure 1-6 NVMe-IP/NVMeG3-IP/NVMeG4-IP demo environment setup on KCU116
with AB18 (PCIe Gen3/Gen4)

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Figure 1-7 NVMeG3-IP/NVMeG4-IP demo environment setup on ZCU102
with AB17 (PCIe Gen3/Gen4)

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Figure 1-8 NVMe-IP/NVMeG3-IP/NVMeG4-IP demo environment setup on ZCU106
with AB18 (PCIe Gen3/Gen4)

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Figure 1-9 NVMe-IP/NVMeG3-IP/NVMeG4-IP demo environment setup on ZCU106
with AB17 (PCIe Gen3/Gen4)

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Figure 1-10 NVMe-IP/NVMeG3-IP/NVMeG4-IP demo environment setup on VCU118
with AB18 (PCIe Gen3/Gen4)

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Figure 1-11 NVMe-IP/NVMeG3-IP/NVMeG4-IP demo environment setup on VCU118
with AB17 (PCIe Gen3/Gen4)

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Figure 1-12 NVMe-IP for Gen4 demo environment setup on Alveo-U50 with
customized AB18 (PCIe Gen4)
Note: The modification details of customized AB18 for using with Alveo-U50 are described in
Topic 3 (Customized AB18 board)

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2 Demo setup
1) Power off system.
2) Check DIP switch setting for JTAG configuration on Zynq board.
•For ZC706 board, set SW11=all OFF to configure PS from JTAG and set
SW4[1:2]=[OFF ON] to connect JTAG with USB-to-JTAG interface, as shown in Figure
2-1.
Figure 2-1 SW11 setting to configure PS from JTAG on ZC706
•For ZCU106/ZCU102 board, set SW6=all ON to configure PS from JTAG, as shown in
Figure 2-2.
Figure 2-2 SW6 setting to configure PS from JTAG on ZCU106

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3) Setup and connect NVMe SSD to PCIe adapter board.
AB18-PCIeX16, AB16-PCIeXOVR, or customized AB18 (Alveo-U50 card)
i) Confirm that two mini jumpers are inserted at J5 connector on AB18.
ii) Connect ATX power supply to AB board.
iii) Connect PCIe connector on FPGA board/Alveo card to FPGA Side (A-side) and
connect NVMe PCIe SSD to device side (B-Side) onAB board, as shown in Figure 2-3
Warning: Please confirm that the SSD is inserted in the correct side of AB18
(B-side, not A-side) before power on system.
Figure 2-3 Setup AB18-PCIeX16 connection

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AB17-M2FMC
i) Connect M.2 NVMe SSD to Drive#1 M.2 connector on AB17-M2FMC.
ii) Connect AB17-M2FMC to HPC/HPC1 connector on KCU105(J22), ZCU106(J5),
ZCU102(J4), or HSPC on VCU118 (J22), as shown in Figure 2-4
Figure 2-4 Setup AB17-M2FMC connection

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4) Connect USB cables for JTAG programming and Serial console.
a) For AC701/VC707/ZC706, connect micro USB cable for JTAG and mini USB cable for
Serial console.
b) For KCU105/KCU116/ZCU106/VCU118, connect two micro USB cables for JTAG and
Serial console.
Figure 2-5 USB cable connection
c) For Alveo-U50, connect Alveo programming cable to Alveo-U50 board by using
Ribbon cable and connect micro USB cable for JTAG and Serial console as shown in
Figure 2-6.
Note: More details about Alveo programming cable are described in the user guide.
https://www.xilinx.com/support/documentation/boards_and_kits/accelerator-cards/ug
1377-alveo-programming-cable-user-guide.pdf
Figure 2-6 Alveo Programming cable

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5) Power on FPGA development board, adapter board, and ATX power supply for AB18.
Figure 2-7 Turn on power switch on adapter board

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6) After connecting USB cables to PC, additional COM port is detected. For
Ultrascale/Ultrascale+ board/Alveo card, many COM ports are detected.
a) KCU105/KCU116/VCU118: Select Standard COM port
b) ZCU106: Select the lowest number of the additional COM ports
c) Alveo-U50: Select number#2 of the additional COM ports
On Serial console, set Buad rate=115,200, Data=8-bit, Non-Parity, and Stop = 1, as shown
in Figure 2-8.
Figure 2-8 Select and set COM port

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7) When using AB17-M2FMC connection on KCU105 or VCU118 board, user must set VADJ
on FMC connector as following step.
KCU105 board
Open Serial console to connect with Enhanced COM port (Buad rate=115,200 Data=8 bit
Non-Parity Stop=1). The console shows System Controller menu, as shown in Figure 2-9.
To set VADJ of FMC to 1.8V, the following step is recommended.
Figure 2-9 Setting VADJ of FMC on KCU105
i) Input ‘4’ to select Adjust FMC Settings.
ii) Input ‘4’ to set FMC VADJ to 1.8V.
iii) Input ‘0’ to return to Main Menu.
iv) Input ‘2’ to get PMBUS Voltages.
v) Input ‘7’ to get VADJ1V8 Voltage. The output voltage of this menu must be equal to
1.8V to confirm that VADJ has been set completely.
For more details of System Controller, please check “UG917 KCU105 Board User Guide”
in section “Appendix C: System Controller”.
https://www.xilinx.com/support/documentation/boards_and_kits/kcu105/ug917-kcu105-e
val-bd.pdf

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VCU118 board
Open SCUI.exe and run following step.
Figure 2-10 Setting VADJ of FMC for VCU118
i) Select File->Change the System Controller Port.
ii) Select COM port number which is Enhanced COM Port.
iii) Click “OK” button to confirm the port.
iv) Select FMC tab -> Set VADJ tab -> Current tab. Click “Set VADJ to 1.8V” button.
v) Select Voltages tab and click “Get VADJ_1V8 Voltage” button. The output voltage
must be equal to 1.8V to confirm that VADJ has been set completely.
System controller tool (SCUI.exe) can be downloaded from Xilinx website.
https://www.xilinx.com/products/boards-and-kits/vcu118.html#documentation
Direct link for SCUI.exe on Vivado2017.4.
https://www.xilinx.com/member/forms/download/design-license.html?cid=07015756-bc8
9-402c-9308-2be69db6f96c&filename=rdf0396-vcu118-system-controller-c-2017-4.zip

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8) Download and program configuration file and firmware to FPGA board.
AC701, VC707, KCU105, KCU116, VCU118, and Alveo-U50 card
Configure FPGA by using Vivado tool, as shown in Figure 2-11.
Figure 2-11 Program FPGA by Vivado
ZC706, ZCU106, and ZCU102 board
Open Vivado TCL shell and run NVMeIPTest_xxx.bat, NVMeG3IPTest_xxx.bat, or
NVMeG4IPTest_xxx.bat as shown in Figure 2-12.
Figure 2-12 Command script to download demo file on Vivado TCL shell