Digital Electronics Corporation VT240 Series User manual

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EK-VT240- TM-001
VT240 Series
Technical Manual
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

EK-VT240- TM-001
VT240 Series
Technical Manual
Prepared by Educational Services
of
Digital Equipment Corporation
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

1st Edition, August 1984
Copyright © 1984 by Digital Equipment Corporation.
All Rights Reserved.
Printed in U.S.A.
The reproduction of this material, in part or whole, is strictly
prohibited. For copy information, contact the Educational Services
Department, Digital Equipment Corporation, Maynard, Massachusetts
'H754.
The information in this document is subject to change without
notice. Digital Equipment Corporation assumes no responsibility
for any errors that may appear in this document.
This equipment generates and uses radio frequency energy and if
not installed and used properly, that is, in strict accordance
with the manufacturer's instructions, may cause interference to
radio and television reception. It has been type tested and found
to comply with the limits for a Class B computing device in
accordance with the specifications in Subpart J of part 15 of FCC
Rules, which are designed to provide reasonable protection against
such interference in a residential installation. However, there is
no guarantee that interference will not occur in a particular
installation. If this equipment does cause interference to radio
or television reception, which can be determined by turning the
equipment off and on, the user is encouraged to try to correct the
interference by one or more of the following measures:
reorient the receiving antenna
relocate the computer with respect to the receiver
move the computer away from the receiver
plug the computer into a different outlet so that computer and
receiver are on different branch circuits.
If necessary, the user should consult the dealer or an experienced
radio/television technician for additional suggestions. The user
may find the following booklet prepared by the Federal
Communications Commission helpful:
"How to Identify and Resolve Radio-TV Interference Problems".
This booklet is available from the US Government Printing Office,
Washington, DC 20402, Stock No. 004-000-00345-4.
The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts.
momoomD
DECwriter
P/OS
UNIBUS
DEC DIGITAL
Professional
VAX
DECmate LA
Rainbow VMS
DECnet MASSBUS
RSTS
VT
DECUS PDP
RSX Work
Processor
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INTRODUCTION
CHAPTER 1
1.1
1.2
1. 2.1
1. 2.2
1. 2.3
1.3
1. 3.1
1. 3.2
1. 3.3
1.4
loS
1.6
1. 6.1
1. 6. 2
1. 6. 3
1. 6. 4
1. 6. S
1. 6.6
CHAPTER 2
2.1
2.2
2.3
2.4
2.S
2.S.1
2.S.2
2.S.3
2.S.4
2.S.S
2.S.6
2.S.6.1
2.S.6.2
2.S.7
SYSTEM INTRODUCTION
Genera 1 .......•.••..•.
Physical Description
System Box (VS240)
Keyboard (LK201)
Monitor ...•..•.•
Display Capabilities
Display Characteristics
Text Capabilities .•••.
Graphics Capabilities
Communications Environment
Major Operating States
Operating Modes •..•.••.
VT100 Mode •••.••••
VT200 Mode, Seven-Bit
VT200 Mode, Eight-Bit
VTS2 Mode •.•..
ReGIS Mode
4010/4014 Mode
Controls
Controls
CONTROLS, INDICATORS, AND CONNECTORS
General
System Box (VS240)
Monochrome Monitor (VR201)
Color Monitor (VR241)
Keyboard (LK201)
Main Keypad
Editing Keypad •.....•••••••.
Auxiliary Keypad .....••......•.•
Top-Row Function Keys
Visual Indicators
Audible Indicators
Audible Keyclick •.•••
Be 11 ••••••••••••••••
Connector Cable
iii
CONTENTS
1-1
1-1
1-1
1-3
1-3
1-3
1-4
1-4
l-S
I-S
I-S
1-6
1-6
1-6
1-6
1-7
1-7
1-7
2-1
2-1
2-2
2-4
2-S
2-7
2-8
2-8
2-9
2-9
2-11
2-11
2-11
2-12
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CHAPTER 3
3.1
3.2
3.2. 1
3.2.2
3.2. 3
3. 3
3.3.1
3.3.2
3.3. 3
3.3.4
3.3. 5
3.3.6
3.3. 7
3.4
CHAPTER 4
4.1
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.2
4.2. 3
4.2.4
4.2. 5
4.2.6
4.2. 7
4.2.8
4.2. 9
4.2.113
4.2.11
4.2.11.1
4.2.11.2
4.2.11.3
4.2.12
4.2.13
4.2.14
4.2.15
4.3
4.4
CHAPTER 5
5.1
5.2
5.2.1
5.2.1.1
5.2.1.2
5.2.1.3
SYSTEM OVERVIEW
Genera 1 ...................••
Operating States ........ .
Set-Up
Local
On-Line
System Architecture
CPU Logic ........••..••••
Video Logic
System Communication
Logic
(Opt ion) Integral Modem
Power Supply .....
Keyboard
Monitor
System Interaction ......•.
CPU LOGIC
Genera 1 .•......•..•.......
Major Circuits/Components
Central Processor Unit ....•.
T11 Internal Circuits
T11 Transactions
Mode Register
Control Gates •••••.
Address Latch ........••.
Decode
Memory Map
Memory Access
Read Only Memory (ROM)
(RAM) Ra ndom Access Memory
I/O Buffer .....•..
I/O Decode ......•.
Keyboard Interface (I/F)
8251A USART Internal Circuits •••••
8251A USART Addresses .•.......•••••.
8251A USART Timing Diagrams ..••....•.
Nonvolatile RAM (NVR)
Interrupt Control
Command Register
Clock Generator ..••••••••
Signal Descriptions
Schematic Reference Information
SYSTEM COMMUNICATION LOGIC
Genera 1 .••••..••••••.....•••..•..•••..•.•••
Major Circuits/Components •.......•••...••..
Dual Asynchronous Receiver/Transmitter
(DUART)
2681 DUART
2681
2681
DUART
DUART
Internal Circuits
Addresses ..••••
Timing Diagrams •....••••••
iv
3-1
3-1
3-1
3-2
3-2
3-3
3-4
3-4
3-5
3-5
3-5
3-5
3-6
3-6
4-1
4-2
4-3
4-4
4-6
4-12
4-12
4-15
4-15
4-18
4-18
4-19
4-22
4-23
4-26
4-27
4-29
4-313
4-31
4-33
4-34
4-35
4-35
4-35
5-1
5-2
5-2
5-4
5-6
5-6
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5.2.2
5.2.2.1
5.2.2.2
5.2. 3
5.2.4
5.2.5
5.2. 6
5.2.7
5.3
5.4
CHAPTER 6
6.1
6.2
6.2.1
6.2.1.1
6.2.1.2
6.2. 2
6.2.3
6.2.4
6.2.4.1
6.2.4.2
6.2.4.3
6.2. 5
6.2.5.1
6.2.5.2
6.2.5.3
6.2.5.4
6.2.5.5
6.2.5.6
6.2.6
6.2.7
6.2.7.1
6.2.7.2
6.2.7.3
6.2.8
6.2. 9
6.2.10
6.2.11
6.2.12
6.2.13
6.2.14
6.2.15
6.2.16
6.3
6.4
Communication/Modem (Comm/Modem) Control ...
Comm/Modem Control Circuits ....•••••...
Comm/Modem Control Addresses .••••••••••
Communication Mul tiplexer (Comm Mux) •••••.•
Printer Interface (I/F) .•••.••••.••••••••••
EIA Host Interface (I/F) ••..........•...•••
20 rnA Interface (I/F) •.••••••••••••••••••••
Integral Modem Option Connector (J5) ......•
Signal Descriptions .•..••••••••.••.••••.•.•••..
Schematic Reference Information .•..••••••.•••..
VIDEO LOGIC
5-8
5-9
5-11
5-12
5-12
5-14
5-14
5-16
5-17
5-17
General ........................................ 6-1
Major Circuits/Components •.••••••••••••••.•..•• 6-2
Character Processor (CP) ••....•..•.••.••••• 6-2
8085A-2 Microprocessor Device Internal
Ci rcui ts ............................... 6-5
8085A-2 Microprocessor Device
Transactions .......................... .
Character Processor (CP) Memory .•.........•
Video Access •••••.•.......•.••.•.•..•••....
Graphics Processor •.•..••..•••••••.•.....•••
PD7220 Graphics Display Controller
(GDC) Internal Circuits •....•..•.•••••.
PD7220 Graphics Display Controller
(GDC) Addresses ..••••••.••.•..•.•••••..
PD7220 Graphics Display Controller
(GDC) Transactions ....••.••....•..••••.
Timing and Control Circuits ..••.•.......••.
Clock Generator .......•.••••.•........•
BEN and STOP Gates .•..••.....•••..•.•..
ROM Address Counter .••.•••.•.•..•••.••.
Timing Signal Generator ...•.••••......•
Read-Modify-Write (RMW) Generator .•...•
BLANK Genera tor .•.....•...•....•••••••.
Mode Select •••••••••....•...••••••••..•....
Bit Map Addressing Circuit .•..••••••.......
Plane and Byte Select ••...........•••••
Address Select ........................ .
Row/Column Mux .....•.......•...•.•.•.••
High/Low (Hi/Lo) Byte Select ......••..•••••
Bit Map Write Enable •...••..•••••....•.••..
Pattern Select ............................ .
Logic unit ................................ .
Write Data Select •••...•••.•.•.••••••...•••
Bit Map •••..........................•••••••
Parallel-to-Serial (p/S) Converter ..•••••.•
Output Map ....•.•••••.•.•••••.•....•••••••.
Digital-to-Analog (D/A) •.••.........•.•.•.•
Signal Descriptions •.•.•••.........•.•.••••..•.
Schematic Reference Information ..•.•••••••.•...
v
6-6
6-8
6-9
6-12
6-12
6-14
6-18
6-22
6-23
6-24
6-24
6-24
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-32
6-34
6-35
6-37
6-39
6-40
6-41
6-43
6-46
6-47
6-47
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CHAPTER 7
7.1
7.2
7.3
7.3.1
7.3.1.1
7.3.1.2
7.3.2
7.3.2.1
7.3.2.2
7.3.2.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.4.1
7.4.4.2
7.4.5
7.4.6
7.4.7
7.5
7.5.1
7.5.2
7.5.2.1
7.5.2.2
7.5.2.3
7.5.3
7.5.3.1
7.5.3.2
7.5.4
7.5.4.1
7.5.4.2
7.5.4.3
7.5.5
7.5.5.1
7.5.5.2
7.5.5.3
7.5.5.4
7.5.6
7.5.6.1
7.5.6.2
7.5.6.3
7.5.6.4
7.5.6.5
7.5.7
7.5.7.1
7.6
LK2131 KEYBOARD
Genera 1 •.•.....•.•..•.•.•••••••••••••••••••••••
Physical Description ••••••••••••••.••••••••••••
Functional Description •...••••.•••..•.•••••.•••
Keyboard Operation Overview .••••.•......•••
Keyboard Scanning ...•...••••••••••.••••
Control of Audio Transducer and
Indicators ............................ .
Keyboard Firmware Functions ••..••••••••.•.•
Functions Not Changed by CPU
Instructions .......................... .
Functions Changed by CPU Instructions .•
Firmware Functions Changed by CPU
Instructions .......................... .
Detailed Keyboard Circuit Description •.••••••••
Keyboard Matrix Scanning ..••...••••••••••••
Audio Transducer Control Circuit ..•••••••••
Indicator (LED) Control Circuit ••••••..•.••
Keyboard Communication •••••••••••••••••••••
Keyboard Transmit Mode •••••••••••••••••
Keyboard Receive Mode ••••••••••••••••••
Reset Signal for 81351 Microprocessor •••••••
Hardware Keyboard Identification (ID) ••••••
Voltage Supplies •••.••..••.••••••••••••.••.
Keyboard Programming ••.••••••••••••••••••.••••.
Keyboard Layout and Key Identification .••.•
Modes ••••••••••••••••••••••••••••••••••••••
Special Considerations Regarding
Autorepea t ............................ .
Special Considerations Regarding
Down/Up Mode •.....••...••••••••.••••..•
Autorepeat Rates •••••••••••.•••••••••••
Keyboard Peripherals ..•.••••.•••.•.••••••••
Aud i 0 ••••••••••••••••••••••••••••••••••
Indicators (LEDs) ••.••...••.••..•......
Keyboard-to-System Module Protocol •...•...•
Keycode Transmission .......••.•.....••.
Special Code Transmission ......•.•.••••
Power Up Transmission ....••....•.•.••.•
System Module to Keyboard Protocol ..•.•••••
Comma nd s •••••••••••••••••••••••••••••••
Parameters ............................ .
Peripheral Commands •....••...•.•.•••••.
Mode Set Commands ..••.•••••.•.••.•..•••
Special Considerations ..•..•.••••••••••••..
Error Handling .•.•••..•.•..•.•••.•..•••
Keyboard Locked Condition ••..••....••••
Reserved Code .••••..••.•...•........•.•
Test Mode ••••••••••••••••••••••••••••••
Future Expansion ......•.....••••••.....
Default Conditions •....•..••.••.•••••••..••
Audio Volume .......................... .
Specifications
vi
7-1
7-2
7-4
7-4
7-5
7-5
7-5
7-5
7-6
7-6
7-6
7-6
7-14
7-14
7-16
7-16
7-16
7-17
7-17
7-17
7-17
7-17
7-23
7-23
7-25
7-25
7-26
7-26
7-26
7-27
7-27
7-27
7-29
7-29
7-313
7-313
7-31
7-36
7-38
7-38
7-39
7-39
7-39
7-39
7-413
7-413
7-41
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CHAPTER 8
8.1
8.2
8.3
8.3.1
8.3.2
8.4
8.4.1
8.5
8.6
8.7
8.7.1
8.7.2
8.7.3
8.7.4
8.7.5
8.7.6
8.7.7
8.7.8
8.7.9
8.7.10
CHAPTER 9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
CHAPTER
10
10.1
10.1.1
10.1.2
10.1.3
10.1.3.1
10.1.3.2
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.7
10.2.8
10.2.9
10.3
MONOCHROME MONITOR
Gener a 1 ••••••••.••••
Physical Description
Functional Overview
VIDEO Da ta
SYNC Da ta
Monochrome Monitor System Communication
Composite Video Signal ••••••••••••
CRT
Yoke ••••.••...•
Monitor Module
Dynamic Focus
Grid Bias
Horizontal Deflection
Linear Regulator
Vertical Deflection
Video Amplifier (Amp)
Flyback Transformer
Jl
J2
Pi ...... .
POWER SUPPLY
Genera 1 ••••••••••••••.•••••••••
Major Circuits/Components •...•••
AC Input and Fan Components •••••
Power Supply 1 (PSI)
DC Power Input Connector (Jl)
+5 V Input Circuit
+12 V Input Circuit
-12 V Input Circuit
DC Power Okay Circuit
INTEGRAL MODEM OPTION
General ...................... .
Compatibility and Features
Functional Description
Physical Description
Power Requirements
Temperature and Humidity •••..
Major Circuits ••..•••......
Talk/Data Relay Circuit
Switch Hook Detector Circuit •.•••
Ring Detector Circuit
Hook Relay Circuit
Line Interface Circuit ..•••••••
Dial Tone Detect Circuit
Audio Coupler Circuit
Master Clock Circuit
Modern Control LSI Circuit ••••.
Terminal Interface Signal Description
vii
8-1
8-2
8-4
8-5
8-5
8-5
8-7
8-10
8-11
8-11
8-12
8-12
8-13
8-13
8-14
8-14
8-15
8-16
8-16
8-16
9-1
9-2
9-3
9-4
9-14
9-14
9-15
9-16
9-16
10-1
10-2
10-2
10-3
10-4
10-4
10-4
10-4
10-6
10-6
10-6
10-6
10-7
10-7
10-10
10-10
10-11
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10.3.1
10.3.2
10.3.2.1
10.3.2.2
10.3.2.3
10.3.2.4
10.3.2.5
10.3.2.6
10.3.2.7
10.3.2.8
10.3.2.9
10.3.2.10
10.3.2.11
10.3.2.12
10.3.2.13
10.3.2.14
10.3.2.15
10.3.2.16
10.3.2.17
10.3.2.18
10.3.2.19
10.3.2.20
Signal States •.••••••.•....•.•••••••••••••. 10-12
Interface Signals •.•...•••••••••••••.•••... 10-12
Transmitted Data (TO) ••••.••••••••••••• 10-12
Received Data (RD) ••••••••..•..•.•.•••• 10-14
Clear to Send (CTS) •••••••••••.•...••.• 10-14
Data Set Ready (DSR) •.•••••••.....•..•• 10-14
Signal and Power Ground ••••••••••••...• 10-14
Carrier Detect (CD) •••••••••••••••••••• 10-14
Speed Indication (CI) •••••••••••....•.. 10-14
Data Terminal Ready (DTR) •••.•••••••••• 10-14
Data Rate (Speed) Select (CH) •.•....... 10-15
Dial Tone Detect (DTD) •.•••...•••••.••• 10-15
Line Switch (Talk/Data) •••••..••...•••• 10-15
Data Available (DA) ••.•.•••••••••••.••• 10-15
Off Hook Drive (OH-D) •••.••••••••••••.. 10-15
9- or 10-Bit Character (9/10 SEL) •..•.• 10-15
Coupler Cut Through (CCT) •.•.•.•....... 10-15
Switch Hook (SW) ••••.....••••••••••••.. 10-15
Off Hook Modem (OH-M) .•••...•••••••••.. 10-15
Analog Loop Test (ANL) ••....•.•••••••.• 10-16
Remote Data Loopback Test (RDL) ..••••.. 10-16
Test Mode Indicate (Test IND) •••..••••• 10-16
APPENDIX A SPECIFICATIONS
APPENDIX B VT240/VT102 DIFFERENCES
APPENDIX C VT240/VT125 DIFFERENCES
APPENDIX D REGISTER BIT VALUES
APPENDIX E VIDEO LOGIC WRITE MODE PROGRAMMING OVERVIEW
FIGURES
1-1
1-2
2-1
VT240 Series Video Terminals •.•••.••••.••...•••
VT240 Series Terminal Block Diagram .•••...•.•••
System Box Controls, Indicators, and
1-2
1-2
Connectors ..................................... 2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
3-1
3-2
3-3
VR201 Monitor Controls, Indicators, and
Connectors ..................................... 2-3
VR241 Monitor Controls, Indicators, and
Connectors (Front and Rear) •.••..•••••••.•.....
Keyboard (North American) ...••.••.••..••.••.•••
Main Keypad .•.••.....•••••..••••••••.......•...
Ed i ti ng Keypad ••••••••.••••••••••••••••••••••••
Auxiliary Keypad •.•...••.•••.•.••.......•.•..•.
Top-Row Function Keys and LEOs .••.•••..••.....•
Connector for BCC01 Cable ••........•..•.•••••..
VT240 Series Terminal System Block Diagram •.•..
System Interaction in Set-up ••.•.......••••..•.
System Interaction in Local (Printer Port
2-4
2-6
2-7
2-8
2-8
2-10
2-12
3-3
3-6
Inactive) ...................................... 3-7
viii
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3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
System Interaction in Local (Printer Port as
Output Port) .................................. .
System Interaction in Local (Printer Port as
Input Port) ................................... .
System Interaction in On-Line (Printer Port as
Inactive or Output Port) •..•••.••••••••••••.•••
System Interaction in On-Line (Printer Port as
Inactive or Input Port) •••••••••••.••••••••••••
System Interaction in On-Line (Printer Port as
Input Port) ................................... .
System Interaction in On-Line (Printer Port as
Output Port) .................................. .
System Interaction in On-Line (Printer Port as
I/O Port) ..................................... .
System Interaction in On-Line (Printer Port as
Inactive or Output Port) •.•••••...•••••••••••••
System Interaction in On-Line (Printer Port as
Inactive or Input Port) •••••••••••••••••.•....•
System Interaction in On-Line (Printer Port as
Input Port) ................................... .
System Interaction in On-Line (Printer Port as
Output Port) .................................. .
System Interaction in On-Line (Printer Port as
I/O Port) ..................................... .
VT240-Series Terminal System Block Diagram •...•
CPU Logic Block Diagram ••••••.••••••••..•••••••
CPU Block Diagram •..•.•••••••.•••••••.....•••••
TIl Internal Block Diagram •••••••....••••••..•.
Power-Up Sequence ••.••..•••••..•..•••••••.•.•••
TIl Timing Diagram ............................ .
TIl 16-Bit Dynamic Read Transaction Diagram •.••
TIl 16-Bit Dynamic Write Transaction Diagram ••.
TIl Refresh Transaction Diagram •.....••••••••..
TIl ASPI Transaction Diagram ••••.••••.••..••••.
Mode Reg i ster ••••••..••••••••••..••••••••.•.•..
Control Gates Block Diagram •.•••...•.••.••••••.
Address Latch Block Diagram •••.••••••.••..•••.•
Memory Map Block Diagram •••••••••••••••••.•••••
VT240-Series Terminal Address Map •.•••..•••••••
Memory Access Decode Block Diagram ••..•.•••.••.
Read Only Memory (ROM) Block Diagram .•••••...••
Random Access Memory (RAM) Block Diagram ••••••.
RAM CAS Ga t e s ••••••••••••••••••••••••••••••••••
RAM Devices Array ••••••••••••••••••••••••••••••
I/O Buffer Block Diagram •.•••.••••.•...••••...•
I/O Decode Block Diagram ••...•••••..•.••••••••.
Keyboard Interface (I/F) Block Diagram •..•..•••
8251A USART Internal Circuits Block Diagram ..•.
8251A USART Transmit Data (TxD) Timing
Diagram ....................................... .
8251A USART Receive Data (RxD) Timing Diagram •.
Nonvolatile RAM (NVR) Block Diagram ..••••...•..
Interrupt Control Block Diagram ..•••..•.•.•.•.•
ix
3-7
3-8
3-8
3-9
3-9
3-10
3-10
3-11
3-11
3-12
3-12
3-13
4-1
4-2
4-3
4-5
4-7
4-8
4-9
4-10
4-11
4-11
4-12
4-14
4-15
4-16
4-17
4-18
4-18
4-20
4-21
4-21
4-22
4-23
4-27
4-28
4-30
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4-31
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4-29
4-30
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
Command Register Block Diagram ••.••••••••••••..
Clock Generator Block Diagram •..••••••••.••••••
VT240-Series Terminal System Block Diagram •••••
System Communications Logic Block Diagram ••••••
DUART Block Diagram ••••••.••••••••••••.••••••••
2681 DUART Internal Circuits Block Diagram •.•••
2681 DUART: Transmit Data Timing Diagram •.•••••
2681 DUART: Receive Data Timing Diagram ••••••••
Communication/Modem (Comm/Modem) Control Block
Diagram ....................................... .
Comm Mux Block Diagram •••••••••••••••••••••••••
Printer Interface (I/F) Block Diagram ••••••••••
EIA Host Interface (I/F) Block Diagram •••••••••
20 mA Interface (I/F) Block Diagram ••••••••••••
Integral Modem Option Connector (J5) Pinout •••.
VT240-Series Terminal System Block Diagram •.•••
Video Logic Block Diagram ••••••••••••.•••••••••
Character Processor (CP) Block Diagram •.•••••.•
8085A-2 Microprocessor Device Internal Block
4-34
4-35
5-1
5-3
5-4
5-5
5-8
5-9
5-10
5-13
5-13
5-15
5-15
5-16
6-1
6-3
6-4
Diagram ........................................ 6-5
Character Processor (8085A-2 Microprocessor
Device) Read/Write Transactions ••••••••••••••••
Character Processor (CP) Memory Block Diagram ••
Video Access Block Diagram ••...••••••••••••••••
Graphics Processor Block Diagram .••••••••.•••••
PD7220 GDC Block Diagram •••••••••••••••••••••••
PD7220 GDC Timing Diagram: CPU/CP Write
6-7
6-8
6-10
6-13
6-13
Transacti on .................................... 6-18
PD7220 GDC Timing Diagram: CPU/CP Read
Transaction ................................... .
PD7220 GDC Timing Diagram: Display Timing .•••••
PD7220 GDC Timing Diagram: Video Sync Signals ••
PD7220 GDC Timing Diagram: 2-Plane write
6-19
6-19
6-20
Transaction •••••••••••••.•••••••••••••••••••••• 6-21
PD7220 GDC Timing Diagram: Video DMA write
Transaction ................................... .
Timing and Control Block Diagram Circuits ••••••
Clock Generator Block Diagram ••••••••••....••••
BEN and STOP Gates Block Diagram •.•••••••••••••
ROM Address Counter Block Diagram •••••••••.••••
Timing Signal Generator Block Diagram ••••••••••
Read-Modify-Write (RMW) Generator Block
Diagram ....................................... .
BLANK Generator Block Diagram ••••••••••••••••••
Mode Select Block Diagram •••••••••••••••••.•.••
Bit Map Addressing Circuit Block Diagram •••.•••
Plane and Byte Select Block Diagram ••.•••••..••
Address Select Block Diagram •••••••••••••••••••
Row/Column Mux Block Diagram •••••••••••••••••••
Hi/La Byte Select Block Diagram ••.•••••••••••••
Bit Map write Enable Block Diagram •••.•••••••••
Pattern Select Block Diagram •••••••••••••.••.••
Logic unit Block Diagram •••••••••••••••••••••••
x
6-22
6-23
6-23
6-25
6-25
6-25
6-26
6-27
6-28
6-29
6-30
6-32
6-33
6-33
6-34
6-36
6-38
.'
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6-32
6-33
6-34
6-35
6-36
7-1
7-2
7-3
7-4
7-5
7-6
7-7A
7-7B
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
10-1
10-2
10-3
10-4
10-5
write Data Select Block Diagram ••••••••••••••••
Bit Map Block Diagram ••••••••••••••••••••••••••
Parallel-to-Serial (p/S) Converter Block
Diagram ..•.............................•.......
Output Map Block Diagram •••••••••••••••••••••••
Digital-to-Analog (D/A) Block Diagram ••••••••••
VT240-Series Terminal System Block Diagram •••••
LK201 Keyboard •••••••••••••••••••••••••••••••••
Keyboard Cable Connections •••••••••••••••••••••
LK201 Keyboard Block Diagram ••••••••••.••••••••
Matrix Scanning Block Diagram ••••••••••••••••••
Example of Ghost Key Generation ••••••••••••••••
LK201-AA Keyboard Layout •••••••••••••••••••••••
LK201-AA Keyboard Layout •••••••••••••••••••••••
Beeper Control Circuit •••••••••••••••••••••••••
Indicator (LED) Control Circuit ••••••••••••••••
Keyboard Transmit and Receive Character
F 0 rrna t ........................................ .
System Module to Keyboard Protocol •••••••••.•••
Indicator (LED) Parameter ••••.••••••••••••.••••
Indicator (LED) Layout •••••••••••••••••••••••••
Audio Volume Parameter •••••••••••••••••••••••••
Set Main Array to Down/Up Example ••••••••••••.•
Set Main Array to Autorepeat Example •••••••••••
Change Rates in Buffer 3 Example •••••••••••••••
VT240-Series Terminal System Block Diagram •••••
Monochrome Monitor Exterior View ••••.•.•••.•••.
Monochrome Monitor Block Diagram •••••••••..••••
Monochrome Monitor System Communications
Diagram ...•........••.......•..................
Composite Video Signal Representation ••••••••••
Composite Video Sync Timing Diagram ••••••••••••
Monitor Module Block Diagram •••••••••••••••••••
Moni tor Modul e Pl Pi nout •••••••••••••••••••••••
VT240-Series Terminal System Block Diagram •••••
Power Supply Block Diagram •••••••••••••••••••••
AC Input and Fan Components Block Diagram ••••••
Physical Location of Power Supply Components •••
Power Supply 1 (PS1) Block Diagram •••••••••••••
Input Regulation Circuitry ••.••••••••••••••••••
DC Output Circuits •••••••••••••••••••••••••••••
+5.1 V Crowbar Circuit ••••.••••••••••••••••••••
PSl Component Layout •••••••••••••••••••••••••••
Logic Board DC Power Input Connector •••••••••••
+5 V Input Circuit •••••••••••••••••••••••••••••
+12 V Input Circuit ••••••••••••••••••••••••••••
-12 V Input Circuit ••••••••••••••••••••••••••••
DC Power OK Circuit ••••••••••••••••••••••••••••
VT240-Series Terminal Block Diagram ••••••••••••
Physical Description •••••••••••••••••••••••••••
Block Diagram ....................••............
Talk/Data Relay •.••...•.•••.••••••••••••••••.••
Audio Coupler •••••••••••••••.••••••••••••••••••
xi
6-39
6-40
6-42
6-44
6-46
7-1
7-2
7-3
7-4
7-7
7-8
7-12
7-13
7-15
7-15
7-16
7-30
7-34
7-34
7-34
7-37
7-37
7-37
8-1
8-3
8-4
8-6
8-7
8-9
8-12
8-16
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-7
9-8
9-14
9-15
9-15
9-16
9-16
10-1
10-3
10-5
10-5
10-7
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10-6
10-7
10-8
10-9
10-10
10-11
D-l
D-2
D-3
D-4
D-5
D-6
D-7
D-8
D-9
D-10
D-ll
D-12
D-13
D-14
D-15
D-16
D-17
D-18
D-19
D-20
D-21
D-22
D-23
E-l
E-2
E-3
E-4
E-5
E-6
Originate Mode ................................ .
Answer Mode ••••••••••••••••••••••••••••••••••••
Te s t Mode ••••••••••••••••••••••••••••••••••••••
Modem Clock •..•.•••.•.•.••••••••••••••••••.••••
Modem Control LS I ............•....•...•...••••.
Stack Connector ....•.........•••••••••••••••••.
8251A USART: Command Register (Mode Instruction
Format, Asynchronous Mode) .••.••••••••••••••••.
8251A USART: Command Register (Command Data
Format) ••.....•••••••••..•.•••.••••••••••••••••
8251A USART: Status Register •••••••••••••••••••
2681 DUART: Mode Register 1 (MRl)
(Channel A and B) •••.•••••••.••••••••••••••••••
2681 DUART: Mode Register 2 (MR2)
(Channel A and B) •.••••••••••••••.•••••••••..••
2681 DUART: Status Register (SR)
(Channel A and B) •.••••••••••••••••••••••••••••
2681 DUART: Data Clock Selection Register
(DCSR) (Channel A and B) ....•••...••••••.••.••.
2681 DUART: Command Register (CR)
(Channel A and B) ..••••••••••••••••••••••••••••
2681 DUART: Receive/Transmit Data Registers
(RDR/TDR) (Channel A and B) ••••••••••••••••••••
2681 DUART: Input Change Register (ICR) ..•••••.
2681 DUART: Input Port Register (IPR) •••.•••..•
2681 DUART: Counter Timer/Upper (CTUR) and
Lower (CTLR) Registers ••.•••••••.•.•...........
2681 DUART: Auxiliary Control Register (ACR) ••.
2681 DUART: Interrupt Status Register (ISR) ••••
2681 DUART: Interrupt Mask Register (IMR) .••••.
2681 DUART: Output Port Configuration Register
(OPCR) •••••••••••••••••••••••••••••••••••••••••
Comm/Modem Control: Comm Control write (CCWR)
and Read Registers (CCRD) ••••••••••••••••••••••
Comm/Modem Control: Modem Control write Register
(MCWR) •••••••••••••••••••••••••••••••••••••••••
Comm/Modem Control: Modem Control Read Register
(MCRD) •••••••••••••••••••••••••••••••••••••••••
PD7220 GDC Status Register •••••.•••••..•.•...•.
Video Logic Mode Select Register 0 ••••••••.•.••
Video Logic Mode Select Register 1 ••••••••.••..
Video Logic Unit Register •.•••••••••••••....•••
Mode 0 (Read Back Mode) Programming Values •••••
Mode 1 (Text Mode) Programming Values ••••.••••••
Mode 2 (Vector Mode) Programming Values ••••••..
Mode 3 (DMA Scroll Mode) Programming Values .•••
Mode 4 (Screen Erase Mode) Programming Values ••
Mode 5 (Word/Line Erase Mode) Programming
Values ..........................................
xii
10-9
10-9
10-9
10-10
10-10
10-12
D-l
D-2
D-3
.'
D-4
D-5
D-6
D-7
D-8
D-8
D-9
D-9
D-10
D-10
D-ll
D-ll
D-12
D-13
D-14
D-14
D-15
D-15
D-16
D-16
E-l
E-2
E-3
E-4
E-5
E-6
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

TABLES
4-1
4-2
4-3
4-4
4-5
4-6
4-7
5-1
5-2
5-3
5-4
5-5
6-1
6-2
6-3
6-4
6-5
6-6
6-7
7-1
7-2
7-3
7-4
7-5
7-6
8-1
8-2
8-3
8-4
9-1
9-2
9-3
10-1
DAL Signal Values During Power-Up Sequence ...••
Output Flag Decode Gates Truth Table ••.•••••••.
R/W Decode Gates Truth Table ••••••••••••••....•
I/O Addresses ................................. .
8251A USART Addresses ••••••••••••••••.•••••••••
CPU Logic Signal Descriptions ••••••••.••••••••.
CPU Logic Schematic References •.•••••••..••••••
2681 DUART Addresses ••••••••.••.••••••••••••••.
Comm/Modem Control Addresses ••••••••.••••••.•••
Comm/Modem Control Definition of Integral Modem
Op t ion Pro toe 0 1 ............................... .
System Communication Logic Signal
Descriptions .................................. .
System Communication Logic Schematic
References ••••••••••••••••••..•••••••••••••••••
Character Processor Memory Addresses ••••••••••.
Video Access Circuit I/O Addresses •••••••••.•••
PD7220 GDC Commands Summary ...•.••••••..•••••••
Video Output Map (VOM) Addressing .•••••••••••••
Intensity Definition for Output Map Outputs ••••
Video Logic Signal Description .••••.•••••••••••
Video Logic Schematic References •••••••••••••••
Keyboard Matrix ••••••••••••••••••.•••••.•••••••
Keyboard Functional Divisions •••••.••••••••••• ~
Keycode Translation Table ••••••••••••••••••••••
Peripheral Commands in Hexidecimal ••.••••••••••
Keyboard Division Default Modes ••••••••••••••••
Default Rates in Autorepeat Buffers ••••••••••••
J1 Pin-out •••••••••••••••••••••••••••••••••••••
J3 Pin-out •••••••••••••••••••••••••••••••••••••
Composite Video Values •••••••••••••••••••••••••
Composite Video Sync Component ••••••••••••••.••
Power Supply 1 (PSI) Components ••••••.•••••••••
Input Voltage Specifications •••••••••••••••••••
Output Voltage Specifications •••••.••••••..••••
Interface Signal Levels ••••••••••••••••••••••••
xiii
4-13
4-13
4-14
4-25
4-29
4-36
4-45
5-7
5-11
5-12
5-17
5-25
6-9
6-11
6-15
6-45
6-45
6-48
6-62
7-9
7-18
7-19
7-33
7-39
7-40
8-6
8-7
8-8
8-10
9-9
9-11
9-12
10-13
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INTRODUCTION
GENERAL
This manual provides information to help Field Service engineers,
and other personnel trained by Digital Equipment Corporation,
isolate VT240 Series Terminal malfunctions. This manual documents
hardware functions to the major circuit level, identifying the
major circuits within the VT240 Series terminal and providing
functional descriptions of those circuits.
Summarized operating and programming information is provided where
neccessary to understand the functionality of a hardware component
or circuit.
MANUAL ORGANIZATION
The first three chapters of this manual introduce the VT240 Series
terminal.
Chapter 1 System Introduction -- introduces the VT240 Series
terminal.
Chapter 2,
all VT240
connectors.
Controls, Indicators, and Connectors -- describes
Series terminal controls, indicators, and
Chapter 3, System Overview provides an overview of the
VT240 Series terminal system interactions.
Chapters 4 through 10 identify the major logics that comprise the
VT240 Series terminal, and identify and describe the major
circuits within those logics.
Chapter 4, CPU Logic -- describes the logic responsible for
overall control over VT240 Series terminal operation.
Chapter 5, System Communication Logic describes the logic
responsible for communication with host and auxiliary devices.
Chapter 6, Video Logic -- describes the logic responsible for
developing composite video output to a monitor device.
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Chapter 7, LK201 Keyboard -- describes the module responsible
for operator input.
Chapter 8, Monochrome Monitor describes the module
responsible for visual output to the operator.
Chapter 9, Power Supply describes the system box power
supply responsible for converting ac input to dc potentials
needed to operate the terminal.
Chapter 10, Integral Modem -- describes the option responsible
for modem communication with a remote host (when installed).
This manual does not provide a technical description of the VR241
color monitor (used with the VT241 terminal). This monitor is
described in separate Digital Equipment Corporation publications
(refer to Related Documentation) .
The final part of this
provide specifications,
programming reference data.
manual is made up of Appendices which
differences between terminals, and
Appendix A, Specifications -- provides VT240 Series terminal
specifications.
Appendix B, VT240/VT102 Differences
differences between the VT240 Series
terminal.
Appendix C, VT240/VT125 Differences
differences between the VT240 Series
terminal.
descrbes the
terminal and VT100
describes the
terminal and VT125
Appendix D, Register Bit Values -- provides a summary of bit
values for register devices.
Appendix E, Video Logic Write Mode Programming Overview --
provides a summary of the video logic write modes.
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RELATED DOCUMENTATION
The following related documents supplement the information in this
manual.
VT240 Series Terminal Documentation
VT240 Series Pocket Service Guide
VT240 Series Programmer's Reference Manual
VT240 Series Programmer's Pocket Guide
VT240 Series Owner's Manual
VT240 Series Installation Guide
VT240 Series Integral Modem Installation Guide
VT240 Series Video Terminal IPB
VR241-A Series Documentation
VT241-A Series Installation/Owner's Guide
VT241-A Series Installation Guide
VT241-A Series Mini Maintenance Manual
VT241-A Series Pocket Service Guide
Maintenance Print Sets
VT240 (VS240, VR20l, LK201)
VS240 (System Box)
VR201 (Monochrome Monitor)
LK201 (Keyboard Module)
VR241 (Color Monitor)
xvii
EK-VT240-PS
EK-VT240-RM
EK-VT240-HR
EK-VT240-UG
EK-VT240-IN
EK-VT24X-IN
EK-VT240-IP
EK-VR241-IN
EK-TILSW-IN
EK-VR241E-PS
EK-VR241-PS
MP-0l807
MP-01597
MP-01410
MP-01395
MP-01893
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