Diodes PI7C9X2G304SL User manual

Document Number DS39933 Rev 2-2
PI7C9X2G304SL
PCI EXPRESS GEN 2 PACKET SWITCH
3-Port, 4-Lane, SlimPacket PCIe 2.0 Packet Switch
DATASHEET
REVISION 2-2
September 2017
1545 Barber Lane Milpitas, CA 95035
Telephone: [phone]
FAX: [phone]
Internet: http://www.di o de s .c om

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IM PORTANT NOTICE
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PA RTICULA R PURPOSE ( A ND THEIR EQUIV A LENTS UNDER THE LA WS OF A NY JURISDICTION) .
Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other
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LIFE SUPPORT
Diodes Incorporated products are specifically not authorized f or use as critical components in life support devices or systems w ithout
the express w ritten approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems w hich:
1. are intended to implant into the body, or
2. support or sustain life and w hose failure to perform w hen properly used in accordance w ith instructions for use provided
in the labeling can be reasonably expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system w hose failure to perform can be reasonably expected to
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Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or
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Incorporated products in such safety-critical, life support devices or systems.
Copyright © 2016, Diodes Incorporated
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REVISION HISTORY
Date
Revision Number
Description
06/09/10
0.1
Preliminary Datasheet
10/21/10
0.2
Added Section 6 EEPROM Interface And System Management Bus
Added Section 7 Register Description
07/12/11
0.3
Added Industrial Temperature Support (Section 1 Features, Section 11.1 Absolute
M aximum Ratings, Section 13 Ordering Information)
11/23/11
0.4
Up dated Section 1 Features (integrated reference clock)
Updated Section 3.1 PCI Express Interface Signals (Added REFCLKI_P, REFCLKI_N,
REFCLKO_P[2:0], REFCLKO_N[2:0], and IREF)
07/25/12
1.0
Up dated Section 1 Features (OBFF and LTR support)
Updated Section 3 Pin Description (RXPOLINV_DIS, P RSNT [3:1], TEST4,TEST5, and
CVDDR)
Up dated Section 6 EEPROM Interface And Sy stem M anagement Bus
Up dated Section 7 Register Description
01/02/13
1.1
Updated Section 3 Pin Description (PWR_SAV, TCK, and TRST_L)
Added Section 11.4 AC Switching Characteristics of Clock Buffer
Up dated Table 8-1 Clock Requirement
Updated Table 3.5 Power Pins
Updated Table 4.1 Pin List of 129-Pin LQFP
07/15/14
1.2
Updated Section 1 (512-by te maximum p ayload size support, No-blocking cap ability )
Up dated Section 3.2 Port Configuration Signals
Up dated Section 3.3 M iscellaneous Signals
Updated Section 4.1 Pin List of 129-Pin LQFP
Updated Section 5.1 Physical Layer Circuit
Updated Section 5.1.7 Drive De-Emphasis
Updated Section 7.2.75 Device Capabilities Register (M ax_Payload_Size Supported)
Updated Section 13 Ordering Information
Up dated Table 11-2 DC Electrical Characteristics
11/17/14
1.3
Updated Section 7.2 Transparent M ode Configuration Regis t ers
Up dated Section 8 Clock Scheme
07/16/15
1.4
Up dated Section 3.1 PCI Express Interface Signals
Up dated Section 3.2 Port Configuration Signals
Updated Section 5.1 Physical Layer Circuit
Updated Section 6.1 EEPROM Interface
Up dated Section 7.2 Transparent M ode Configuration Registers
Up dated Section 8 Clock Scheme
Up dated Table 9-1 Instruction Register Codes
Up dated Table 9-2 JTAG Device ID Register
Up dated Table 9-3 JTAG Boundary Scan Register Definition
Up dated Table 11-2 DC Electrical Characteristics
09/07/15
1.5
Up dated Table 11-1 Absolute M aximum Ratings
12/23/15
1.6
Up dated Section 3.1 PIN Description
Up dated the Table 11-1 Absolute M aximum Ratings
Up dated the Table 11-2 DC Electrical Characteristics
03/04/16
1.7
Added Section 11
Power Sequence
Updated Section 4.1 PIN LIST of 129-PIN LQFP
09/05/17
2-2
Up dated Section 1 Features
Updated Section 3.2 Port Configuration Signals
Updated Section 5.1 Physical Layer Circuit
Updated Section 6.1.4 M appingEEPROM Contents to Configuration Registers
Updated Section 7.2 Transparent Mode Configuration Registers
Updated Section 12.1 Absolute M aximum Ratings
Up dated Table 12-2 DC Electrical Characteristics
Added Section 12.4 Operating Ambient Temperature
Added Section 12.5 Power Consumption
Revision numbering system changed to whole number

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TABLE OF CONTENTS
1FEA T U R ES ....................................................................................................................................................................................... 10
2GENERAL DESCRIPTION......................................................................................................................................................... 11
3PIN DESCRIPTION ....................................................................................................................................................................... 13
3.1 PCI EX P R ES S INTERFACE SIGNA LS ....................................................................................................................13
3.2 PORT CONFIGURATION SIGNA LS ........................................................................................................................14
3.3 MISCELLANEOUS SIGNA LS....................................................................................................................................14
3.4 JTA G BOUNDARY SCA N SIGNA LS .......................................................................................................................15
3.5 POW ER PINS ..................................................................................................................................................................16
4PIN ASSIGNMENTS ...................................................................................................................................................................... 17
4.1 PIN LIST OF 129-PIN LQFP .........................................................................................................................................17
5FUNCTIONAL DESCRIPTION................................................................................................................................................. 18
5.1 PHYS ICA L LA YER CIRCUIT ....................................................................................................................................18
5.1.1 RECEIVER DETECTION .................................................................................................................................18
5.1.2 RECEIVER SIGNAL DETECTION .................................................................................................................19
5.1.3 RECEIVER EQUALIZATION ..........................................................................................................................19
5.1.4 TRANSMITTER S WING ....................................................................................................................................19
5.1.5 DRIVE AMPLITUDE AND DE-EMPHASIS SETTINGS ............................................................................19
5.1.6 DRIVE AMPLITUDE.........................................................................................................................................20
5.1.7 DRIVE DE-EMPHASIS .....................................................................................................................................21
5.1.8 TRANSMITTER ELECTRICAL IDLE LATENCY .........................................................................................21
5.2 DATA LI N K LA YER (DLL) ........................................................................................................................................21
5.3 TRANSACTION LA YER RECEIVE BLOCK (TLP DECAPSULATION) ........................................................22
5.4 ROUTING ........................................................................................................................................................................22
5.5 TC/ VC MAPPING ..........................................................................................................................................................22
5.6 QUEUE.............................................................................................................................................................................22
5.6.1 PH .........................................................................................................................................................................23
5.6.2 PD .........................................................................................................................................................................23
5.6.3 NPHD ...................................................................................................................................................................23
5.6.4 CPLH ....................................................................................................................................................................23
5.6.5 CPLD ....................................................................................................................................................................23
5.7 TRANSACTION ORDERING.....................................................................................................................................23
5.8 PORT ARBITRATION..................................................................................................................................................24
5.9 VC A RBIT RATIO N .......................................................................................................................................................24
5.10 F LOW CONTROL..........................................................................................................................................................24
5.11 TRANSATION LA YER TRANSMIT BLOCK (TLP ENCAPSULATION) .......................................................25
5.12 ACCE SS CONTROL SERVICE............................................................................................................................................25
6EEP RO M IN TERFACE AND SYSTEM MANAGEMENT BUS...................................................................................... 26
6.1 EEPROM INT ERFA CE .................................................................................................................................................26
6.1.1 AUTO M ODE EERPOM ACCESS ..................................................................................................................26
6.1.2 EEPROM MODE AT RESET ...........................................................................................................................26
6.1.3 EEPROM SPACE ADDRESS MAP.................................................................................................................26
6.1.4 MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS ...............................................28
6.2 SMBU S INT ERFA CE .....................................................................................................................................................36
7REGISTER DESCRIPTION........................................................................................................................................................ 37
7.1 REGISTER T YP ES .........................................................................................................................................................37
7.2 TRANSPARENT MODE CONFIGURATION REGISTERS ................................................................................37

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7.2.1 VENDOR ID REGISTER – OFFSET 00h ......................................................................................................39
7.2.2 DEVICE ID REGISTER – OFFSET 00h........................................................................................................39
7.2.3 COMMAND REGISTER – OFFSET 04h .......................................................................................................39
7.2.4 PRIMARY STATUS REGISTER – OFFSET 04h...........................................................................................40
7.2.5 REVISION ID REGISTER – OFFSET 08h ....................................................................................................41
7.2.6 CLASS CODE RE GISTE R – OFFSET 08h....................................................................................................41
7.2.7 CACHE LINE REGISTER – OFFSET 0Ch....................................................................................................41
7.2.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ........................................................................41
7.2.9 HEADER TYPE REGISTER – OFFSET 0Ch ................................................................................................41
7.2.10 PRIMARY BUS NUMBER REGISTER – OFFSET 18h...............................................................................41
7.2.11 SECONDARY BUS NUMBER REGISTER – OFFSET 18h ........................................................................41
7.2.12 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h....................................................................42
7.2.13 SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ..................................................................42
7.2.14 I/O BASE ADDRESS REGISTER – OFFSET 1Ch .......................................................................................42
7.2.15 I/O LIM IT A DDRESS RE GISTER – OFFSET 1Ch ......................................................................................42
7.2.16 SECONDARY STATUS REGISTER – OFFSET 1Ch ...................................................................................42
7.2.17 MEMORY BASE ADDRESS REGISTER – OFFSET 20h............................................................................43
7.2.18 MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h ..........................................................................43
7.2.19 PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h..........................................43
7.2.20 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h ........................................43
7.2.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h ..........44
7.2.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch ........44
7.2.23 I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h.........................................................44
7.2.24 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h........................................................44
7.2.25 CAPABILITY POINTER REGISTER – OFFSET 34h ..................................................................................44
7.2.26 INTERRUPT LINE REGISTER – OFFSET 3Ch...........................................................................................45
7.2.27 INTERRUPT PIN REGISTER – OFFSET 3Ch .............................................................................................45
7.2.28 BRIDGE CONTROL REGISTER – OFFSET 3Ch ........................................................................................45
7.2.29 POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 40h ......................................................46
7.2.30 POWER MANAGEMENT DATA REGISTER – OFFSET 44h ...................................................................46
7.2.31 PPB SUPPORT EXTENSIONS – OFFSET 44h............................................................................................47
7.2.32 DATA REGISTER – OFFSET 44h...................................................................................................................47
7.2.33 MSI CAPABILITY REGISTER – OFFSET 4Ch (Downstream Port Only)...............................................47
7.2.34 MESSAGE CONTROL REGISTER – OFFSET 4Ch (Downstream Port Only).......................................47
7.2.35 MESSAGE ADDRESS REGISTER – OFFSET 50h (Downstream Port Only) ........................................47
7.2.36 MESSAGE UPPER ADDRESS REGISTER – OFFSET 54h (Downstream Port Only) .........................48
7.2.37 MESSAGE DATA REGISTER – OFFSET 58h (Downstream Port Only) ................................................48
7.2.38 VPD CAPABILITY REGISTER – OFFSET 5Ch (Upstream Port Only)...................................................48
7.2.39 VPD DATA REGISTER – OFFSET 60h (Upstream Port Only) ................................................................48
7.2.40 VENDOR SPECIFIC CAPABILITY REGISTER – OFFSET 64h ..............................................................48
7.2.41 XPIP CSR0 – OFFSET 68h (Test Purpose Only).........................................................................................49
7.2.42 XPIP CSR1 – OFFSET 6Ch (Test Purpose Only) ........................................................................................49
7.2.43 REPLAY TIME-OUT C OUNTER – OFFSET 70h........................................................................................49
7.2.44 ACKNOWLEDGE LATENCY TIMER – OFFSET 70h................................................................................49
7.2.45 SWITCH OPERATION MODE – OFFSET 74h (Upstream Port).............................................................50
7.2.46 SWITCH OPERATION MODE – OFFSET 74h (Downstream Port)........................................................51
7.2.47 XPIP_CSR2 – OFFSET 78h.............................................................................................................................51
7.2.48 PHY PARAMETER 1 – OFFSET 78h.............................................................................................................51
7.2.49 PHY PARAMETER 2 – OFFSET 7Ch ............................................................................................................52
7.2.50 XPIP_CSR3 – OFFSET 80h.............................................................................................................................52
7.2.51 XPIP_CSR4 – OFFSET 84h.............................................................................................................................52
7.2.52 XPIP_CSR5 – OFFSET 88h.............................................................................................................................53
7.2.53 TL_CSR – OFFSET 8Ch ...................................................................................................................................53
7.2.54 PHY PARAMETER 3 – OFFSET 90h.............................................................................................................54
7.2.55 PHY PARAMETER 4 - OFFSET 94h..............................................................................................................54
7.2.56 OPERA TION M ODE –OFFSET 98h..............................................................................................................54

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7.2.57 SSID/SSVID CAPABILITY REGISTER – OFFSET B0h..............................................................................54
7.2.58 SUBSYSTEM ID REGISTER – OFFSET B4h ...............................................................................................55
7.2.59 GPIO C ONTR OL REGISTER – OFFSET B8h (Upstream Port Only).....................................................55
7.2.60 EEPROM CONTROL REGISTER – OFFSET BCh (Upstream Port Only).............................................56
7.2.61 EEPROM ADDRESS REGISTER – OFFSET BCh (Upstream Port Only)..............................................57
7.2.62 EEPROM DATA REGISTER – OFFSET BCh (Upstream Port Only)......................................................57
7.2.63 PCI EXPRESS CAPABILITY REGISTER – OFFSET C0h .........................................................................57
7.2.64 DEVICE CAPABILITIES REGISTER – OFFSET C4h ................................................................................58
7.2.65 DEVICE CONTROL REGISTER – OFFSET C8h........................................................................................58
7.2.66 DEVICE STATUS REGISTER – OFFSET C8h.............................................................................................59
7.2.67 LINK CAPABILITIES REGISTER – OFFSET CCh .....................................................................................60
7.2.68 LINK C ONTROL REGISTER – OFFSET D0h..............................................................................................61
7.2.69 LINK STATUS R EGISTER – OFFSE T D0h ..................................................................................................61
7.2.70 SLOT CAPABILITIES REGISTER (Downstream Port Only) – OFFSET D4h .......................................62
7.2.71 SLOT CONTROL REGISTER (Downstream Port Only) – OFFSET D8h................................................63
7.2.72 SLOT STATUS REGISTER (Downstream Port Only) – OF FSET D8h ....................................................64
7.2.73 DEVICE CAPABILITIES REGISTER 2 – OFFSET E4h .............................................................................64
7.2.74 DEVICE CONTROL REGISTER 2 – OFFSET E8h .....................................................................................64
7.2.75 DEVIDE STATUS REGISTER 2 – OFFSET E8h .........................................................................................65
7.2.76 LINK CAPABILITIES REGISTER 2 – OFFSET ECh..................................................................................65
7.2.77 LINK C ONTROL REGISTER 2 – OFFSET F0h ...........................................................................................65
7.2.78 LINK STATUS R EGISTER 2 – OFFSET F0h................................................................................................65
7.2.79 SLOT CAPABILITIES REGISTER 2 – OFFSET F4h ..................................................................................65
7.2.80 SLOT C ONTOR L REGISTER 2 – OFFSET F8h ..........................................................................................65
7.2.81 SLOT S TATUS REGISTER 2 – OFFSET F8h ...............................................................................................66
7.2.82 PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY REGISTER – OFFSET 100h.......66
7.2.83 UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h .......................................................66
7.2.84 UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h...........................................................67
7.2.85 UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch ..................................................67
7.2.86 CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h ............................................................68
7.2.87 CORRECTABLE ERROR MASK REGISTER – OFFSET 114 h................................................................69
7.2.88 ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h............................69
7.2.89 HEADER LOG REGISTER – OFFSET From 11Ch to 128h......................................................................70
7.2.90 PCI EXPRESS VIRTUAL CHANNEL CAPABILITY REGISTER – OFFSET 140h................................70
7.2.91 PORT VC CAPABILITY REGISTER 1 – OFFSET 144h.............................................................................70
7.2.92 PORT VC CAPABILITY REGISTER 2 – OFFSET 148h.............................................................................70
7.2.93 PORT VC C ONTROL REGISTER – OFFSET 14Ch....................................................................................71
7.2.94 PORT VC STATUS REGISTER – OFFSET 14Ch ........................................................................................71
7.2.95 VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 150h...............................................................71
7.2.96 VC RESOURCE CONTROL REGISTER (0) – OFFSET 154h...................................................................72
7.2.97 VC RESOURCE STATUS REGISTER (0) – OFFSET 158h .......................................................................72
7.2.98 VC RESOURCE CAPABILITY REGISTER (1) – OFFSET 15Ch..............................................................73
7.2.99 VC RESOURCE CONTROL REGISTER (1) – OFFSET 160h...................................................................73
7.2.100 VC RESOURCE STATUS REGISTER (1) – OFFSET 164h .......................................................................74
7.2.101 VC ARBITRATION TABLE REGISTER – OFFSET 170h...........................................................................74
7.2.102 PORT ARBITRATION TABLE REGISTER (0) and (1) – OFFSET 180h and 1C0h..............................74
7.2.103 PCI EXPRESS POWER BUDGETING CAPABILITY REGISTER – OFFSET 20Ch.............................75
7.2.104 DATA SELECT REGISTER – OFFSET 210h................................................................................................75
7.2.105 POWER BUDGETING DATA REGISTER – OFFSET 214h......................................................................75
7.2.106 POWER BUDGET CAPABILITY REGISTER – OFFSET 218h ................................................................76
7.2.107 ACS EXTENDED CAPABILITY HEADER – OFFSET 220h (Downstream Port Only)........................76
7.2.108 ACS CAPABILITY REGISTER – OFFSET 224h (Downstream Port Only).............................................76
7.2.109 EGRESS CONTROL VECTOR – OFFSET 228h (Downstream Port Only) ............................................77
7.2.110 LTR EXTENDED CAPABILITY HEADER – OFFSET 230h (Upstream Port Only).............................77
7.2.111 MAX SNOOP LATENCY REGISTER – OFFSET 234h (Upstream Port Only).......................................77
7.2.112 MAX NO-SNOOP LATENCY REGISTER – OFFSET 234h (Upstream Port Only)...............................77

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8CLOCK S C H EM E .......................................................................................................................................................................... 79
9IEEE 1149.1 COMPATIBLE JTAG CONTROLLER.......................................................................................................... 80
9.1 INST RU CT IO N REGISTER.........................................................................................................................................80
9.2 BYPASS REGISTER .....................................................................................................................................................80
9.3 DEVICE ID REGISTER ................................................................................................................................................80
9.4 BOUNDA RY S CAN REGISTER ................................................................................................................................81
9.5 JTA G BOUNDARY SCAN REGISTER ORDER.....................................................................................................81
10 POWER MANAGEMENT ........................................................................................................................................................... 83
11 POWER SEQUENCE..................................................................................................................................................................... 84
12 ELECTRICAL AND TIMING SPECIFICATIONS.............................................................................................................. 85
12.1 ABSOLUTE MAXIMUM RATINGS.........................................................................................................................85
12.2 DC SPECIFICATIONS ..................................................................................................................................................85
12.3 AC SPECIFICAT IONS ..................................................................................................................................................85
12.4 OPERATING AM BI ENT TEMPERATURE.............................................................................................................87
12.5 POW ER CONSUMPTION............................................................................................................................................87
13 PACKAGE INFORMATION....................................................................................................................................................... 88
14 ORDERING INFORMATION .................................................................................................................................................... 89

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TABLE OF FIGURES
FI GURE 5-1 DRIVER OUTPUT WAVEFORM.....................................................................................................................................20
FI GURE 6-1 SMBU S ARCHIT ECTURE IMPLEMENTATION ON PI7C9X2G304SL.......................................................................36
FI GURE 11-1 INITIAL POWER-UP SEQUENCE.................................................................................................................................84
FI GURE 13-1 PACKAGE OUTLINE DRAWING...................................................................................................................................88
LIST OF TABLES
TABLE 5-1 RECEIVER DETECTION THRESHOLD SETTINGS..........................................................................................................18
TABLE 5-2 RECEIVER SIGNAL DETECT THRESHOLD....................................................................................................................19
TABLE 5-3 RECEIVER EQUALIZATION SETTINGS..........................................................................................................................19
TABLE 5-4 TRANSMITTER SWI NG SETTINGS..................................................................................................................................19
TABLE 5-5 DRIVE AMP LIT UDE BA SE LEVEL REGISTERS.............................................................................................................20
TABLE 5-6 DRI VE AMP LIT UDE BA SE LEVEL SETTINGS...............................................................................................................20
TABLE 5-7 DRI VE DE-EM P H A SI S BA SE LEVEL REGI ST E R ...........................................................................................................21
TABLE 5-8 DRI VE DE-EM P H A SI S BA SE LEVEL SETTINGS ...........................................................................................................21
TABLE 5-9 SUMMARY OF PCI EX P RE SS ORDERING RULES.........................................................................................................23
TABLE 6-1 SMBU S AD D RE SS PIN CONFIGURATION.....................................................................................................................36
TABLE 7-1 REGI STER ARRAY LAYOUT FOR VC ARBIT RATION..................................................................................................74
TABLE 7-2 TABLE ENT RY SIZ E I N 4BIT S.......................................................................................................................................74
TABLE 8-1 AC SW IT CHI N G CHARACTERISTICS.............................................................................................................................79
TABLE 9-1 INSTRUCTION RE GI ST ER CODES...................................................................................................................................80
TABLE 9-2 JTA G DEVICE ID REGISTER.........................................................................................................................................80
TABLE 9-3 JTA G BOUNDARY SCAN REGISTER DEFINITION.......................................................................................................81
TABLE 12-1 ABSOLUTE MAXIMUM RAT I N GS................................................................................................................................85
TABLE 12-2 DC ELECTRICAL CHARACTERISTICS.........................................................................................................................85
TABLE 12-3 PCI EX P RE SS INTERFACE -DIFFERENT IAL TRANSMITTER (TX) OUT PUT (5.0 GBP S)CHARACTERIST ICS .....85
TABLE 12-4 PCI EX P RE SS INTERFACE -DIFFERENT IAL TRANSMITTER (TX) OUT PUT (2.5 GBP S)CHARACTERIST ICS .....86
TABLE 12-5 PCI EX P RE SS INTERFACE -DIFFERENT IAL RECEIVER (RX) INP UT (5.0 GBP S)CHARACT ERIST ICS ................86
TABLE 12-6 PCI EX P RE SS INTERFACE -DIFFERENT IAL RECEIVER (RX) INP UT (2.5 GBPS)CHARACT ERIST ICS ................87
TABLE 12-7 OP ERAT ING AMBIENT TEMPERATURE......................................................................................................................87
TABLE 12-8 POWER CONSUMPTION................................................................................................................................................87

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1FEAT URES
•4-lane PCI Express Ge n 2 Switch with 3 PCI Express ports
•Supports “Cut-through”(Default) as well as “Store and Forward” mode for packet s witching
•Peer-to-peer switching between any two downstream ports
•150 ns typical latency for packet routed through Switch without blocking
•Integrated reference clock for downstream ports
•Strapped pins configurable with optional EEPROM or SMBus
•SMBus interface support
•Compliant with SystemManagement (SM) Bus, Version 1.0
•Compliant with PCI Express Base Specification Revision 2.1
•Compliant with PCI Express CEM Specification Revision 2.0
•Compliant with PCI-to-PCI Bridge Architecture Specification Revision 1.2
•Compliant with Advanced Configuration PowerInterface (ACPI) Specification
•Reliability, Availability and Serviceability
-Supports Data Poisoning and End-to-End CRC
-Advanced Error Reporting and Logging
-IEEE 1149.1 JTAG interface support
•Advanced Power Saving
-Empty downstreamports are set to idle state to minimize power consumption
•Link Power Management
-Su p ports L0, L0s , L1, L2, L2/L3Ready and L3 link power states
-Active state power management for L0s and L1 states
•Device State Power Management
-Supports D0, D3Hot and D3Cold device power states
-3.3V Aux Power support in D3Cold power state
•Port Arbitration: Round Robin (RR), Weighted RR and Time-based Weighted RR
•Extended Virtual Channel capability
-Two Virtual Channels (VC) and Eight Traffic Class (TC) support
-Dis abled VCs’ buffer is assigned to enabled VCs for resource sharing
-Independent TC/VC mapping for each port
-Provides VC arbitration selections: Strict Priority, Round Robin (RR) and Programmable Weighted
RR
•Supports Isochronous Traffic
-Isochronous traffic class mapped to VC1 only
-Strict time based credit policing
•Supports up to 512-b y t e ma ximu m payload s ize
•Programmable driver current and de-emphasis level at each individual port
•Support Access Control Service (ACS) for peer-to-peer traffic
•Support Address Translation (AT) packet for SR-IOV application
•Support OBFF and LTR
•Low Power Dissipation: 650 mW typical in L0 normal mode
•Industrial Temperature Range -40oto 85oC
•128-pin LQFP 14mm x 14mm package

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2GENERAL DESCRIPTION
Similar to the role o f PCI/PCIX Bridge in PCI/PCIX bus architecture, the function of PCI Express (PCIE) Switch is to
expand the connectivity to allow more end devices to be reached by host controllers in PCIE serial interconnect
architecture. The 4-lane PCIe Switch is in 3-port type configuration. It provides users the flexibility to expand or
fan-out the PCI Express lanes based on their application needs.
In the PCI Exp ress Architecture, the PCI E Switch forwards posted and non-posted requests, and completion packets
in e ither downstream or upstream direction concurrently as if a virtual PCI Bridge is in operation on each port.
By vis ualizing the port as a virtual Bridge, the Switch can be logically viewed as two-level cascaded multiple virtual
PCI-to-PCI Bridges, where one upstream-port Bridge sits on all downstream-port Bridges. Similar to a P CI Bridge
during enumeration, each port is given a unique bus number, device number, and function number by the initiating
software. The bus number, device number, and function number are combined to form a destination ID for each
specific port. In addition to that, the memory-map and IO address ranges are exclu s ively allocated to each port as
well. After the software enumeration is finished, the packets are routed to the dedicated port based on the embedded
address or destination ID. To ensure the packet integrity during forwarding, the Switch is not allowed to split the
packets to multiple s mall packets or merge the received packets into a large transmit packet. A ls o, the IDs of the
requesters and completers are kept unchanged along the path between ingress and egress port.
The Switch emp loys the architecture of Combined Input and Output Queue (CIOQ) in implementation.
The main reason for choosing CIOQ is that the required me mo ry bandwidth of input queue equals to the bandwidth of
ingress port rather than increasing proportionally with port numbers as an output queue Switch does. The CIOQ at
each ingress port contains separate dedicated queues to store packets. The packets are arbitrated to the egress port
bas ed on the PCIe transaction-ordering rule. For the packets without ordering information, they are permitted to pass
over each other in case that the addressed egress port is available to accept them. As to the packets required to follow
the ordering rule, the Head-Of-Line ( HO L) is s ue becomes unavoidable for packets destined to different egress ports
since the operation of producer-consumer model has to be retained; otherwise the system might occur hang-up
problem. On the other hand, the Switch places replay buffer at each egress port to defer the packets before sending it
out. This can assure the maximum throughput being achieved and therefore the Switch wo rks effic iently. Another
advantage of implementing CIOQ in PCIe Switch is that the credit announcement to the counterpart is simplified and
streamlined because of the credit-based flow control protocol. The protocol requires that each ingress port maintains
the credits independently without checking other ports' credit availability, which is otherwise required by pure output
queue architecture.
The Switch supports two virtual channels (VC0, VC1) and eight traffic classes (TC0 ~ TC7) at each port.
The ingress port independently assigns packets into the preferred virtual channel while the egress port outputs the
packet based on the predefined port and VC arbitration algorithm. For instance, the isochronous packet is given a
special traffic class number other than TC0 and mapped into VC1 accordingly. By employing the strict time based
credit policy for port arbitration and assigning higher priority to VC1 than VC0, the Switch can therefore guarantee
the time-s ens itiv e packet is not blocked by regular traffic to assure the quality of service. In addition, some data-
centric applications only carry TC0/VC0 t raffic. As a result, there are no packets that would consume VC1 bandwidth.
In order to improve the efficiency of buffer usage, the unused VC1 queues can be reassigned to VC0 and enable each
of the ingress ports to handle more data traffic bursts. This virtual channel resource relocation feature enhances the
performance of the PCIe Switch further.
The Switch provides the advanced feature of Access Control Service (ACS). This feature regulates which components
are allowed to communicate with each other within the PCIe mu ltip le-point fabric, and allows the system to have
more control over packet routing in the Switch. As a result, peer-to-peer traffic can be facilitated more accurately and
efficiently. When the system also implements Address Translation Service (ATS), the peer-to-peer requests with
translated address can be routed directly by enabling the corresponding option in ACS to avoid possible performance
bottleneck associated with re-direction, which introduces extra latency and may increase link and RC congestion.
The built-in Integrated Reference Clock Buffer of the PCI Exp res s Switch supports three reference clock outputs.
The clock buffer is froma single 100MHz clock input, and distributes the clock source to three outputs, which can be

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used by the downstream PCI Express end devices. The clock buffer feature can be enabled and disabled by strapping
pin setting.

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3PIN DESCRIPTION
3.1 PCI EXPRESS INTERFACE SIGNALS
NAME
PIN
TY P E
D ES C R I P TI O N
REFCLKP
REFCLKN
110, 111
I
Re fe rence Clock In put Pair: Connect to 100MHz differential clock
when integrated reference clock buffer is disabled (CLKBUF_PD=1),
or connect to one ofthe Integrated Reference Clock Output Pairs
(REFCLKO_P and REFCLKO_N) of this Switch when integrated
reference clock buffer is enabled (CLKBUF_PD=0).
The input clock signals must be delivered to the clock buffer cell
through an AC-coupled int erface so t hat only t he AC information o f
the clock is received, converted, and buffered. It is recommended that a
0.1uF be used in t he AC-co up ling.
PERP [3:0]
122, 102, 97,
128
I
PC I Expre s s Data Serial Input Pairs: Differential data receive
signals in four ports.
Port 0 (Upstream Port) Lane 0 is P ERP[0] an d P ERN[0 ]
Port 0 (Upstream Port) Lane 1 is P ERP[3] an d P ERN[3]
Port 1 (Downstream Port) is PERP[1] an d P ERN[1]
Port 2 (Downstream Port) is PERP[2] an d P ERN[2]
PERN [3:0]
121, 103, 98,
127
I
PETP [3:0 ]
118, 106, 100,
124
O
PC I Expre s s Data Serial Output Pa irs: Differential data transmit
signals in four ports.
Port 0 (Upstream Port) L an e 0 is P ETP[0 ] an d P ETN[0]
Port 0 (Upstream Port) L an e 1 is P ETP[3] an d P ETN[3]
Port 1 (Downstream Port) is PETP[1] an d P ETN[1]
Port 2 (Downstream Port) is PETP[2] an d P ETN[2]
PETN [3:0]
117, 107, 101,
123
O
P E RST _L
10
I
System Reset(Active LOW): When P ERST_L is asser t ed, t he
internal states of wholechip except sticky logics are initialized.
Please refer to Table 11-2forPREST_L spec.
DWNRST _L[2:1]
6, 5
O
Downstream Device Reset (Active LOW): DWNRST_L provides a
reset signal t o the devices connected t o thedownstreamports of th e
switch. The signal is active when either PE RST _Lis asserted or the
device is just plugged in t o t he swit ch. DWNRST _L [x] corresponds to
Portx, where x= 1,2 .
REXT
116
I
External Reference Resistor: Connect an external resistor (1.43K
Ohm +/- 1%) to REXT_GND to provide a reference to both thebias
currents and impedancecalibration circuitry.
REXT_GND
115
I
External Reference Resistor Ground: Connect to anexternal resistor
t o REXT .
REFCLKI_P ,
REFCLKI_N
74, 73
I
Integrated Reference Clock Input Pair: Connect to external
100MHz differential clock for the integrated reference clock buffer.
REFCLKO_P[2 :0]
78, 81, 85
O
Integrated Reference C lock Output Pairs: 100MHz external
differential HCSL clock outputs for t he integrated reference clock
buffer.
REFCLKO_N[2:0]
77, 80, 83
O
IREF
86
I
Differential Reference Clock Output CurrentResistor: External
resist or (475 Ohm +/- 1%) connection to set the differential reference
clock out put current.
CLKBUF_PD
60
I
Re fe rence Clock Output Pairs Power Down: W hen CLKBUF_PD is
asserted high, theintegrated reference clock buffer and Reference
Clock Outputs are disabled. When it is asserted low, t he integrated
reference clock buffer and Reference Clo ck Out put s are enabled. This
pin hasinternal pull-down. If no board t race is co n n ected t o t his pin,
the internal pull-
down resistor ofthis pin isenough.However, if pin is
connected to a board t race and not driven, it is recommended that an
external 330-ohm p ull-down resistor be used.

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3.2 PORT CONFIGURATION SIGNALS
NAME
PIN
TY P E
D ES C R I P TI O N
VC1_EN
18
I
Vi rtual Channel 1 Re source S haring En able: The chip provides the
capability t o support v irtual channel 1 (VC1 ), in addit ion t o t he
st an dard v ir t ual channel 0. W hen t his p in is assert ed high, Virt ual
Channel 1 is enabled, andvirtual channel resource sharingis not
available. When it is asserted low, the chip would allocate t he
additional VC1 resource to VC0, and VC1 capability is disabled. T his
pin hasinternal pull-down resist or. If no board t race is connected t o
this pin, the internal pull-
down resistor of this pin isenough.However,
if pin is connected to a board traceand not driven, it is recommended
that an external 330-ohm pull-down resist or be used.
RXPOLINV_DIS
24
I
Rx Po l arity In version Di sable: W h en RXPO LI NV_ DISis assert ed
high, it indicates to disable Rx P olarity Inversion detection function.
Otherwise, it indicates to enable Rx Polarity Inversion detection
function. This pin has internal pull-
down resistor. Ifno boardtrace is
connected t o t his pin, t he internal pull-down resistor of t his pin is
enough. However, if pinis connectedto a boardtraceandnot driven,it
is recommended that an external 330-ohm pull-down resist or be used.
PL_512B
53
I
Max. Payload Size 512B: When P L_512B is asserted high, it
indicates the max. payload size capability is 512B. Otherwise, it
indicates the m ax . Payload size is 256B. This pin has internal pull-
down resistor. If no boardtrace is connectedto thispin, theinternal
pull-down resistor of this pi
n isenough.However, if pinisconnected
to a board trace andnot driven, it is recommendedthat an external 330-
ohm pull-down resist or be used.
P RSN T [2:1]
20, 19
I
Present: W hen P RSN T is asserted low, it indicates that the device is
present in theslot ofdownstream port. Otherwise, it indicates the
absence of the device.P RSNT[x] is co rrespo ndent t o P ort x, where
x=1,2. These pins have internal pull-down resistors.
SLOT CLK
33
I
S l o t Clock C onfig uration: It determines if the downstream
component uses the same physical referenceclockthat the platform
pro vides o n t he connector. W hen SLOT CLK is h igh , t he p latform
reference clock is employed. By default, all downstream ports use the
same physical reference clock provided by platform. T his pin has
internal pull-
down resistor. If noboardtraceisconnectedtothis pin,
the internal pull-
down resistor ofthis pin isenough.However, if pin is
connected to a board t race and not driven, it is recommended that an
external 330-ohm p ull-down resistor be used.
SLOT _IMP[2:1]
46, 45
I
Slot Implemented: T hese signals are asserted to indicate that the
downstream portsare connectedto slots. SLOT_IMP[x] corresponds to
Portx, where x= 1,2. W hen SLOT _I MP[ x] is assert ed, t he Po rtx is
connected to slot. These pins haveinternal pull-down resistors. If n o
board trace is connected to these pins, the internal pull-down resistors
of these pins are enough. However, if pins are connected to a board
trace and not driven, it is recommended that external 330-ohm p ull-
down resist ors be used.
P O RT ST AT US[ 2: 0 ]
69, 68, 67
O
Port Status: These signals indicate thestatus of each port. Please
connect t o pin header for debug used.
PORTSTATUS[x] iscorrespondent toPort x, where x=0, 1,2.
3.3 MISCELLANEOUS SIGNALS
NAME
PIN
TY P E
D ES C R I P TI ON
EECLK
70
O
EEP R O M C l o ck: Clo ck signal t o the EEPROM interface.
EEPD
71
I/O
EEP R O M Data: Bi-directional serial data interface to and from the
EEPROM. The pin is set to ‘1’ by default .
SMBCLK
26
I
SMBus Clock: System management Bus Clock. This pin requires an
external 5.1K-ohm pull-up resistor.
SMBDATA
27
I/O
SMBus Data: Bi-Directional Sy st e m Management Bus Data. Thispin
requires an external 5.1K-ohm p ull-up resistor.

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NAME
PIN
TY P E
D ES C R I P TI ON
SCAN_EN
72
I/O
Fu l l -Scan Enable Control: For normal operation,SCAN_EN is an
out put wit h a value of “0”. SCAN_EN becomes an inp ut during
manufact uring t esting.
GP I O [ 7:0]
44, 43, 42,
39, 38, 37,
35, 36
I/O
Ge n eral Purpose Input a nd Output: Theseeight general-purpose
pinsare programmedaseitherinput-only or bi-directional p ins by
writing the GPIO output enable controlregister.
When SMBus is implemented, GPIO[7:5]act as the SMBus address
pins, which set Bit 2 to0 of the SMBus address.
Debug Mode Selection: In debug mode, GP IO[4:0] are used for
Debug Mode Selection.
P W R_ SAV
28
I
Power Saving Mode: PWR_SAVisa strappingpin. W hen t his pin is
pulled high when system is reset, the Power Saving Mode is enabled.
When this pin is pulled low when syst em is reset, the Power Saving
Mode is disabled. When t his pin is pulled low, it should be t ied t o
gro und t h ro ugh a 330-ohm pull-down resistor. When t his pin is pulled
high, a 5.1K-ohm pull-up resistor should be used.
TEST3
TEST5
TEST6
17
25
51
I
Test3/5/6:These pins areforinternal test purpose.Test3,Test5 and
T est 6 sh ould be t ied t o gro und t hrough a 3 30-ohm pull-down resistor.
TEST4
22
I
Test4: T he pin is for in ternal t est purpose. I t should be t ied t o gro und
through a 330-ohm pull-down r esist or for n ormal o peration.
Port S tatus Output Enable: In debug mo de, it is used t o enable
Port St atus out put.
TEST1
9
I
Test1: T he pin is fo r internal t est pur pose. It sh ould be t ied t o 3.3 V
through a 5.1K-ohm pull-up resist or f or normal o peration.
Debug Mode Enable: In debug mo de, it need be t ired t o lo w t hrough a
330-ohm pull-down resistor.
TEST2
16
I
Test2: T he pin is for internal test purpose. Test2should be t ied t o 3.3V
through a 5.1K-ohm pull-up resist or.
NC
7, 21, 47, 48,
52, 54, 57,
58, 59, 75,
76, 114
Not C onnected: T hese pins can be just left open.
3.4 JTAG BOUNDARY SCAN SIGNALS
Name
Pin
Ty pe
De scription
T CK
89
I
Te s t C l ock: Usedto clock state informationanddata intoandout of
t he chip durin g boun dary scan. When JTAG boundary scan function is
not implemented, this pin should be left open (NC).
TMS
92
I
Test Mode Select: Used to control thestate ofthe Test Access Port
controller. W hen JT AG boundary scan fun ctio n is not implemented,
thispin shouldbe pulledlowthrough a 330-Ohm p ull-down resistor.
TDO
88
O
Test Data Output: Used (in conjunction wit h T CK) t o shift data out of
the T est Access Port (TAP)in a serial bit stream.W hen JT AG
boundary scan function isnot implemented, thispin shouldbe left open
(NC).
TDI
93
I
Te s t Data In put: Used (in conjunction wit h TCK) t o shift dat a and
instructions into t he TAP in a serial bit stream. W hen JTAG boundary
scan functionisnot implemented, thispin shouldbe left open(NC).
TRST_L
94
I
Test Reset(Active LOW): Active LOW signal to reset the TAP
controller into an initialized state. When JTAG boundary scan function
is not implemented, t his pin should be p ulled lo w t hr ough a 330-Ohm
pull-down resistor.

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3.5 POWER PINS
NAME
PIN
TY P E
D ES C R I P TI O N
VDDC
3, 23, 29, 31,
40, 55, 62,65,
91
P
VDDC Supply (1.0V): Used as digital core power pins.
VDDR
1, 8, 49, 64, 96
P
VDDR Supply (3.3V): Used as digital I/O power pins.
CVDDR
79, 82, 84
P
VDDR Supply (3.3V): Used as referenceclock power pins.
VDDCAUX
13, 14
P
VDDCAUXSupply (1.0V): Used as auxiliary core power pins.
VAUX
15
P
VAUXSupply (3.3V): Used as auxiliary I/O power pins.
AVDD
99, 105, 108,
119, 125
P
AVDD Supply (1.0V): UsedasPCI Express analogpower pins.
AVDDH
113
P
AVDDH Su pply (3.3V): Used as P CI Ex press analog high voltage
power pins.
CGND
109, 112
P
Ground: Used as reference clock ground pins.
VSS
2, 4, 11, 12, 30,
32, 34, 41,50,
56, 61, 63,66,
87, 90, 95,104,
120, 126,129
P
VSS Ground: Used as ground pins.

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4PIN ASSIGNMENTS
4.1 PIN LIST of 129-PIN LQFP
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
1
VDDR
33
SLOTCLK
65
VDDC
97
PERP[1]
2
VSS
34
VSS
66
VSS
98
PERN[1]
3
VDDC
35
GPIO[1]
67
P O RT ST AT US[ 0]
99
AVDD
4
VSS
36
GPIO[0]
68
P O RT ST AT US[ 1]
100
P ET P[1]
5
DWNRST _L[1]
37
GPIO[2]
69
P O RT ST AT US[ 2]
101
P ET N[1]
6
DWNRST _L[2]
38
GPIO[3]
70
EECLK
102
PERP[2]
7
NC
39
GPIO[4]
71
EEPD
103
PERN[2]
8
VDDR
40
VDDC
72
SCAN_EN
104
VSS
9
TEST1
41
VSS
73
REFCLKI_N
105
AVDD
10
P E RST _ L
42
GPIO[5]
74
REFCLKI_P
106
P ET P[2]
11
VSS
43
GPIO[6]
75
NC
107
P ET N[2]
12
VSS
44
GPIO[7]
76
NC
108
AVDD
13
VDDCAUX
45
SLOT_IMP[1]
77
REFCLKO_N[2]
109
CGND
14
VDDCAUX
46
SLOT_IMP[2]
78
REFCLKO_P [2]
110
REFCLKP
15
VAUX
47
NC
79
CVDDR
111
REFCLKN
16
TEST2
48
NC
80
REFCLKO_N[1]
112
CGND
17
TEST3
49
VDDR
81
REFCLKO_P [1]
113
AVDDH
18
VC1_EN
50
VSS
82
CVDDR
114
NC
19
P RSN T [1]
51
TEST6
83
REFCLKO_N[0]
115
REXT_GND
20
P RSN T [2]
52
NC
84
CVDDR
116
REXT
21
NC
53
PL_512B
85
REFCLKO_P [0]
117
P ET N[3]
22
TEST4
54
NC
86
IREF
118
P ET P[3]
23
VDDC
55
VDDC
87
VSS
119
AVDD
24
RXPOLINV_DIS
56
VSS
88
TDO
120
VSS
25
TEST5
57
NC
89
T CK
121
PERN[3]
26
SMBCLK
58
NC
90
VSS
122
PERP[3]
27
SMBDATA
59
NC
91
VDDC
123
PET N[0 ]
28
P W R_ SAV
60
CLKBUF_PD
92
TMS
124
P ET P[0]
29
VDDC
61
VSS
93
TDI
125
AVDD
30
VSS
62
VDDC
94
TRST_L
126
VSS
31
VDDC
63
VSS
95
VSS
127
PERN[0]
32
VSS
64
VDDR
96
VDDR
128
PERP[0]
129
E_PAD

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5FUNCT IONAL DESCRIPT ION
Multiple virtual P CI-to-P CI Bridges (VPPB), connected by a virtual PCI bus, reside in the Switch. Each VPPB
contains the complete PCIe architecture layers that consist of the physical, data link, and transaction layer.
The packets entering the Switch via one of VPPBs are first converted fromserial bit-stream into parallel bus signals in
physical layer, stripped off the link-related header by data link layer, and then relayed up to the transaction layer to
extract out the transaction header. According to the address or ID embedded in the transaction header, the entire
transaction packets are forwarded to the destination VPPB for formatting as a serial-type PCIe packet through the
transmit circuits in the data link layer and physical layer. The following sections describe these function elements for
processing PCIe packets within the Switch.
5.1 PHYSICAL LAYER CIRCUIT
The phys ical layer c ircu it design is based on the PHY Interface for PCI Exp ress Architecture (PIPE). It contains
Physical Media Attachment (PMA) and Physical Cod ing Sub-layer (PCS) blocks. PMA includes Seria lize r/
Deserializer (SERDES), PLL1, Clock Recovery module, receiver detection circuits, beacon transmitter, electrical idle
detector, and input/output buffers. PCS consists of fra mer, 8B/10B encoder/decoder, rece iver e las tic buffe r, and PIPE
PHY control/status circuitries. To provide the fle xib ility for port configuration, each lane has its own control and
status signals for MAC to access individually. In addition, a pair of PRBS generator and checker is included for PHY
built-in self test. The main functions of physical layer circuits include the conversion between serial-link and parallel
bus, provision of clock source for the Switch, resolving clock difference in receiver end, and detection of physical
layer errors .
In order to meet the needs of different application, the drive amplitude, de-emphasis and equalization of each
transmitting channels can be adjusted using EEPROM individually. De-emphasis of -3.5 db is implemented by the
transmitters when full swing signaling is used,while an offset can be individually applied to each channel.
5.1.1 RECEIVER DETECTION
The physical layer circuits implement receiver detection, which detects the presence of an attached 50 ohm to ground
termination as per PCI Express Specification. The detect circuits determine if the voltage levels of the receiver have
crossed the internal threshold after a configurable time determined by the Receiver Detection Threshold field in the
PHY Parameter 2 Register (offset 7Ch, bit[6:4]), which can be configured by EEPROM or SMBUS settings.
Tabl e 5-1 Receiver Detection Threshold Settings
Receiver Detection
Threshold
Threshold
000
1.0 us
001
2.0 us
010
4.0 us (Recommended)
011
5.0 us
100
10 us
101
20 us
110
40 us
111
50 us
1Multiple lanes could share the PLL.

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5.1.2 RECEIVER SIGNAL DETECTION
Receiver signal idling is detected with levels above a programmable threshold specified by Receiver Signal Detect
fie ld in the PHY Parameter 2 Register (Offset 7Ch, bit[21:20]), which can be configured on a per-port basis via
EEPROM or SMBUS settings.
Tabl e 5-2 Receiver Signal Detect Threshold
Receiver Signal Detect
Min (mV ppd)
Max (mV ppd)
00
50
80
01 (Recommended)
65
175
10
75
200
11
120
240
5.1.3 RECEIVER EQUALIZATION
The receiver implements programmable equalizer via the Receiver Equalization fie ld in the P HY Parameter 2 Register
(Offset 7Ch, bit[25:22]), which can be configured on a per-port basis via EEPROM or SMBUS settings.
Tabl e 5-3 Receiver Equalization Settings
Receiver Equalization
Equalization
0000
Off
0010
Low
0110 (Recommended)
Medium
1110
High
5.1.4 TRANSMITTER SWING
The PCI Express transmitters support implementations of both full voltage swing and half (low) voltage swing. In full
swing signaling mode, the transmitters implement de-emphasis, while in half swing mode, the transmitters do not.
The Transmitter Swing field in the PHY Parameter 2 Register (offset 7Ch, Bit[30]) is used for the selection of full
swing signaling or half swing signaling, which can be configured on a per-port basis via EEPROM or SMBUS
settings.
Tabl e 5-4 Transmitter Swing Settings
Transmitter Swing
Mode
De-e m pha sis
0
Full Voltage Swing
Implemented
1
Half Volt age Swing
Not implemented
5.1.5 DRIVE AMPLITUDE AND DE-EMPHASIS SETTINGS
Depending on the operation condition (voltage swing and de-emphasis condition), one of the Drive Amplitude Base
Level fields in the S witch Operation Mode Register (offset 74h) and one of the Drive De-Emphasis Base Level fields
in the PHY Parameter 1 Register (offset 7Ah) are active for configuration of theamplitude and de-emphasis.
The final drive amplitude and drive de-emphasis are the summation of the base level value and the offset value.
The offset value for drive amplitude is 25 mV pd, and 6.25 mV pd for drive de-emphasis.
The driver output waveform is the synthesis of amplitude and de-emphasis. The driver amplitude without de-emphasis
is specified as a peak differential voltage level (mVpd), and the driver de-emphasis modifies the driver amplitude.

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-(Amplitude) –De-Emphasis
1
0
111
0 0 0
Input digital wave form
Output analog waveform
-(Amplitude) + De-Emphasis
Amplitude –De-Emphasis
Amplitude + De-Emphasis
Figure 5-1 Driver Output Waveform
5.1.6 DRIVE AMPLITUDE
Only one of the Drive Amplitude Level field in the Switch Operation Mode Reg ister (offset 74h, bit[20:16], bit[25:21]
and bit[30:26]) is active depending on the de-emphasis and swing condition. The settings and the corresponding
values of the amplitude level, which can be configured by EEPROM or SMBUS settings.
Tabl e 5-5 Drive Amplitude Base Level Registers
Register
De-Emphasis Condition
Swing Condition
C_DRV_LVL_3P5_NOM
-3.5 db
Full
C_DRV_LVL_6P0_NOM
-6.0 db
Full
C_DRV_LVL_HALF_NOM
N/A
Half
Tabl e 5-6 Drive Amplitude Base Level Settings
Setting Amplitude
(mV pd)
Setting Amplitude
(mV pd)
Setting Amplitude
(mV pd)
00000
0
00111
175
01110
350
00001
25
01000
200
01111
375
00010
50
01001
225
10000
400
00011
75
01010
250
10001
425
00100
100
01011
275
10010
450
00101
125
01100
300
10011
475
00110
150
01101
325
Others
Reserved
Note :
1. Nominal levels. Actual levels will vary with temperature, voltage and boardeffects.
2. The maximumnominal amplitude of the out put driver is 4 75 mV pd. Combined values of driver amplitude and de-emphasis greater
than 475mVpdshouldbe avoided.
3. At higher amplitudes, actual swings will be less than thetheoretical value due to process variations and environment factors, such as
voltage overhead compression, package losses, board losses, and ot her effects.

PI7C9X2G304SL Page 21 of 20 September 2017
Document Number DS39933 R ev 2-2 w ww.diodes .com© Diodes Incorpor ated
PI7C9X2G304SL
5.1.7 DRIVE DE-EMPHASIS
The Drive De-Emphasis Level field in the PHY Parameter 1 Register (Offset 78h, b it[20:16], bit [25:21] and
bit[30:26]) controls the de-emphasis base level. The settings and the corresponding values of the de-emphasis level,
which can be configured globally via EEPROM or SMBUS settings.
Tabl e 5-7 Drive De-Emphasis Base Level Register
Register
De-Emphasis Condition
C_ EMP _ POST _GEN1_3P5_NOM
-3.5 db
C_ EMP _ POST _GEN2_3P5_NOM
-3.5 db
C_ EMP _ POST _GEN2_6P0_NOM
-6.0 db
Tabl e 5-8 Drive De-Emphasis Base Level Settings
Setting
De-Emphasis
(mV pd)
Setting
De-Em p h asi s
(mV pd)
Setting
De-Emphasis
(mV pd)
00000
0.0
01011
69.0
10110
137.5
00001
6.0
01100
75.0
10111
144.0
00010
12.5
01101
81.0
11000
150.0
00011
19.0
01110
87.0
11001
156.0
00100
25.0
01111
94.0
11010
162.5
00101
31.0
10000
100.0
11011
169.0
00110
37.5
10001
106.0
11100
175.0
00111
44.0
10010
112.5
11101
181.0
01000
50.0
10011
119.0
11110
187.5
01001
56.0
10100
125.0
11111
194.0
01010
62.5
10101
131.0
-
-
Note :
1. Nominal levels. Actual levels will vary with temperature, voltage and board effects.
2. T he maximum nominal amplitude of the out put driver is 475 mV pd. Combin ed values of driver amplitude and de-emphasis greater
than 475mVpdshouldbe avoided.
3. At higher amplitudes, actual swings will be less than thetheoretical value due to process variations and environment factors,such as
voltage overhead compression, package losses, board losses, and ot her effects.
5.1.8 TRANSMITTER ELECTRICAL IDLE LATENCY
After the last character of the PCI Express transmission, the output current is reduced, and a differential voltage of
less than 20 mV with common mode of VTX-CM -DC is established within 20 UI. This delay time is programmable
via Transmitter PHY Latency field in the PHY Parameter 2 Register (Offset 7Ch, bit[3:0]), which can be configured
by EEPROM or SMBUS settings.
5.2 DATA LINK LAYER (DLL)
The Data Link Layer (DLL) provides a reliable data transmission between two PCI Express points. An ACK/NACK
protocol is employed to guarantee the integrity of the packets delivered. Each Transaction Layer Packet (TLP) is
protected by a 32-bit LCRC for error detection. The DLL receiver performs LCRC calculation to determine if the
incoming packet is corrupted in the serial link. If an LCRC error is found, the DLL transmitter would issue a NACK
data link layer packet (DLLP) to the opposite end to request a re-transmission, otherwise an ACK DLLP would be
sent out to acknowledge on reception of a good TLP.
In the transmitter, a retry buffer is implemented to store the transmitted TLPs whose corresponding A CK/NA CK
DLLP have not been received yet. When an ACK is received, the TLPs with sequence number equals to and smaller
than that carried in the ACK would be flushed out from the buffer. If a NACK is received or no ACK/NACK is
returned from the link partner after the replay timer expires, then a replay mechanism built in DLL transmitter is