Dynamic Engineering PMC-XM-DIFF User manual

DYNAMIC ENGINEERING
150 DuBois, Suite C
Santa Cruz, CA 95060
[phone] Fax [phone]
http://www.dyneng.com
[email protected]
Est. 1988
User Manual
PMC-XM-DIFF
Interface Module with Re-configurable I/O logic
RS-485 or LVDS or mixed
34 Differential Pairs at Bezel
32 Differential Pairs at Pn4
Revision A
Corresponding Hardware: Revision A
10-2007-0201
Corresponding Firmware: Revision A

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PMC-XM-DIFF
PMC based interface module
With plug-in I/O hardware and Re-
configurable I/O logic
Dynamic Engineering
150 DuBois, Suite C
Santa Cruz, CA 95060
[phone]
FAX: [phone]
This document contains information of
proprietary interest to Dynamic Engineering. It
has been supplied in confidence and the
recipient, by accepting this material, agrees that
the subject matter will not be copied or
reproduced, in whole or in part, nor its contents
revealed in any manner or to any person except
to meet the purpose for which it was delivered.
Dynamic Engineering has made every effort to
ensure that this manual is accurate and
complete. Still, the company reserves the right to
make improvements or changes in the product
described in this document at any time and
without notice. Furthermore, Dynamic
Engineering assumes no liability arising out of
the application or use of the device described
herein.
The electronic equipment described herein
generates, uses, and can radiate radio
frequency energy. Operation of this equipment
in a residential area is likely to cause radio
interference, in which case the user, at his own
expense, will be required to take whatever
measures may be required to correct the
interference.
Dynamic Engineering’s products are not
authorized for use as critical components in life
support devices or systems without the express
written approval of the president of Dynamic
Engineering.
Connection of incompatible hardware is likely to
cause serious damage.
©2007-2010 by Dynamic Engineering.
Other trademarks and registered trademarks are
owned by their respective manufactures.
Manual Revision A. Revised February 26, 2010

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Table of Contents
PRODUCT DESCRIPTION 6
THEORY OF OPERATION 8
PROGRAMMING 9
ADDRESS MAP SPARTAN3 10
Register Definitions 11
PMC_XM_BASE 11
PMC_XM_USER_SWITCH 13
XM_CHAN0/1_CNTRL 15
XM_CHAN0/1_STATUS 17
XM_CHAN0/1_WR/RD_DMA_PNTR 19
XM_CHAN0/1_FIFO 19
XM_CHAN0/1_TX_AMT_LVL 20
XM_CHAN0/1_RX_AFL_LVL 20
XM_CHAN0/1_TX/RX_FIFO_COUNT 21
ADDRESS MAP: VIRTEX ATP DESIGN 22
Register Definitions 23
XM_VATP_BASE 23
XM_VATP_STATUS 25
XM_VATP_CHAN0/1_CNTRL 26
XM_VATP_CHAN0/1_STATUS 27
XM_VATP_TX0/1_FIFO 28
XM_VATP_RX0/1_FIFO 28
XM_VATP_TX0/1_DCOUNT 29
XM_VATP_RX0/1_DCOUNT 29
VIRTEX PIN OUT 30
TRANSITION MODULE MECHANICAL DRAWING 39
MEZZANINE MODULE CONNECTOR J1 40

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MEZZANINE MODULE CONNECTOR J2 41
APPLICATIONS GUIDE 42
Interfacing 42
Construction and Reliability 43
Thermal Considerations 43
WARRANTY AND REPAIR 44
Service Policy 44
Out of Warranty Repairs 44
For Service Contact: 44
SPECIFICATIONS 45
ORDER INFORMATION 46

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List of Figures
FIGURE 1 PMC-XM BLOCK DIAGRAM 6
FIGURE 2 PMC-XM SPARTAN3 XILINX ADDRESS MAP 10
FIGURE 3 PMC-XM SPARTAN3 BASE CONTROL REGISTER 11
FIGURE 4 PMC-XM SPARTAN3 USER SWITCH PORT 13
FIGURE 5 PMC-XM SPARTAN3 STATUS PORT 14
FIGURE 6 PMC-XM SPARTAN3 CHANNEL CONTROL REGISTER 15
FIGURE 7 PMC-XM SPARTAN3 CHANNEL STATUS PORT 17
FIGURE 8 PMC-XM SPARTAN3 CHANNEL DMA POINTER PORT 19
FIGURE 9 PMC-XM SPARTAN3 CHANNEL FIFO PORT 19
FIGURE 10 PMC-XM SPARTAN3 CHANNEL TX ALMOST EMPTY PORT 20
FIGURE 11 PMC-XM SPARTAN3 CHANNEL RX ALMOST FULL PORT 20
FIGURE 12 PMC-XM SPARTAN3 CHANNEL TX/RX FIFO COUNT PORT 21
FIGURE 13 PMC-XM VIRTEX (ATP) XILINX ADDRESS MAP 22
FIGURE 14 PMC-XM VIRTEX (ATP) BASE CONTROL REGISTER 23
FIGURE 15 PMC-XM VIRTEX (ATP) BASE STATUS PORT 25
FIGURE 16 PMC-XM VIRTEX (ATP) CHANNEL CONTROL REGISTER 26
FIGURE 17 PMC-XM VIRTEX (ATP) CHANNEL STATUS PORT 27
FIGURE 18 PMC-XM VIRTEX (ATP) CHANNEL TX FIFO PORT 28
FIGURE 19 PMC-XM VIRTEX (ATP) CHANNEL RX FIFO PORT 28
FIGURE 20 PMC-XM VIRTEX (ATP) CHANNEL TX FIFO COUNT PORT 29
FIGURE 21 PMC-XM VIRTEX (ATP) CHANNEL RX FIFO COUNT PORT 29
FIGURE 22 PMC-XM MEZZANINE CONNECTOR J1 PINOUT 40
FIGURE 23 PMC-XM MEZZANINE CONNECTOR J2 PINOUT 41

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Product Description
The PMC-XM-DIFF features a Xilinx Spartan3-1500 676 pin FPGA to implement the
PCI interface and two independent I/O channels each with a separate input and output
scatter-gather DMA engine to move data to/from host memory over the local 32-bit 33
MHz PCI bus. A Xilinx Virtex4 668 pin FPGA interfaces between the Spartan3 and the
IO. The IO can be configured with RS-485, LVDS or both.
Each IO has separate direction, and termination controls to allow any combination of
inputs and outputs. Impedance controlled and length matched within the mil [.001”] to
allow for any user requirement.
Other features include on-board PLL, optional RAM (1Mx36-bit QDDRII RAM),
temperature sensor, DIP Switch, Built in DMA, and user LED’s.
PCI IF
Data Flow
Control
FPGA
1M x 36 RAM
DMA
RX TX
4Kx32 FIFO
4Kx32 FIFO
RX TX
4Kx32 FIFO
4Kx32 FIFO
User Virtex PLL
34 LVDS / RS-485 IO
Programmable Terminations LEDs(4)
DIPSWITCH
TEMP
SENSOR
FIGURE 1 PMC-XM-DIFF BLOCK DIAGRAM
The engineering kit comes with a basic design for the Virtex consisting of the VHDL
package used to generate the ATP implementation. The design includes decoding,
DMA , two channels, IO loop-back and more. The package can include the Windows®
driver and reference code. The reference software is provided as source and can be

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user modified to do whatever you want. The package includes an auto design detection
feature to automatically load menus corresponding to different designs loaded into the
Virtex. The user can change the design number and use the generic driver to access
new features added to the clients implementation. The Virtex can be loaded from
FLASH and overwritten with software. The reference package includes the Virtex load
utilities, PLL programming software, and Temperature sensor read as well as IO loop-
back tests.

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Theory of Operation
The Spartan3 FPGA implements the PCI interface for the PMC-XM. Data is transferred
to/from the PCI bus using single-word accesses for control/status or through the four
scatter-gather DMA engines (two in and two out) for accessing the two I/O channels,
each with a 4K x 32-bit transmit FIFO and a 4K x 32-bit receive FIFO.
A data transfer state-machine controls the bidirectional bursting of data between the
Spartan3 and the Virtex for the two I/O channels. The data is transferred across a 32-
bit bidirectional data bus and Virtex control/status registers are addressed by an eight-
bit address bus. The transfers are independently enabled from the Channel Control
Registers in the Spartan3. In the Virtex ATP design used by Dynamic Engineering to
test the PMC-XM hardware, there are also four corresponding 4K x 32-bit FIFOs to
buffer the bursted data. Handshaking signals generated by the Virtex let the transfer
state-machine know when to burst data and, when the FIFOs are near their limits, when
to move only single words.
The plug-in Interface Module is accessed through the Virtex by the user-specified
design with which it is configured. A programmable PLL supplies two independent clock
frequencies (maximum 200 MHz) to be used by the user. Digital clock managers
(DCMs) in the Virtex FPGA can be used to further enhance the clock capabilities. A
1Mx36-bit QDDRII RAM is accessible by the Virtex for intermediate processing of I/O
data and a 13-bit digital temperature sensor can be used to read the ambient
temperature of the PMC-XM environment.
Scatter-gather DMA is accomplished by writing a list of memory descriptors to host
memory. Each descriptor consists of three long-words: the physical address of a block
of contiguous user memory, the length of that block and a pointer to the next list entry.
The last word of each descriptor also contains two flag-bits that are replaced with zeros
for the actual memory access. Bit 0 is the end-of-chain bit. When this bit is set, the
current descriptor is the last in the list. Bit 1 is the direction bit. When this bit is set, it
indicates that the transfer is from the module to host memory. When this bit is zero,
data is transferred from host memory to the PMC-XM.
The address of the first list entry is written to the DMA engine to begin DMA processing.
The DMA continues until the list is complete and an interrupt is signaled to clean-up the
transfer and potentially begin another. It is necessary that all memory pages that are to
be accessed be physically resident in memory while the DMA is in progress.
The four DMA engines can all operate simultaneously. PCI bus access is arbitrated on
a round-robin basis with a DMA engine relinquishing the bus at the end of each list entry
transfer or when the corresponding FIFO gets close to full for the transmit or empty for
the receive. The arbiter can also be configured to give priority to a channel that is
approaching the FIFO limit (almost-empty for the transmit or almost-full for the receive).

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Programming
Programming the PMC-XM requires only the ability to read and write data from the host.
The base address is determined during system configuration of the PCI bus. The base
address refers to the first user address for the slot in which the PMC is installed. The
VendorId = 0x10EE. The CardId = 0x0024. Current revision = 0x07
Depending on the software environment it may be necessary to set-up the system
software with the PMC-XM "registration" data. For example in WindowsNT there is a
system registry, which is used to identify the resident hardware.
To use DMA it will be necessary to acquire a block of non-paged memory that is
accessible from the PCI bus in which to store chaining descriptor list entries.
At Dynamic Engineering the PMC-XM-DIFF is tested in a Windows environment and we
use the Dynamic Engineering Drivers to do the hardware accesses and manage the
DMA’s. We use MS Visual C++ in conjunction with the drivers to write our test software.
Please consider purchasing the engineering kit for the PMC-XM; the software kit
includes the drivers and our test suite.
The Spartan3 address space begins at address offset 0, the Virtex address space
begins at offset 0x400.

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Address Map Spartan3
Register Name Offset Description
PMC_XM_BASE 0x0000 // Base control register
PMC_XM_USER_SWITCH 0x0004 // User switch/Xilinx rev. read port
PMC_XM_STATUS 0x0008 // Interrupt status/clear port
XM_CHAN0_CNTRL 0x0010 // Channel 0 Control register offset
XM_CHAN0_STATUS 0x0014 // Channel 0 Status read/latch clear port offset
XM_CHAN0_WR_DMA_PNTR 0x0018 // Channel 0 Write DMA physical address register
XM_CHAN0_RD_DMA_PNTR 0x001C // Channel 0 Read DMA physical address register
XM_CHAN0_FIFO 0x0020 // Channel 0 FIFO offset for single word access
XM_CHAN0_TX_AMT_LVL 0x0024 // Channel 0 TX almost empty level register offset
XM_CHAN0_RX_AFL_LVL 0x0028 // Channel 0 RX almost full level register offset
XM_CHAN0_TX_FIFO_COUNT 0x002C // Channel 0 TX FIFO count read port offset
XM_CHAN0_RX_FIFO_COUNT 0x0030 // Channel 0 RX FIFO count read port offset
XM_CHAN1_CNTRL 0x0040 // Channel 1 Control register offset
XM_CHAN1_STATUS 0x0044 // Channel 1 Status read/latch clear port offset
XM_CHAN1_WR_DMA_PNTR 0x0048 // Channel 1 Write DMA physical address register
XM_CHAN1_RD_DMA_PNTR 0x004C // Channel 1 Read DMA physical address register
XM_CHAN1_FIFO 0x0050 // Channel 1 FIFO offset for single word access
XM_CHAN1_TX_AMT_LVL 0x0054 // Channel 1 TX almost empty level register offset
XM_CHAN1_RX_AFL_LVL 0x0058 // Channel 1 RX almost full level register offset
XM_CHAN1_TX_FIFO_COUNT 0x005C // Channel 1 TX FIFO count read port offset
XM_CHAN1_RX_FIFO_COUNT 0x0060 // Channel 1 RX FIFO count read port offset
FIGURE 2 PMC-XM SPARTAN3 XILINX ADDRESS MAP
The address map provided is for the local decoding performed within the PMC-XM
Spartan3 Xilinx. The addresses are all offsets from a base address. The base address
and interrupt level are provided by the host in which the PMC-XM is installed.
The host system will search the PCI bus to find the assets installed during power-on
initialization. The VendorId = 0x10EE and the CardId = 0x0024 for the PMC-XM.
Interrupts are requested by the configuration space. PCIView and other third party
utilities can be useful to see how your system is configured. Dynamic Engineering
recommends using the Dynamic Engineering Drivers to take care of initialization and
device registration.

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Register Definitions
PMC_XM_BASE
[0x0000] Base Control Register (read/write)
Base Control Register
Data Bit Description
31-17 Spare
16 Load Virtex
15-10 Spare
9 Virtex Init
8 Virtex Reset
7 Virtex Flash Enable
6 Slave Serial Mode Enable
5 Virtex Program Init
4 Virtex Program Select
3 Flash Select
2 Flash Control
1 Force Interrupt
0 Master Interrupt Enable
FIGURE 3 PMC-XM SPARTAN3 BASE CONTROL REGISTER
All bits are active high and default to ‘0’ on reset or power-up.
Master Interrupt Enable: This bit enables the interrupts for the base portion of the XM
design. When this bit is a ‘1’, the interrupt is enabled; and when this bit is a ‘0’ the
interrupt is disabled. Currently the only interrupt source for this portion of the design is
the Force Interrupt bit.
Force Interrupt: When this bit is ‘1’ and the Master Interrupt Enable is ‘1’, an interrupt
will be generated. This bit is useful for software development and debugging.
Flash Control: When this bit is ‘1’, the Flash Select bit controls which Flash Prom is
connected to the JTAG port. When this bit is ‘0’, I/O bit 63 controls the selection. When
I/O bit 63 is grounded, the Virtex Flash is selected; when I/O bit 63 is open, the signal is
pulled high and the Spartan3 Flash is selected.
Flash Select: When Flash Control is set to ‘1’ this bit controls which Flash Prom is
connected to the JTAG port. When Flash Select is ‘0’, the Virtex Flash is selected;
when Flash Select is ‘1’, the Spartan3 Flash is selected. When Flash Control is ‘0’, this
bit has no effect.

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Virtex Program Select: When this bit is ‘1’, the Virtex Flash is controlled by the Virtex
Flash Enable bit. When this bit is ‘0’, the Virtex Flash is controlled by the Virtex done
bit.
Virtex Program Init: When this bit is set to ‘1’ it forces the Virtex to re-configure from the
Flash Prom. When this bit is ‘0’, the Virtex can be re-configured by a bit-file load.
Slave Serial Mode Enable: When this bit is set to ‘1’, slave serial programming mode is
selected on the Virtex. When this bit is ‘0’ master serial mode is selected. Slave serial
mode is used when the Virtex is programmed from a file by the Spartan3 and master
serial mode is used when the Virtex configures from the on-board flash.
Virtex Flash Enable: When this bit is ‘0’ and the Virtex Program Select bit is ‘1’, the
Virtex flash is disabled so that the Spartan3 can program the Virtex from a bit-file.
Virtex Reset: When this bit is ‘1’, all the registers and FIFOs in the Virtex are reset.
When this bit is ‘0’, the Virtex can resume normal operation.
Virtex Init: When set to ‘1’, this bit delays configuration when a configuration cycle has
been initiated. When this bit transitions to ‘0’, the mode bits are sampled and the
configuration can proceed. The bit then becomes a status bit, which is read from the
Status register, a ‘0’ indicating a CRC error.
Load Virtex: when set to ‘1’, begins the process of programming the Virtex device from
a bit-file. The data must be read from the file and loaded into the TX0 FIFO. When the
hardware detects that the load is complete this bit will be automatically cleared.

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PMC_XM_USER_SWITCH
[0x0004] User Switch Port (read only)
Dip-Switch Port
Data Bit Description
31-16 Spare
15-8 Xilinx Design Revision Number
7-0 Sw7-0
FIGURE 4 PMC-XM SPARTAN3 USER SWITCH PORT
Sw7-0: The user switch is read through this read-only port. The bits are read as the
lowest byte. Access the port as a long word and mask off the undefined bits. The dip-
switch positions are defined in the silkscreen. For example the switch figure below
indicates a 0x12.
Xilinx design revision number: The value of the second byte of this port is the rev.
number of the Xilinx design (currently 0x05 - rev. E).
1
7 0
0

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PMC_XM_STATUS
[0x0008] Status Register Read / Latch Clear Write
Status Register
Data Bit Description
31 Interrupt Status
30-24 Spare
23 Virtex Status 3
22 Virtex Status 2
21 Virtex Status 1
20 Virtex Status 0
19-10 Spare
9 Virtex Init Status
8 Virtex Configuration Done
7-1 Spare
0 Local Interrupt Active
FIGURE 5 PMC-XM SPARTAN3 STATUS REGISTER
Local Interrupt Active: When read as a ‘1’, a local interrupt condition is active.
Currently, the only such condition is the Force Interrupt bit in the Base Control Register.
A system interrupt will not occur unless the Master Interrupt Enable bit in the Base
Control Register is also set. When read as a ‘0’, no local interrupt conditions are active.
Virtex Configuration Done: When read as a ‘1’, the Virtex FPGA has successfully
configured. When read as a ‘0’, the Virtex configuration was not successful.
Virtex Init Status: When read as a ‘1’ after the Virtex configuration, it indicates that a
CRC error did not occur during the Virtex configuration. When read as a ‘0’ after the
Virtex configuration, it indicates that a CRC error occurred during the previous Virtex
configuration. In this case the Done bit should also be low.
Virtex Status 3-0: These bits are driven by the Virtex to indicate arbitrary status
conditions. In the current Virtex ATP design they are all low, but they can be assigned
for any purpose desired.
Interrupt Status: When read as a ‘1’, an enabled local interrupt condition is active and a
system interrupt should be asserted. When read as a ‘0’, no enabled local interrupt is
active.

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XM_CHAN0/1_CNTRL
[0x0010, 0x0040] Channel Control Register (read/write]
Control Register
Data Bit Description
31-9 Spare
11 DMA Read Arbitration Priority Enable
10 DMA Write Arbitration Priority Enable
9 Virtex Interrupt Enable
8 Receive Enable
7 Transmit Enable
6 Force Interrupt
5 Master Interrupt Enable
4 DMA Read Enable
3 DMA Write Enable
2 FIFO Bypass
1 RX FIFO Reset
0 TX FIFO Reset
FIGURE 6 PMC-XM SPARTAN3 CHANNEL CONTROL REGISTER
TX/RX FIFO Reset: When this bit is ‘1’, the transmit or receive FIFO for the referenced
channel is placed in a reset condition. When this bit is ‘0’, the corresponding FIFO is in
a normal operational state.
FIFO Bypass: When this bit is ‘1’, any data written to the transmit FIFO will be
transferred to the receive FIFO as long as there is room in the receive FIFO. This
facilitates FIFO loop-back testing. When this bit is ‘0’, data written to the transmit FIFO
will remain in the FIFO until read by the data transfer state machine.
DMA Write Enable: When this bit is ‘1’, the write DMA interrupt is enabled for the
referenced channel. When this bit is ‘0’, the write DMA interrupt is disabled.
DMA Read Enable: When this bit is ‘1’, the read DMA interrupt is enabled for the
referenced channel. When this bit is ‘0’, the read DMA interrupt is disabled.
Master Interrupt Enable: This bit enables the local interrupts for the referenced channel.
When this bit is a ‘1’, the interrupt is enabled; and when this bit is a ‘0’ the interrupt is
disabled. Currently the only interrupt source for this portion of the design is the Force
Interrupt bit in this register.
Force Interrupt: When this bit is ‘1’ and the Master Enable is a ‘1’, a system interrupt will

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occur. This bit is useful for software development and debugging.
Transmit Enable: When this bit is ‘1’, the transfer state machine is enabled to move data
from the referenced channel’s transmit FIFO to the corresponding Virtex transmit FIFO.
When this bit is ‘0’, the transmit transfer state machine is disabled.
Receive Enable: When this bit is ‘1’, the transfer state machine is enabled to move data
from the referenced channel’s Virtex receive FIFO to the corresponding local receive
FIFO. When this bit is ‘0’, the receive transfer state machine is disabled.
Virtex Interrupt Enable: When this bit is ‘1’, the corresponding Virtex interrupt (VINT0 for
channel 0 or VINT1 for channel 1) is enabled to cause a system interrupt when active.
When this bit is ‘0’, the Virtex interrupt can not cause a system interrupt.
DMA Write Arbitration Priority Enable: When this bit is ‘1’, the write DMA for the
referenced channel will receive priority if the TX FIFO has become almost empty as
defined by the value stored in the TX_AMT_LVL register. When this bit is ‘0’, the DMA
arbitration will follow round-robin arbitration priority.
DMA Read Arbitration Priority Enable: When this bit is ‘1’, the read DMA for the
referenced channel will receive priority if the RX FIFO has become almost full as
defined by the value stored in the RX_AFL_LVL register. When this bit is ‘0’, the DMA
arbitration will follow round-robin arbitration priority.

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XM_CHAN0/1_STATUS
[0x0014, 0x0044] Channel Status Read / Latch Clear Write
Status Register
Data Bit Description
31 INT_STAT
30-18 Spare
17 Virtex Interrupt Active
16 Local Interrupt Active
15 Read DMA Interrupt Active
14 Write DMA Interrupt Active
13 Read DMA Error
12 Write DMA Error
11-8 Spare
7 Receive FIFO Valid
6 Receive FIFO Full
5 Receive FIFO Almost Full
4 Receive FIFO Empty
3 Spare
2 Transmit FIFO Full
1 Transmit FIFO Almost Empty
0 Transmit FIFO Empty
FIGURE 7 PMC-XM SPARTAN3 CHANNEL STATUS REGISTER
Transmit FIFO Empty: When read as a ‘1’, the corresponding transmit FIFO is empty.
When read as a ‘0’, the FIFO has at least one word in it.
Transmit FIFO Almost Empty: : When read as a ‘1’, the corresponding transmit FIFO is
almost empty as determined by the value entered in the almost empty level register.
When read as a ‘0’, there is more data in the FIFO than specified in the level register.
Transmit FIFO Full: When read as a ‘1’, the corresponding transmit FIFO is full. When
read as a ‘0’, there is room for at least one more word in the FIFO.
Receive FIFO empty: When read as a ‘1’, the corresponding receive FIFO is empty.
When read as a ‘0’, the FIFO has at least one word in it.
Receive FIFO Almost Full: When read as a ‘1’, the corresponding receive FIFO is
almost full as determined by the value entered in the almost full level register. When
read as a ‘0’, there is less data in the FIFO than specified in the level register.

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Receive FIFO Full: When read as a ‘1’, the corresponding receive FIFO is full. When
read as a ‘0’, there is room for at least one more word in the FIFO.
Receive FIFO Valid: When read as a ‘1’, there is valid receive data to read. When read
as a ‘0’, there is no valid receive data. There is a four-deep pipeline on the output of the
RX FIFO that will be filled before data is retained in the FIFO. Therefore even though
the FIFO is empty there may actually be up to four long-words of valid receive data.
This status bit indicates when there is valid data even though the FIFO is empty.
Write DMA Error: When read as a ‘1’, a write DMA error has been detected. This will
occur if there is a target or master abort or if the direction bit in the next pointer of one of
the chaining descriptors is a one. When read as a ‘0’, no error has occurred.
Read DMA Error: When read as a ‘1’, a read DMA error has been detected. This will
occur if there is a target or master abort or if the direction bit in the next pointer of one of
the chaining descriptors is a zero. When read as a ‘0’, no error has occurred.
Write DMA Interrupt Active: When read as a ‘1’, a write DMA interrupt is latched. This
indicates that the scatter-gather list for the current write DMA has completed, but the
associated interrupt has yet to be completely processed. When read as a ‘0’, no write
DMA interrupt is pending.
Read DMA Interrupt Active: When read as a ‘1’, a read DMA interrupt is latched. This
indicates that the scatter-gather list for the current read DMA has completed, but the
associated interrupt has yet to be completely processed. When read as a ‘0’, no read
DMA interrupt is pending
Local Interrupt Active: When read as a ‘1’, a local interrupt condition is active for the
referenced channel. Currently, the only such condition is the Force Interrupt bit in the
Channel Control Register. A system interrupt will not occur unless the Master Interrupt
Enable bit in the Channel Control Register is also set. When read as a ‘0’, no local
interrupt conditions are active.
Virtex Interrupt Active: When read as a ‘1’, the corresponding Virtex interrupt (VINT0 for
channel 0 or VINT1 for channel 1) is active. A system interrupt will not occur unless the
Virtex Interrupt Enable in the Channel Control Register is set. When read as a ‘0’, the
Virtex interrupt is inactive.
INT_STAT: When read as a ‘1’, an enabled channel interrupt condition is active and a
system interrupt should be asserted. When read as a ‘0’, no enabled channel interrupt
is active.

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XM_CHAN0/1_WR/RD_DMA_PNTR
[0x0018, 0x001C, 0x0048, 0x004C] DMA Address Register (Write only)
DMA Pointer Address Register
Data Bit Description
31-0 First Chaining Descriptor Physical Address
FIGURE 8 PMC-XM SPARTAN3 CHANNEL DMA POINTER REGISTER
These write-only ports are used to initiate scatter-gather DMAs. When the physical
address of the first chaining descriptor is written to one of these ports, the
corresponding DMA engine reads three successive long words beginning at that
address. The first is the address of the first memory block of the DMA buffer, the
second is the length in bytes of that block, and the third is the address of the next
chaining descriptor in the list of buffer memory blocks. This process is continued until a
bit in one of the next pointer values read indicates that it is the end of the chain.
Note: Writing a zero to one of these ports will abort the associated DMA if one is in
progress.
XM_CHAN0/1_FIFO
[0x0020, 0x0050] Write TX/Read RX FIFO Port
TX / RX FIFO Port
Data Bit Description
31-0 FIFO Data 31-0
FIGURE 9 PMC-XM SPARTAN3 CHANNEL FIFO PORT
Data written to this address is written into the transmit FIFO as long as the FIFO is not
full. When this address is read a data-word is read from the receive FIFO. When the
receive FIFO becomes empty, the last data-word that was in the FIFO will be returned.

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XM_CHAN0/1_TX_AMT_LVL
[0x0024, 0x0054] TX Almost Empty Level Register (read/write)
TX Almost Empty Level Register
Data Bit Description
31-16 Spare
15-0 TX FIFO Almost Empty Level
FIGURE 10 PMC-XM SPARTAN3 CHANNEL TX ALMOST EMPTY REGISTER
This register specifies the level at which the transmit FIFO almost empty level will be
asserted. When the number of data words in the transmit FIFO is less than or equal to
this count the almost empty status will be asserted.
XM_CHAN0/1_RX_AFL_LVL
[0x0028, 0x0058] RX Almost Full Level Register (read/write)
RX Almost Full Level Register
Data Bit Description
31-16 Spare
15-0 RX FIFO Almost Full Level
FIGURE 11 PMC-XM SPARTAN3 CHANNEL RX ALMOST FULL REGISTER
This register specifies the level at which the receive FIFO almost full level will be
asserted. When the number of data words in the receive FIFO is greater than or equal
to this count the almost full status will be asserted.