e2v EV10AQ190TPY-DK User manual

EV10AQ190x-DK
VITA 57 FMC Quad 10-bit ADC Demo Kit

EV10AQ190x-DK User Guide
1067BX–BDC–12/11

EV10AQ190x-DK - User Guide i
1067BX–BDC–12/11
Table of Contents
Section 1
General Overview ................................................................................. 1-1
1.1 Disclaimer .................................................................................................1-1
1.2 Quad 10-bit ADC.......................................................................................1-2
1.3 Demo Kit ...................................................................................................1-3
Section 2
Quick Start ............................................................................................ 2-1
2.1 Operating Procedure.................................................................................2-1
2.2 Troubleshooting ........................................................................................2-1
2.2.1 Installation ..........................................................................................2-1
2.2.2 Start up Procedure .............................................................................2-2
2.2.3 Measurement......................................................................................2-2
2.3 External Equipment...................................................................................2-6
Section 3
Main Functions ..................................................................................... 3-1
3.1 Analog Input Signal...................................................................................3-1
3.1.1 Analog Input Channel A......................................................................3-2
3.1.2 Analog Input Channel B......................................................................3-3
3.1.3 Analog Input Channel C .....................................................................3-3
3.1.4 Analog Input Channel D .....................................................................3-4
3.2 ADC Clock Input Signal ............................................................................3-4
3.3 Control of ADC Settings............................................................................3-5
3.4 ADC Junction Temperature Monitoring.....................................................3-5
3.5 ADC Current Consumption Monitoring .....................................................3-6
3.6 ADC SYNC Signal ....................................................................................3-7
3.7 DC/DC Converter ......................................................................................3-7
Section 4
Software Tools...................................................................................... 4-1
4.1 Overview ...................................................................................................4-1
4.2 Configuration.............................................................................................4-2
4.3 User Interface Installation .........................................................................4-2
4.4 USB Driver Installation..............................................................................4-8
4.5 Operating Modes ....................................................................................4-13
4.5.1 Settings.............................................................................................4-15
4.5.2 TEST ................................................................................................4-19

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4.5.3 Input Impedance...............................................................................4-22
4.5.4 CLOCK .............................................................................................4-24
4.5.5 Power ...............................................................................................4-25
4.5.6 Acquisition Control............................................................................4-26
4.5.7 Acquisition ........................................................................................4-28
4.5.8 Demo Kit Configuration File..............................................................4-34
4.5.9 Data Save File ..................................................................................4-35
4.5.10 Regional and Language Options ......................................................4-36
Section 5
FPGA CODE......................................................................................... 5-1
5.1 Software Configuration .............................................................................5-1
5.2 FPGA Binary File ......................................................................................5-1
5.3 FPGA Programming..................................................................................5-2
5.4 VHDL CODE .............................................................................................5-5
Section 6
Demo kit Hardware Configuration......................................................... 6-1
6.1 Channel D .................................................................................................6-1
6.2 Clock Selection .........................................................................................6-1
6.3 SPI Signal .................................................................................................6-2
6.4 SYNC Signal .............................................................................................6-4
Section 7
Layout Information ................................................................................ 7-1
Section 8
Mechanical Dimensions........................................................................ 8-1
Section 9
Ordering Information............................................................................. 9-1

General Overview
EV10AQ190x-DK - User Guide 1-1
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Section 1
General Overview
The QUAD 10-bit Demo Kit enables the easy evaluation of the characteristics and per-
formance of QUAD 10-bit ADC EV10AQ190x. The Demo kit is plug_and_play and
needs little external equipment.
The Demo kit is delivered with software which allows acquisition of data using the
FPGA.
The QUAD 10-bit Demo Kit is compatible with VITA57 FMC (FPGA Mezzanine Card)
standard.
For more information please see the VITA site web.
http://www.vita.com/fmc.html
The QUAD 10-bit Demo kit is 100% compatible with XILINX VIRTEX 6 evaluation kit
ML605.
This board is designed for use as a reference design.
All front end devices are fitted including: DC-DC regulator, ADC driver, clock
generator….
Please see Section 3 “Main Functions” .
The FPGA VHDL data acquisition code for the ML605 board is supplied.
Please see Section 5 “FPGA CODE” .
1.1 Disclaimer The information in this document is provided in connection with E2V products.
No license, express or implied, by estoppel or otherwise, to any intellectual property
right is granted by this document or in connection with the sale of E2V products.
EXCEPT AS SET FORTH IN E2V'S TERMS AND CONDITIONS OF SALE LOCATED
ON E2V'S WEB SITE, E2V ASSUMES NO LIABILITY WHATSOEVER AND DIS-
CLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS
PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-
INFRINGEMENT. IN NO EVENT SHALL E2V BE LIABLE FOR ANY DIRECT, INDI-
RECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES
(INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSI-
NESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE
OR INABILITY TO USE THIS DOCUMENT, EVEN IF E2V HAS BEEN ADVISED OF
THE POSSIBILITY OF SUCH DAMAGES.
E2V makes no representations or warranties with respect to the accuracy or complete-
ness of the contents of this document and reserves the right to make changes to
specifications and product descriptions at any time without notice. E2V does not make
any commitment to update the information.

General Overview
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This kit must be regarded as a tool, not a finished product. It allows the evaluation of
performance of the e2v component, design prototypes and debug software. It CANNOT
be resold as a finished product that must be compliant with local relevant regulations.
Its function is as a development system, demonstrating the performance of e2v semi-
conductors components and not as a final product available on general release.
Since this Development Kit is intended to be used on an industrial workbench and mod-
ified by the user to build his prototypes, NO WARRANTY OF ANY KIND can apply.
NO LIABILITY will be accepted by e2v, whatsoever may arise as a result of the use of
these boards.
All company and/or product names may be tradenames, trademarks and/or registered
trademarks of the respective owner with which they are associated.
1.2 Quad 10-bit ADC The EV10AQ190x-DK Demo Kit is based on e2v EV10AQ190x 1.25 Gsps Quad 10-bit
ADC whose block diagram is given on Section 1-1.
Figure 1-1. EV10AQ190x Quad 10-bit ADC Block Diagram
The EV10AQ190x Quad 10-bit ADC integrates four 10-bit ADC cores which can operate
independently (four-channel mode) or group by two cores (two-channel mode with the
ADCs interleaved two by two) or one-channel mode where all four ADCs are all
interleaved.
All four ADCs are clocked from the same external input clock signal and controlled via
an SPI bus (Serial Peripheral Interface). An analog multiplexer (cross-point switch) is
used to select the analog input depending on the mode the quad ADC is used.
The clock input is common to all four ADCs. This block receives an external 2.5 GHz
clock (maximum frequency) and generates the internal sampling clocks for each ADC
core depending on the mode used. Please refer to latest version of datasheet
EV10AQ190x for more information.
http://www.e2v.com/products-and-services/specialist-semiconductors/broadband-data-
converters/datasheets/
Clock
Buffer
+
selection
+
decimation
+
SDA
LVDS Buffers
T/H
10 bit
1.25 Gsps
ADC core
10 bit
1.25 Gsps
ADC core
10 bit
1.25 Gsps
ADC core
10 bit
1.25 Gsps
ADC core
Analog MUX
(Cross Point Switch)
Serial
Peripheral
Interface
Offset
Gain
2.5 GHz
Clock
LVDS Buffers LVDS Buffers LVDS Buffers
Gain GainGain
T/H T/H T/H
Offset Offset Offset
Phase Phase Phase Phase

General Overview
EV10AQ190x-DK - User Guide 1-3
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1.3 Demo Kit Figure 1-2 provides an overview of system architecture.
Figure 1-2. EV10AQ190x-DK Demo Kit System Architecture (when Connected with a VIRTEX6 Evaluation Kit)
The complete system is built with the e2v demo kit and an FPGA development kit.
e2v Demo kit contains the following items :
Quad 10-bit Demo kit with EV10AQ190CTPY ADC
Cables & Power Supply
– Universal 12V power Adapter & Cables
– USB Cables to communicate with a PC (control of ADC settings and settings
for data acquisition)
4 analog inputs with SMA connectors
1 clock input with SMA connector (if external clock input is programming)
2 SAMTEC MC-HPC-8.5L connectors HPC (High Pin Count) compatible with VITA57
standard for ADC LVDS digital outputs
CD ROM with GUI Software
Note: The ML605 VIRTEX 6 Evaluation kit with XC6VVLX240T-1FFG1156 FPGA is not sup-
plied within the e2v kit and should be purchased separately from Xilinx or its authorised
distributors.
RF generator PC
GUI
control,
acquisition
& analysis
12V supply
adapter
FPGA
(VIRTEX 6)
VITA57 interface
e2v
QUAD 10-bit
4 channels
12V supply
adapter
I/O USB control
A
B
CD
DN
CLK

General Overview
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Figure 1-3. EV10AQ190x-DK Demo Kit Simplified Schematic
Figure 1-4. EV10AQ190x-DK Demo Kit Functional Architecture
Acquisition and formatting of ADC digital output data are done within the FPGA Eval Kit.
Data is then transmitted again to the ADC Demo Kit.
A USB driver on the ADC Demo kit allows for transmission of the data to the computer
that performs the display and processing of ADC output data (FFT).
Software and Graphical User Interface are provided with the Demo Kit.
The provided software operates using Labview RunTime (no license required).
PCDevice
FPGA
Acquisition &
formatting
Driver USB
USB Transport Layer USB
Control &
Events
Acquisition
Processing
Display
USB cable
FX2
USB Transport Layer
ADC

Quick Start
EV10AQ190x-DK - User Guide 2-1
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Section 2
Quick Start
2.1 Operating
Procedure
1. Install the Software as described in section 4 Software Tools.
2. Install the FPGA code into ML605 Xilinx evaluation board (see Section 5.3
“FPGA Programming” )
3. Turn OFF the ML605 Xilinx evaluation board.
4. Fix Heatsink/Fan to the ADC if no external form of ventilation is to be used (see
Section 3.4)
5. Connect the QUAD 10-bit Demo Kit on ML605 Xilinx evaluation board.
6. Connect the power supplies of both evaluation boards.
7. Connect the USB cable.
8. Turn ON power supplies of QUAD 10-bit Demo Kit.
9. Turn ON power supplies of ML605 Xilinx evaluation board.
10. Launch the EvalkitQuadAdc10Bits.exe software.
11. Check if currents are correct (see Section 4.5.5 Power).
12. Select the ADC mode of your ADC (4 channels or 2 channels or 1 channel)
13. Turn the mode ADC test ramp active (see chap Section 4.5.2 TEST).
This sequence is mandatory to allow the synchronization of 4 channels into
FPGA
14. Launch acquisition and check if sample signal is correct.
15. Return to normal mode (Turn OFF Test mode).
16. Connect a RF generator on Analog input.
17. Turn on the RF generator.
18. Launch acquisition (see Section 4.5.7 Acquisition).
2.2 Troubleshooting
2.2.1 Installation Check that you own rights to write in the directory (administrator rights).
Check for the available disk space.
Check that the USB port is free and properly configured.
– QUAD 10-bit connected to USB 2 driver

Quick Start
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Figure 2-1. USB Port Driver Configuration
Warning: this installation is done for one USB connector only. If USB connector is
changed, USB driver need to be re-installed before use.
2.2.2 Start up Procedure Check that supplies are properly powered on and properly connected.
Check if the Xilinx FPGA evaluation board ML605 is properly configured with correct
software.
Check if QUAD 10-bit Demo Kit is properly plugged into FPGA connector.
Check if USB connector is properly plugged.
2.2.3 Measurement Check if QUAD 10-bit ADC is properly configured in normal mode without standby
and test mode.
Note: check if currents are correct (see Section 4.5.5 Power)
Note: check if test mode is OFF (see Section 4.5.2 TEST)
Check if acquisition mode is correctly configured.
Warning: if no windowing is used or if signal is non coherent, FFT of Figure 6 is
obtained

Quick Start
EV10AQ190x-DK - User Guide 2-3
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Figure 2-2. FFT without Windowing or with non Coherent Signal
Figure 2-3. FFT with Windowing
Warning: if the Fin frequency has an exact value such as 250 MHz the FTT result is
wrong that is why it is recommended to perform measurements with shift of few MHz
e.g. 250.2 MHz.

Quick Start
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Figure 2-4. Example of Wrong INL Measurement if Incorrect Fin such as Exactly
250 MHz
With channel A and channel C (amplifier channels) an RF attenuator should be added
on the SMA connecter to have optimum performance. When these channels are not
being used the attenuator or 50 Ohm terminator should be kept in place. This will
prevent the amplifiers from adding noise into the system.
Figure 2-5. RF Attenuator Added on SMA Connector
Check that the junction temperature of QUAD 10-bit ADC is lower than 105°C and
that heatsink is properly connected.
Figure 2-6. Junction Temperature Monitoring with GUII

Quick Start
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Check if acquisition is synchronous.
The ADC RAMP test procedure will set the ADC to output a ramp on each channel
these ramps are synchronous at the output of the ADC after a SYNC process has been
completed.
The FPGA RESET done during this procedure will always ensure that the 4 channels
are acquired in the FPGA synchronously.
However if the channels are found not to be synchronous as shown in Figure 2-7.
Figure 2-7. Non Synchronous Channels
Return to ADC test mode disable -> Apply and then return into ADC test mode ramp
mode -> Apply.
This will re-run the synchronization procedure of the ADC and FPGA..
Note: it is not always necessary to have the ramp patterns aligned to obtain correct data acqui-
sition using the analog inputs.

Quick Start
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Figure 2-8. Synchronous Channels
Note: it is not always necessary to have the ramp patterns aligned to obtain correct data acqui-
sition using the analog inputs. Even if the ramp mode is not synchronous, you could
return to the normal mode and perform one acquisition. Normally the acquisition of sinus
wave in normal mode is correct.
2.3 External
Equipment
The QUAD 10-bit Demo Kit needs very little external hardware.
RF generator for Analog input signal
– The QUAD 10-bit ADC can convert analog signals up to 2GHz
– For optimum performance this generator must have a low phase noise
Please see Table 2-1 for example of signal generator.
Cables & Power Supply (provided by e2v)
– Universal 12V power Adapter & Cables
– USB Cables to communicate with a PC (control of ADC settings and settings
for data acquisition)
PC with Windows
– Windows 2000/98/XP and Windows NT and Windows 7 (note 32bit only)
Please see chap 4.1 Overview
FPGA evaluation board compatible with VITA57 FMC standard
– This Demo Kit board has been specially designed to be plugged with the
XILINX VIRTEX 6 evaluation board EK-V6-ML605-G.
The QUAD 10-bit Demo Kit could be used with other FPGA evaluation boards
compatible with VITA57 FMC standard. However, an assessment of available
connections should be made to ensure full compatibility.

Quick Start
EV10AQ190x-DK - User Guide 2-7
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Option
RF generator for clock input signal whose frequency is different than 2 GHz
– The QUAD 10-bit Demo Kit provides clock signal at 2 GHz using its own PLL
– The QUAD 10-bit Demo Kit could be tested with other clock frequency
Please see Section 6.2 Clock selection
Table 2-1. Example of RF Generator
Signal Generator SSB Phase Noise @ 1 GHz (20 KHz Offset)
Agilent E4424B 250KHz 2GHz (High spectral
purity)
< -134dBc/Hz
Agilent E4426B 250KHz 4GHz (High spectral
purity)
< -134dBc/Hz
SMA100A 9 KHz 6GHz (High spectral purity) < -140dBc/Hz

Quick Start
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Main Functions
EV10AQ190x-DK - User Guide 3-1
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Section 3
Main Functions
3.1 Analog Input
Signal
The user only needs to provide an analog signal at the input.
This signal is digitized by the ADC depending on the chosen operating mode:
4 channel mode (1 channel per ADC core)
2 channel mode (2 interleaved ADC cores)
1 channel mode (4 interleaved ADC cores)
Each channel input is driven in different ways on the board:
Single to Differential Amplifier from Analog Devices (A channel: ADA4960 D.C.
coupled)
Single to Differential Balun RF transformer (B channel:MACOM ETC1-1-13)
Single to Differential Amplifier from Analog Devices (C channel: ADA4960- AC
coupled)
Direct input via SMA connector (D channel) (free for customer use)

Main Functions
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Figure 3-1. Analog Input SMA Configuration
3.1.1 Analog Input
Channel A
The Analog input channel A uses a differential amplifier (ADC driver) from Analog
Devices ref: ADA4960.
Figure 3-2. Channel A : Schematic
A channel B channel C channel D channel Ext Clock

Main Functions
EV10AQ190x-DK - User Guide 3-3
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The ADA4960 is used in DC configuration with output common mode driven by ADC
QUAD 10-bit. The input is biased at 2.5V since this is a requirement for best perfor-
mance from the amplifier, this should be taken into account when using this input.
Note: be careful that if a DC voltage is added after the RF generator output that this will not
damage the generator.
The ADA4960 is used in AC configuration in channel C.
3.1.2 Analog Input
Channel B
The Analog input channel B uses an RF Transformer from MACOM ref: ETC1-1-13 /
MABA-007159
Figure 3-3. Channel B : Schematic
3.1.3 Analog Input
Channel C
The Analog input channel C uses a differential amplifier (ADC driver) from Analog
Devices: ref: ADA4960-1.
Figure 3-4. Channel C : Schematic
The ADA4960-1 is used in AC configuration with output common mode driven by Quad
10-bit ADC.

Main Functions
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3.1.4 Analog Input
Channel D
This channel is free for customer use in differential and AC coupling configuration.
Figure 3-5. Channel D : Schematic
This Channel D could be used in DC configuration. Please see Section 6.1Channel D.
3.2 ADC Clock Input
Signal
ADC clock input is generated by Clock generated PLL Hititte HMC831 (on-board) at 2.0
GHz. This frequency is fixed.
Figure 3-6. ADC Clock Input : Schematic
Note: By default, the on-board PLL clock is selected but an external clock input (pro-
vided by a RF generator) is allowed.
The clock signal is fed to the board via an SMA connector followed by Single to Differen-
tial Balun RF transformer (MABA-007159 MACOM).
Note: for operation at different clock frequencies it is probable that the FPGA interface
will need to be re-compiled using different timing constraints.
Please see Section 6.2 Clock selection.