EastRising Technology ER-OLED0.91-1 User manual

EASTRISINGTECHNOLOGYCO.,LIMITED
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ER-OLED0 .91-1
OLED Module User Manual
EastRising TechnologyCo., Limited
URL: www.lcd-china.com Document Name: Manual i
ER-OLED0.91-1

C
Con nte en nt ts s
1
1. . B Ba as sic S Sp pe ec cif
fi ic ca at ti io on ns ..................................................................................1~6
1.1 Display Specifications .................................................................................................1
1.2 Mechanical
Specifications...........................................................................................1
1.3 Active Area & Pixel Construction ...............................................................................1
1.4 Mechanical Drawing....................................................................................................2
1.5 Pin Definition...............................................................................................................3
1.6 Block Diagram.............................................................................................................5
1.6.1 VCC Supplied Externally....................................................................................5
1.6.2 VCC Generated by Internal DC/DC Circuit........................................................6
2
2. . A Ab bs solut te e M Ma ax xi im mu um m R Ratin
ng gs s.......................................................................... 7
3
3. . O Op pt ti ic cs s & & E El le ec ct tr ri ic ca al l C Ch ha ar ra ac ct te er ri is st ti ic cs s. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .8 8~ ~9 9
3.1 Optics Characteristics . .............. ..... ....... .... .... ... . ...... ...... ......... ....... .. ...... ...8
3.2 DC Characteristics...... .............. ..... ........ . .. .............. .. ...... ......... ...... .. ..... ...8
3.3 AC Characteristics.... .... .......... .... ...... .... .. ......... ...... ......... ...... .... ...... .... .9
4
4. . F Fu un nc ct ti io on na al l S Sp pe ec ci if fi ic ca at ti io on n ....................................................................... 10~11
4.1 Commands .................................. . ..... ....................................................................10
4.2 Power down and Power up Sequence........................................................................10
4.2.1 Power up Sequence......... ................................................................................10
4.2.2 Power down Sequence.....................................................................................10
4.3 Reset Circuit......... .... ...............................................................................................10
4.4 Actual Application Example......................................................................................11
5
5. . R Re el li ia ab bi il li it ty...................................................................................................... 12
5.1 Contents of Reliability Tests......................................................................................12
5.2 Lifetime......................................................................................................................12
5.3 Failure Check Standard..............................................................................................12
6
6. . O Ou utgoing
g Qu uality y C Cont tr ro ol l Speci ific catio on ns s..............................................13~17
6.1 Environment Required...............................................................................................13
6.2 Sampling
Plan............................................................................................................13
6.3 Criteria & Acceptable Quality Level .........................................................................13
6.3.1 Cosmetic Check (Display Off) in Non-ActiveArea........................................13
6.3.2 Cosmetic Check (Display Off) inActive Area.................................................16
6.3.3 Pattern Check (Display On) in Active Area.....................................................17
7
7. . P Pa ac ck ka ag ge e S Sp pe ec ci if fi ic ca at ti io on ns s ................................................................................ 18
8
8. . P Pr reca au utions
s W Whe en U Us si in ng g T Th hes se e O OE EL D Di is spla ay y M Modul le es.......................19~21
8.1 Handling Precautions.................................................................................................19
8.2 Storage Precautions....................................................................................................20
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ER-OLED0.91-1

8.3 Designing Precautions ...............................................................................................20
8.4 Precautions when disposing of the OEL display modules.........................................21
8.5 Other Precautions.......................................................................................................21
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ER-OLED0.91-1

1
1. B Basi ic c Speci
if fications s
1.1 Display Specifications
1) Display Mode: Passive Matrix
2) Display Color: Monochrome (White)
3) Drive Duty: 1/32 Duty
1.2 Mechanical Specifications
1) Outline Drawing: According to the annexed outline drawing
2) Number of Pixels: 128 ×32
3) Panel Size: 30.0 ×11.50 ×1.45 (mm)
4) Active Area: 22.384 ×5.584 (mm)
5) Pixel Pitch: 0.175 ×0.175 (mm)
6) Pixel Size: 0.159 ×0.159 (mm)
7) Weight: 1.05 (g)
1 3 Active Area & Pixel Const uction
P0.175x128 0.016=22.384
P0.175x32-0.016=5.584
0.159
0.175
0.159
0.175
"A"
Detail "A"
Scale (10:1)
Segment 0
( Column 128 )
Common 31
( Row 1 )
Common 0
( Row 32 )
Segment 127
( Column 1 )
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ER-OLED0.91-1

1.4 Mechanical Drawing
Ting-Kuo Hu
20090511
Ivy Lo
20090511 Cherry Lin
20090511
20090511
2-
φ
0 8±0 1
CS#
D/C#
15
15
20090511
0 1±0 03
Contact Side Contact Side
Notes:
1 Color: White
2 Driver IC: SSD1306
3 FPC Number:ER-OLED0 91-1
4 Interface: 4-wire SPI
5 General Tolerance: ±0 30
6 The total thickness (1 55 Max) is without polarizer protective film & remove tape
The actual assembled total thickness with above materials should be 1 80 Max
Active Area 0 91"
128 x32 Pixels
3M#1318B
8 4x8x0 063mm
R
B
P
(Reference Mechnical Design)
(31 6)
(1 61)
(0 86)
Polarizer
t=0 2mm Remove Tape
t=0 15mm Max
15 3
5 8±0 2
0 9
The drawing contained herein is the exclusive property of EastRising It is not allowed to copy, reproduce and or disclose in any formats without permission of EastRising
±0 3
mm
Unless Otherwise S cifi
Unit
To rance
Ang e
Dimension
General Roughness
Tit
Date
By Drawn
Drawing Number
1 of 1
Sheet
Material
Panel / EE E
1:1
Scale A3
Size
DateItem Remark
Rev
Soda Lime / Polyimide
Customer Approval
Signature
±1
A
Humphrey Lin
AOriginal Drawing
P M
"A"
Detail "A"
Scale (10:1)
Segment 0
( Column 128 )
Common 31
( Row 1 )
Common 0
( Row 32)
Segment 127
( Column 1 )
8
VCC
IREF
SDIN
Symbol
RES#
VDD
VSS
SCLK
2 5 7 6 4
3
1
Pin
VCOMH
9
10 12 14
13
11
VBAT
C1P
C1N
C2P
C2N
P0.65x -1) 9.1±0.05
W=0 35 0 0
11 25±0 2
22 384 (A/A) 24 384 (V/A)
25 9 (Polarizer)
26 6±0 2 (Cap Size)
30±0 2 (Panel Size)
(2 1)
(1 1)
0 35±0 3
5.584 (A/A)
7 584 (V/A)
8 8 (Polarizer)
11 5±0 2 (Cap Size)
11 5±0 2 (Panel Size)
(2 1)
(1 1)
0 5±0 5
(1 6)(16 99)
16 3±0 3
18±03
1 45±0 1
0 1±0 03
(46 3)
1
(0 125)
Glue
5±0 310±0 3
8±0 3
6 8
9 25±0 1
P0 175x128-0 016=22 384
P0 175x32-0 016=5 584
0 159
0 175
0 159
0175
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ER-OLED0.91-1
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ER-OLED0.91-1

1.5 Pin Definition
Pin Number Symbol Type Function
P
Po ow we er r S Su up pp pl ly y
7 VDD P
Power
Supply for Logic
This is a voltage supply pin. It must be connected to
external source.
6 VSS P
G
Gr ro ou un nd d o of f O OE EL L S Sy ys st te em m
This is a ground pin. It also acts as a reference for the
logic pins, the OEL driving voltages, and the analog
circuits. It must be connected to external ground.
15 VCC P
P
Po ow we er S Su up pp pl ly
f fo or r O OEL L P Panel l
This is the most positive voltage supply pin of the chip.
A stabilization capacitor should be connected
b
etwee
n
this pin and VSS when the converter is used. It must be
connected to external source when the converter is no
t
used.
Driver
13 IREF I
C
Cu ur rr re en nt t R Re ef fe er re en nc ce e f fo or r B Br ri ig gh ht tn ne es ss s A Ad dj ju us st tm me en nt t
This pin is segment current reference pin. A resisto
r
should be connected between this pin and VSS. Set the
current lower than 12 5μA
14 VCOMH O
Voltage
Output High Level for COM Signal
This pin is the input pin for the voltage output high level
for COM signals. A capacitor should be connecte
d
between this pin and VSS.
DC/DC Converte
er
5 VBAT P
P
Po ow we er r S Su up pp pl ly y f fo or r D DC C/ /D DC C C Co on nv ve er rt te er r C Ci ir rc cu ui it t
This is the power supply pin for the internal buffer of the
DC/DC voltage converter. It must be connected to
external source when the converter is used. It should be
connected to VDD when the converter is not used.
3 / 4
1 / 2 C1P / C1N C2P / C2N I
Positive
Terminal of the Flying Inverting Capacitor
N
Ne eg ga at ti iv ve e T Te er rm mi in na al l o of f t th he e F Fl ly yi in ng g B Bo oo os st t C Ca ap pa ac ci it to or r
The charge-pump capacitors are required between the
terminals. They must be floated when the converter is
not used.
I
In nt te er rf fa ac ce e
9 RES# I
Power
Res set for Controller and Driver
This pin is reset signal input. When the pin is low,
initialization of the chip is executed.
8 CS# I
C
Ch hi ip p S Se el le ec ct t
This pin is the chip select input. The chip is enabled fo
r
MCU communication only when CS# is pulled low.
10 D/C# I
D
Da at ta a/ /C Co om mm ma an nd d C Co on nt tr ro ol l
This pin is Data/Command control pin. When the pin is
p
ulled high and serial interface mode is selected, the dat
a
at SDIN is treated as data. When it is pulled low, the
data at SDIN will be transferred to the command register.
For detail relationship to MCU interface signals, please
refer to the Timing Characteristics Diagrams.
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1.5 Pin Definition (Continued)
Pin Number Symbol Type Function
Int terface
( (C Co on nti inu ued d) )
11 SCLK I
S
Se er ri ia al l Clo oc ck k Input S Si ig gn na al l
The transmission if information in the bus is following
a
clock signal. Each transmission of data bit is take
n
place during a single clock period of this pin.
12 SDIN I
S
Se er ri ia al l Da at ta
Input S Si ig gn na al l
This pin acts as a communication channel. The inpu
t
data through SDIN are latched at the rising edge of SCL
K
in the sequence of MSB first and converted to 8-
b
i
t
p
arallel data and handled at the rising edge of last serial
clock.
SDIN is identified to display data or command by D/C#
bit data at the rising of first SCLK.
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1.6 Block Diagram
1.6.1 VCC Supplied Externally
Segment 127 Segment 0
Common 0 Common 31
~~~ ~
IREF
VCOMH VDD
RES#
VSS
SSD1306
C1
VCC VBAT
C3
C1P C1N
C2N C2P
Active Area 0.91"
128 x32 Pixels
D/C#
SDIN SCLK
CS#
C2
Pins connected to MCU interface: CS#, RES#, D/C#, SCLK, and SDIN
C1: 1μF
C2, C3: 2.2μF
R1: 390kΩ, R1 = (Voltage at IREF – VSS) / IREF
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1.6.2 VCC Generated by Internal DC/DC Circuit
Segment 127 Segment 0
Common 0
Common 31
~~~ ~
IREF
VCOMH VDD
R1
RES#
C2
VSS
SSD1306
C1
VCC VBAT
C4
C3
C5
C6
C1P C1N C2N C2P
D/C#
CS#
SCLK SDIN
Active Area 0.91"
128 x32 Pixels
Pins connected to MCU interface: CS#, RES#, D/C# SCLK, and SDIN
C1, C2, C5, C6: 1μF
C3, C4: 2.2μF
R1: 390kΩ, R1 = (Voltage at IREF – VSS) / IREF
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2
2. . A Ab bs so ol lu ut te e M Ma ax xi im mu um m R Ra at ti in ng gs s
Parameter Symbol Min Max
Unit Notes
Supply Voltage for Logic VDD -0.3 4 V 1, 2
Supply Voltage for Display VCC 0 11 V 1,
2
Operating Temperature TOP -30 70
°C -
Storage Temperature TSTG -40 80 °C -
Note 1: All the above voltages are on the basis of “VSS = 0V”.
Note 2: When this module is used beyond the above absolute maximum ratings,
permanent breakage of the module may occur. Also, for normal operations, it is
desirable to use this module under the conditions according to Section 3.
“Optics & Electrical Characteristics”. If this module is used beyond these
conditions, malfunctioning of the module can occur and the reliability of the
module may deteriorate.
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