EastRising Technology ER-OLED0.91-1 User manual

EASTRISINGTECHNOLOGYCO.,LIMITED
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ER-OLED0 .91-1
OLED Module User Manual
EastRising TechnologyCo., Limited
URL: www.lcd-china.com Document Name: Manual i
ER-OLED0.91-1

C
Con nte en nt ts s
1
1. . B Ba as sic S Sp pe ec cif
fi ic ca at ti io on ns ..................................................................................1~6
1.1 Display Specifications .................................................................................................1
1.2 Mechanical
Specifications...........................................................................................1
1.3 Active Area & Pixel Construction ...............................................................................1
1.4 Mechanical Drawing....................................................................................................2
1.5 Pin Definition...............................................................................................................3
1.6 Block Diagram.............................................................................................................5
1.6.1 VCC Supplied Externally....................................................................................5
1.6.2 VCC Generated by Internal DC/DC Circuit........................................................6
2
2. . A Ab bs solut te e M Ma ax xi im mu um m R Ratin
ng gs s.......................................................................... 7
3
3. . O Op pt ti ic cs s & & E El le ec ct tr ri ic ca al l C Ch ha ar ra ac ct te er ri is st ti ic cs s. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .8 8~ ~9 9
3.1 Optics Characteristics . .............. ..... ....... .... .... ... . ...... ...... ......... ....... .. ...... ...8
3.2 DC Characteristics...... .............. ..... ........ . .. .............. .. ...... ......... ...... .. ..... ...8
3.3 AC Characteristics.... .... .......... .... ...... .... .. ......... ...... ......... ...... .... ...... .... .9
4
4. . F Fu un nc ct ti io on na al l S Sp pe ec ci if fi ic ca at ti io on n ....................................................................... 10~11
4.1 Commands .................................. . ..... ....................................................................10
4.2 Power down and Power up Sequence........................................................................10
4.2.1 Power up Sequence......... ................................................................................10
4.2.2 Power down Sequence.....................................................................................10
4.3 Reset Circuit......... .... ...............................................................................................10
4.4 Actual Application Example......................................................................................11
5
5. . R Re el li ia ab bi il li it ty...................................................................................................... 12
5.1 Contents of Reliability Tests......................................................................................12
5.2 Lifetime......................................................................................................................12
5.3 Failure Check Standard..............................................................................................12
6
6. . O Ou utgoing
g Qu uality y C Cont tr ro ol l Speci ific catio on ns s..............................................13~17
6.1 Environment Required...............................................................................................13
6.2 Sampling
Plan............................................................................................................13
6.3 Criteria & Acceptable Quality Level .........................................................................13
6.3.1 Cosmetic Check (Display Off) in Non-ActiveArea........................................13
6.3.2 Cosmetic Check (Display Off) inActive Area.................................................16
6.3.3 Pattern Check (Display On) in Active Area.....................................................17
7
7. . P Pa ac ck ka ag ge e S Sp pe ec ci if fi ic ca at ti io on ns s ................................................................................ 18
8
8. . P Pr reca au utions
s W Whe en U Us si in ng g T Th hes se e O OE EL D Di is spla ay y M Modul le es.......................19~21
8.1 Handling Precautions.................................................................................................19
8.2 Storage Precautions....................................................................................................20
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8.3 Designing Precautions ...............................................................................................20
8.4 Precautions when disposing of the OEL display modules.........................................21
8.5 Other Precautions.......................................................................................................21
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ER-OLED0.91-1

1
1. B Basi ic c Speci
if fications s
1.1 Display Specifications
1) Display Mode: Passive Matrix
2) Display Color: Monochrome (White)
3) Drive Duty: 1/32 Duty
1.2 Mechanical Specifications
1) Outline Drawing: According to the annexed outline drawing
2) Number of Pixels: 128 ×32
3) Panel Size: 30.0 ×11.50 ×1.45 (mm)
4) Active Area: 22.384 ×5.584 (mm)
5) Pixel Pitch: 0.175 ×0.175 (mm)
6) Pixel Size: 0.159 ×0.159 (mm)
7) Weight: 1.05 (g)
1 3 Active Area & Pixel Const uction
P0.175x128 0.016=22.384
P0.175x32-0.016=5.584
0.159
0.175
0.159
0.175
"A"
Detail "A"
Scale (10:1)
Segment 0
( Column 128 )
Common 31
( Row 1 )
Common 0
( Row 32 )
Segment 127
( Column 1 )
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1.4 Mechanical Drawing
Ting-Kuo Hu
20090511
Ivy Lo
20090511 Cherry Lin
20090511
20090511
2-
φ
0 8±0 1
CS#
D/C#
15
15
20090511
0 1±0 03
Contact Side Contact Side
Notes:
1 Color: White
2 Driver IC: SSD1306
3 FPC Number:ER-OLED0 91-1
4 Interface: 4-wire SPI
5 General Tolerance: ±0 30
6 The total thickness (1 55 Max) is without polarizer protective film & remove tape
The actual assembled total thickness with above materials should be 1 80 Max
Active Area 0 91"
128 x32 Pixels
3M#1318B
8 4x8x0 063mm
R
B
P
(Reference Mechnical Design)
(31 6)
(1 61)
(0 86)
Polarizer
t=0 2mm Remove Tape
t=0 15mm Max
15 3
5 8±0 2
0 9
The drawing contained herein is the exclusive property of EastRising It is not allowed to copy, reproduce and or disclose in any formats without permission of EastRising
±0 3
mm
Unless Otherwise S cifi
Unit
To rance
Ang e
Dimension
General Roughness
Tit
Date
By Drawn
Drawing Number
1 of 1
Sheet
Material
Panel / EE E
1:1
Scale A3
Size
DateItem Remark
Rev
Soda Lime / Polyimide
Customer Approval
Signature
±1
A
Humphrey Lin
AOriginal Drawing
P M
"A"
Detail "A"
Scale (10:1)
Segment 0
( Column 128 )
Common 31
( Row 1 )
Common 0
( Row 32)
Segment 127
( Column 1 )
8
VCC
IREF
SDIN
Symbol
RES#
VDD
VSS
SCLK
2 5 7 6 4
3
1
Pin
VCOMH
9
10 12 14
13
11
VBAT
C1P
C1N
C2P
C2N
P0.65x -1) 9.1±0.05
W=0 35 0 0
11 25±0 2
22 384 (A/A) 24 384 (V/A)
25 9 (Polarizer)
26 6±0 2 (Cap Size)
30±0 2 (Panel Size)
(2 1)
(1 1)
0 35±0 3
5.584 (A/A)
7 584 (V/A)
8 8 (Polarizer)
11 5±0 2 (Cap Size)
11 5±0 2 (Panel Size)
(2 1)
(1 1)
0 5±0 5
(1 6)(16 99)
16 3±0 3
18±03
1 45±0 1
0 1±0 03
(46 3)
1
(0 125)
Glue
5±0 310±0 3
8±0 3
6 8
9 25±0 1
P0 175x128-0 016=22 384
P0 175x32-0 016=5 584
0 159
0 175
0 159
0175
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ER-OLED0.91-1

1.5 Pin Definition
Pin Number Symbol Type Function
P
Po ow we er r S Su up pp pl ly y
7 VDD P
Power
Supply for Logic
This is a voltage supply pin. It must be connected to
external source.
6 VSS P
G
Gr ro ou un nd d o of f O OE EL L S Sy ys st te em m
This is a ground pin. It also acts as a reference for the
logic pins, the OEL driving voltages, and the analog
circuits. It must be connected to external ground.
15 VCC P
P
Po ow we er S Su up pp pl ly
f fo or r O OEL L P Panel l
This is the most positive voltage supply pin of the chip.
A stabilization capacitor should be connected
b
etwee
n
this pin and VSS when the converter is used. It must be
connected to external source when the converter is no
t
used.
Driver
13 IREF I
C
Cu ur rr re en nt t R Re ef fe er re en nc ce e f fo or r B Br ri ig gh ht tn ne es ss s A Ad dj ju us st tm me en nt t
This pin is segment current reference pin. A resisto
r
should be connected between this pin and VSS. Set the
current lower than 12 5μA
14 VCOMH O
Voltage
Output High Level for COM Signal
This pin is the input pin for the voltage output high level
for COM signals. A capacitor should be connecte
d
between this pin and VSS.
DC/DC Converte
er
5 VBAT P
P
Po ow we er r S Su up pp pl ly y f fo or r D DC C/ /D DC C C Co on nv ve er rt te er r C Ci ir rc cu ui it t
This is the power supply pin for the internal buffer of the
DC/DC voltage converter. It must be connected to
external source when the converter is used. It should be
connected to VDD when the converter is not used.
3 / 4
1 / 2 C1P / C1N C2P / C2N I
Positive
Terminal of the Flying Inverting Capacitor
N
Ne eg ga at ti iv ve e T Te er rm mi in na al l o of f t th he e F Fl ly yi in ng g B Bo oo os st t C Ca ap pa ac ci it to or r
The charge-pump capacitors are required between the
terminals. They must be floated when the converter is
not used.
I
In nt te er rf fa ac ce e
9 RES# I
Power
Res set for Controller and Driver
This pin is reset signal input. When the pin is low,
initialization of the chip is executed.
8 CS# I
C
Ch hi ip p S Se el le ec ct t
This pin is the chip select input. The chip is enabled fo
r
MCU communication only when CS# is pulled low.
10 D/C# I
D
Da at ta a/ /C Co om mm ma an nd d C Co on nt tr ro ol l
This pin is Data/Command control pin. When the pin is
p
ulled high and serial interface mode is selected, the dat
a
at SDIN is treated as data. When it is pulled low, the
data at SDIN will be transferred to the command register.
For detail relationship to MCU interface signals, please
refer to the Timing Characteristics Diagrams.
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1.5 Pin Definition (Continued)
Pin Number Symbol Type Function
Int terface
( (C Co on nti inu ued d) )
11 SCLK I
S
Se er ri ia al l Clo oc ck k Input S Si ig gn na al l
The transmission if information in the bus is following
a
clock signal. Each transmission of data bit is take
n
place during a single clock period of this pin.
12 SDIN I
S
Se er ri ia al l Da at ta
Input S Si ig gn na al l
This pin acts as a communication channel. The inpu
t
data through SDIN are latched at the rising edge of SCL
K
in the sequence of MSB first and converted to 8-
b
i
t
p
arallel data and handled at the rising edge of last serial
clock.
SDIN is identified to display data or command by D/C#
bit data at the rising of first SCLK.
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1.6 Block Diagram
1.6.1 VCC Supplied Externally
Segment 127 Segment 0
Common 0 Common 31
~~~ ~
IREF
VCOMH VDD
RES#
VSS
SSD1306
C1
VCC VBAT
C3
C1P C1N
C2N C2P
Active Area 0.91"
128 x32 Pixels
D/C#
SDIN SCLK
CS#
C2
Pins connected to MCU interface: CS#, RES#, D/C#, SCLK, and SDIN
C1: 1μF
C2, C3: 2.2μF
R1: 390kΩ, R1 = (Voltage at IREF – VSS) / IREF
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1.6.2 VCC Generated by Internal DC/DC Circuit
Segment 127 Segment 0
Common 0
Common 31
~~~ ~
IREF
VCOMH VDD
R1
RES#
C2
VSS
SSD1306
C1
VCC VBAT
C4
C3
C5
C6
C1P C1N C2N C2P
D/C#
CS#
SCLK SDIN
Active Area 0.91"
128 x32 Pixels
Pins connected to MCU interface: CS#, RES#, D/C# SCLK, and SDIN
C1, C2, C5, C6: 1μF
C3, C4: 2.2μF
R1: 390kΩ, R1 = (Voltage at IREF – VSS) / IREF
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2
2. . A Ab bs so ol lu ut te e M Ma ax xi im mu um m R Ra at ti in ng gs s
Parameter Symbol Min Max
Unit Notes
Supply Voltage for Logic VDD -0.3 4 V 1, 2
Supply Voltage for Display VCC 0 11 V 1,
2
Operating Temperature TOP -30 70
°C -
Storage Temperature TSTG -40 80 °C -
Note 1: All the above voltages are on the basis of “VSS = 0V”.
Note 2: When this module is used beyond the above absolute maximum ratings,
permanent breakage of the module may occur. Also, for normal operations, it is
desirable to use this module under the conditions according to Section 3.
“Optics & Electrical Characteristics”. If this module is used beyond these
conditions, malfunctioning of the module can occur and the reliability of the
module may deteriorate.
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3. Optic
cs & E El le ec ctr rica al l C Cha ar ra ac ct te er rist ti ics s
3.1 Optics Characteristics
Characteristics Symbol Conditions Min Typ Max Unit
Brightness Lbr With Polarizer
(Note 3) 120 150 - cd/m2
C.I.E. (White) (x)
(y) Without Polarizer 0.26 0.29 0.32 0.33 0.34 0.37
Dark Room Contrast CR -
>2000:1
-
View Angle >160 - - degree
* Optical measurement taken at VDD = 2.8V, VCC = 7.25V.
Software configuration follows Section 4.4 Initialization.
3.2 DC Characteristics
Characteristics Symbol Conditions Min Typ Max Unit
Supply Voltage for Logic VDD - 1 65 2.8 3.3 V
Supply Voltage for Display
(Supplied Externally) VCC Note 3 7
7.25 7.5 V
Supply Voltage for DC/DC VBAT
Internal DC/DC Enable
3 3 - 4.2 V
Supply Voltage for Display
(Generated by Internal DC/DC)
VCC Note 3 7
7.25 7.5 V
High Level Input VIH -
0.8 × V
DD
- VDD V
Low Level Input VIL - 0 -
0.2 × V
DD
V
High Level Output VOH
I
OUT
= 100 μ A, 3.3MHz 0.9 × V
DD
- VDD V
Low Level Output VOL
I
OUT
= 100 μ A, 3.3MHz
0 -
0.1 × V
DD
V
Operating Current for VDD IDD - - 180
300 μA
Note 4 - 4.3 5.4 mA
Operating Current for VCC
(VCC Supplied Externally) ICC Note 5 - 6.8 8.5 mA
Note 4 - 12.6 15.8 mA
Operating Current for VBAT
(V
CC
Generated by Internal DC/DC)
IBAT Note 5 - 18.4 23.0 mA
Sleep Mode Current for V
DD
IDD, SLEEP - - 1 5 μA
Sleep Mode Current for V
CC
ICC, SLEEP - - 1 5 μA
Note 3: Brightness (Lbr) and Supply Voltage for Display (VCC) are subject to the
change of the panel characteristics and the customer’s request.
Note 4: VDD = 2.8V, VCC = 7.25V, 50% Display Area Turn on.
Note 5: VDD = 2.8V, VCC = 7.25V, 100% Display Area Turn on.
* Software configuration follows Section 4.4 Initialization.
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3.3 AC Characteristics
Symbol Description Min Max Unit
tcycle Clock Cycle Time 100 - ns
tAS Address Setup Time 15 - ns
tAH Address Hold Time 15 - ns
tCSS Chip Select Setup Time 20 - ns
tCSH Chip Select Hold Time 10 - ns
tDSW Write Data Setup Time 15 - ns
tDHW Write Data Hold Time 15 - ns
tCLKL Clock Low Time 20 - ns
tCLKH Clock High Time 20 - ns
tRRise Time - 40 ns
tFFall Time - 40 ns
* (VDD - VSS = 1.65V to 3.3V, Ta= 25°C)
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ER-OLED0.91-1

4
4. . F Func cti io on na al l Sp
pe ecifi ic ca at ti io on n
4.1. Commands
Refer to the Technical Manual for the SSD1306
4.2 Power down and Power up Sequence
To protect OEL panel and extend the panel life time, the driver IC power up/down
routine should include a delay period between high voltage and low voltage power
sources during turn on/off. It gives the OEL panel enough time to complete the
action of charge and discharge before/after the operation.
4.2.1 Power up Sequence:
1. Power up VDD
2. Send Display off command
3. Initialization
4. Clear Screen
5. Power up VCC
6. D lay 100ms
(When VCC is stable)
7. Send D splay on command
4.2.2 Power down Sequence:
1. Send Display off command
2. Power down VCC
3. Delay 100ms
(When VCC is reach 0 and panel
is completely discharges)
4. Power down VDD
4.3 Reset Circuit
When RES# input is low, the chip is initialized with the following status:
1. Display is OFF
2. 128×64 Display Mode
3. Normal segment and display data column and row address mapping (SEG0
mapped to column address 00h and COM0 mapped to row address 00h)
4. Shift register data clear in serial interface
5. Display start line is set at display RAM address 0
6. Column address counter is set at 0
7. Normal scan direction of the COM outputs
8. Contrast control register is set at 7Fh
9. Normal display mode (Equivalent to A4h command)
VDD off
VDD
Display
off
V
C
C
of
f
f
V
SS
/Ground
VCC
D
i
is s
p
play on
VDD
VDD
on
V
C
C
on
V
SS
/Ground
VCC
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4.4 Actual Application Example
Command usage and explanation of an actual example
<Initialization>
* Written Value for Parameters
(1)ÎVCC Supplied Externally
(2) ÎVCC Generated by Internal DC/DC Circuit
If the noise is accidentally occurred at the displaying window during the operation,
please reset the display in order to recover the display function.
* Set Charge Pump
0x8D, 0x10(1) / 0x14(2)
Set Multiplex Ratio
0xA8, 0x1F
Set Display Offset
0xD3, 0x00
Set Display Start Line
0x40
Set Segment Re-Map
0xA1
Set COM Output Scan Direction
0xC8
Set COM Pins Hardware Configuration
0xDA, 0x02
Set C nt ast Contr l
0x81, 0xCF
* Set Pre-Charge Period
0xD9, 0x22(1) / 0xF1(2)
Set VCOMH Deselect Level
0xDB, 0x40
Set Normal/Inverse Display
0xA6
Set Entire Display On/Off
0xA4
Set Display On
0xAF
Clear Screen
Set Display Clock Divide Ratio/Oscillator Frequency
0xD5, 0x80
Set Display Off
0xAE
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ER-OLED0.91-1

5
5. . R Re el li ia ab bi il li it ty y
5.1 Contents of Reliability Tests
Item Conditions Criteria
High Temperature Operation 70°C, 240 hrs
Low Temperature Operation -30°C, 240 hrs
High Temperature Storage 80°C, 240 hrs
Low Temperature Storage -40°C, 240 hrs
High Temperature/Humidity Operation
60°C, 90% RH, 120 hrs
Thermal Shock -40°C ⇔85°C, 24 cycles
60 mins dwell
The operational
functions work.
* The samples used for the above tests do not include polarizer.
* No moisture condensation is observed during tests.
5.2 Lifetime
End of lifetime is specified as 50% of initial brightness reached.
Parameter Min Max Unit Condition Notes
Operating Life Time 10 000 - hr 120 cd/m2, 50% Checkerboard 6
Storage Life Time 20,000 - hr Ta= 25°C, 50% RH -
Note 6: The average operating lifetime at room temperature is estimated by the
accelerated operation at high temperature conditions.
5.3 Failure Check Standard
After the completion of the described reliability test, the samples were left at room
temperature for 2 hrs prior to conducting the failure test at 23±5°C; 55±15% RH.
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6
6. . O Ou ut tg go oi in ng g Q Qu ua al li it ty y C Co on nt tr ro ol l S Sp pe ec ci if fi ic ca at ti io on ns s
6.1 Environment Required
Customer’s test & measurement are required to be conducted under the following
conditions:
Temperature: 23 ±5°C
Humidity: 55 ±15 %RH
Fluorescent Lamp: 30W
Distance between the Panel & Lamp: ≥50 cm
Distance between the Panel & Eyes of the Inspector: ≥30 cm
Finger glove (or finger cover) must be worn by the inspector.
Inspection table or jig must be anti-electrostatic.
6.2 Sampling Plan
Level II, Normal Inspection, Single Sampling, MIL-STD-105E
6.3 Criteria & Acceptable Quality Lev l
Partition AQL Definition
Major 0.65 Defects in Pattern Check (Display On)
Minor 1.0 Defects in Cosmetic Check (Display Off)
6.3.1 Cosmetic Check (Display Off) in Non-ActiveArea
Check Item Classification Criteria
Panel
General Chipping Minor
X > 6 mm (Along with Edge)
Y > 1 mm (Perpendicular to edge)
X
Y
X
Y
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6.3.1 Cosmetic Check (Display Off) in Non-ActiveArea (Continued)
Check Item
Classification Criteria
Panel Crack Minor
Any crack is not allowable.
Cupper Exposed
(Even Pin or Film) Minor Not Allowable by Naked Eye Inspection
Film or Trace Damage Minor
Terminal Lead Twist Minor
Not Allowable
Terminal Lead Broken Minor
Not Allowable
Terminal Lead Prober
Mark Acceptable
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6.3.1 Cosmetic Check (Display Off) in Non-ActiveArea (Continued)
Check Item
Classification Criteria
Minor
NG if any bent lead cause lead
shorting.
Terminal Lead Bent
(Not Twist or Broken)
Minor
NG for horizontally bent lead more
than 50% of its width.
Glue or Contamination
on Pin
(Couldn’t Be Removed
by Alcohol)
Minor
Ink Marking on Back
Side of panel
(Exclude on Film) Acceptable Ignore for Any
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ER-OLED0.91-1

6.3.2 Cosmetic Check (Display Off) inActive Area
Check Item
Classification Criteria
Any Dirt & Scratch on
Polarizer’s Protective Film Acceptable Ignore for not Affect the
Polarizer
Scratches, Fiber, Line-Shape
Defect
(On Polarizer) Minor W ≤0.1 Ignore
W > 0.1, L ≤2 n ≤1
L > 2 n = 0
Dirt, Black Spot, Foreign
Material,
(On Polarizer) Minor Φ≤0.1 Ignore
0.1 <Φ≤0.25 n ≤1
0.25 <Φn = 0
Dent, Bubbles, White spot
(Any Transparent Spot on
Polarizer) Minor
Φ≤0.5
ÎIgnore if no Influence on
Display
0.5 < Φn = 0
Fingerprint, Flow Mark
(On Polarizer) Minor Not Allowable
* Protective film should not be tear off when cosmetic check.
** Definition of W & L & Φ(Unit: mm): Φ= (a + b) / 2
W
L
b
: Minor Axis
a: Major Axis
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6.3.3 Pattern Check (Display On) in Active Area
Check Item Classification Criteria
No Display Major
Flicker Major Not Allowable
Missing Line Major
Pixel Short Major
Darker Pixel Major
Wrong Display Major
Un-uniform Major
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