EMC EM78P451 User manual

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* This specification is subject to be changed without notice. 7.23.2001
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EM78P451
I. GENERAL DESCRIPTION
The EM78P451 is an 8-bit microprocessor with low-power and high-speed CMOS technology. Its operation kernel
is implemented by RISC-like architecture. The one time programmable(OTP) version is flexible no matter on mass
production or engineering test. Users can get any volume with a favorable price. This device is equiped with the
function of Serial Peripheral Interface (SPI) and easy-implemented RS-232. These are very suitable for the wire
communication. Only 57 instructions need learn.This product is supported by EMC in-circuit emulator, macro assembler
and Easy C Compiler.
II. FEATURES
• Operating voltage range: 2.2V~5.5V.
• Available in temperature range: 0°C~70°C.
• Operating frequency range:
Crystal mode: DC~20MHz at 5V, and DC~8MHz at 3V.
RC mode: DC~4MHz at 5V, and DC~4MHz at 3V.
• Serial Peripheral Interface (SPI) available.
• 4K x 13 bits on chip ROM (EM78P451).
• 11 special function registers.
• 140 x 8 bits general-purpose registers (SRAM).
• 5 bi-directional I/O ports (35 I/O pins).
• 3 LED direct sinking pins with internal serial resistors.
• Built-in RC oscillator.
• Built-in power-on reset.
• Five stacks for subroutine and interrupt.
• 8-bit real time clock/counter (TCC) with the overflow interrupt.
• Two machine clocks or four machine clocks per instruction cycle.
• Power-down mode.
• Programmable wake-up from sleep circuit on I/O ports.
• Programmable free running on-chip watchdog timer.
• 12 wake-up pins.
• Two open-drain pins.
• Two R-option pins.
• Package :
(1) 40 pin DIP : EM78P451P. (2) 40 pin SOP : EM78P451M.
(3) 42 pin SHRINK : EM78P451R (4) 44 pin QFP : EM78P451AQ.
• Reloadable counter available.
• Four types of interrupts.
1. Pin changed (/INT).
2. SPI completed.
3. TCC over flow.
4. Reloadable counter match.

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EM78P451
III. PIN ASSIGNMENTS
IV. FUNCTIONAL BLOCK DIAGRAM
V. PIN DESCRIPTION
Table 1 Pin description-EM78P451
Symbol Type Function Description
R-OSCI I In XTAL mode: Crystal input; In RC mode: 56 Kohm±5% pull-high to generate
1.8432MHz.
OSCO O In XTAL mode: Crystal output; In RC mode: Instruction clock output.
P90~P95 I/O Port 9 is a 6-bit bi-directional I/O port.All of its pins can be pulled high individually
in software.
P80~P87 I/O Port 8 is an 8-bit bi-directional I/O port. P80 and P81 are also used as the R-option
Fig. 1 Pin assignments
Fig. 2 Functional block diagram

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EM78P451
Symbol Type Function Description
P70~P72 I/O LED direct-driving pin with internal serial resistor as used to be output. Defined in
software.
CLK I/O By connecting P74 and P76 together. P74 can be pulled high in software. P76 can
be defined as an open-drain output.
DATA I/O By connecting P75 and P77 together. P75 can be pulled high by software. P77 can
be defined as an open-drain output.
P60~P67 I/O Port 6 is an 8-bit bi-directional port.All of its pins can be pulled high individually
in software.
P50~P57 I/O Port 5 is an 8-bit bi-directional I/O port.All of its pins can be pulled high individually
in software.
VDD - Power supply pin.
VSS - Ground pin.
/INT I An interrupt schmitt-triggered pin. The function of interrupt triggers at the falling
edge. Users can enable it by software. The internal pull-up resistor is around 50
Kohm.
SDI I/O Serial data in.
SDO I/O Serial data out.
SCK I/O Serial clock.
/SS I/O /Slave select.
VI. FUNCTION DESCRIPTION
VI.1 Operational Registers
1. R0 (IndirectAddressing Register)
R0 is not a physically implemented register. It is employed as an indirect addressing pointer.Any instruction using R0 as
a register actually accesses the data pointed by the RAM Select Register (R4).
2. R1 (TCC)
•Increased by the instruction cycle clock.
•Written and read by any instruction as any other register.
3. R2 (Program Counter) & Stack
•R2 and the hardware stacks are 12 bits wide.
•The structure is depicted in Fig. 3.
•Generating 4096 x 13 bits on-chip OTP ROM addresses to the relative programming instruction codes. One program
page is 1024 words long.
•All the bits of R2 are set "1"s as a RESET condition occurs.
•"JMP" instruction allows the direct loading of the lower 10 program counter bits. Thus, "JMP" allows jump to
any location on one page.

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EM78P451
•"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine
entry address can be any location on one page.
•"RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top of stack.
•"MOV R2,A" allows the loading of an address from the "A" register to the lower 8 bits of PC, and the ninth and
tenth bits (A8~A9) of PC are cleared.
•"ADD R2,A" allows a relative address to be added to the current PC, and the ninth and tenth bits of PC are
cleared.
•Any instruction which would change the contents of R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6", ......)
(except "TBL") will cause the ninth and tenth bits (A8~A9) of PC to be cleared. Thus, the computed jump is
limited to the first 256 locations of any program page.
•"TBL" allows a relative address to be added to the current PC (R2+A→R2), and contents of the ninth and tenth
bits (A8~A9) of PC are not changed. Thus, the computed jump can be on the second (or third, 4th) 256
locations on one program page.
•In the case of EM78P451, the two most significant bits (A10 and A11) will be loaded with the contents of
bits PS0~PS1 in the status register (R3) upon the execution of a "JMP", "CALL", or any instructions which
would change the contents of R2.
Fig. 3 Program counter organization
4. R3 (Status Register)
7654321 0
GP PS1 PS0 T P Z DC C

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EM78P451
•Bit 0 (C) Carry flag
•Bit 1 (DC) Auxiliary carry flag
•Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.
•Bit 3 (P) Power-down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP"
command.
•Bit 4 (T) Time-out bit. Set to 1 by the "SLEP" command and the "WDTC" command, or during power-up and
reset to 0 by WDT time-out.
•Bits 5 (PS0) ~ 6 (PS1) Page-selecting bits. PS0~PS1 are used to select a program memory page. When executing
"JMP", "CALL", or other instructions which cause the program counter to be changed (e.g. MOV R2,A), PS0~PS1
are loaded to the 11th and 12th bits of the program counter which would select one of the available program
memory pages. Note that RET, RETLand RETI instructions do not change the PS0~PS1 bits. That is, the return will
be always to the page from the place where the subroutine was called, regardless of the current setting of PS0~PS1
bits.
PS1 PS0 Program memory page [Address]
0 0 Page 0 [000-3FF]
0 1 Page 1 [400-7FF]
1 0 Page 2 [800-BFF]
1 1 Page 3 [C00-FFF]
•Bit 7 (GP) General read/write bit.
5. R4 (RAM Select Register)
•Bits 0~5 are used to select the registers (address: 00~3F) in the indirect addressing mode.
•Bits 6~7 determine which bank is activated among the 4 banks.
•If no indirect addressing is used, the RSR can be employed as an 8-bit general-purpose read/write register.
•See the configuration of the data memory in Fig. 4.
6. R5~R8 (Port 5 ~ Port8)
•Four I/O registers
•Both P74 and P76 can read or write data from the DATA pin, and both P75 and P77 can read or write data from
the CLK pin .
7. R9 (Port9)
•A 6-bit I/O register. The contents of the upper two most significant bits are read as "0".
8. RA~RF
•Refer to VI.5 Serial Peripheral Interface mode and VI.6 Timer1 .
9. R10~R3E (General-purpose Register)
•R10~R1F and R20~R3E (including Banks 0~3) are general-purpose registers.

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EM78P451
10. R3F (Interrupt Status Register)
7654321 0
- - - - TM1IF RBFIF EXIF TCIF
•Bit 0 (TCIF) TCC overflowing interrupt flag. Set as TCC overflows, reset by software.
•Bit 1 (EXIF) External interrupt flag. Set by falling edge on the /INT pin, reset by software.
•Bits 4~7 are not used and read as "0".
•"1" means interrupt request, "0" means non-interrupt.
•R3F can be cleared by instruction, but can not be set in software.
•IOCF is the interrupt control register.
•Note that to read R3F will get the result of "logic AND" of R3F and IOCF.
Fig. 4 Data memory configuration

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EM78P451
VI.2 Special Purpose Registers
1. A (Accumulator)
•Internal data transfer, or instruction operand holding.
•A non-addressable register.
2. CONT (Control Register)
7654321 0
/PHEN /INT - - PAB PSR2 PSR1 PSR0
•Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2 PSR1 PSR0 TCC Rate WDT Rate
00 0 1:2 1:1
00 1 1:4 1:2
01 0 1:8 1:4
0 1 1 1:16 1:8
1 0 0 1:32 1:16
1 0 1 1:64 1:32
1 1 0 1:128 1:64
1 1 1 1:256 1:128
•Bit 3 (PAB) Prescaler assignment bit.
0: TCC
1: WDT
•Bit 6 (/INT) An interrupt enabling flag can not be written by the CONTW instruction.
0: interrupt masked by the DISI instruction.
1: interrupt enabled by the ENI or RETI instruction.
•Bit 7 (/PHEN) I/O pin pull-high enable flag.
0: For P60~P67, P74~P75 and P90~P95, the pull-high function is enabled.
1: The pull-high function is disabled.
•Bits 4, 5 are not used, and read as "0".
•Bits 0~3 and 7 of the CONT register are readable and writable.
3. IOC5 ~ IOC9 (I/O Port Control Register)
•"1" puts the relative I/O pin into high impedance, while "0" puts the relative I/O pin as output.
•Both P74 and P76 should not be defined as output pins at the same time, and it is the same way for both P75
and P77.

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EM78P451
•Only the lower 6 bits of the IOC9 register are used.
4. IOCD (Pull-high Control Register)
7654321 0
S7 - - - /PU9 /PU8 /PU6 /PU5
•The default values of /PU5, /PU6, /PU8, and /PU9 are “1”which means the pull-high function is disabled.
•/PU6, /PU9 are "AND" gating with /PHEN; that is, each one written "0" will enable the pull high function.
•S7 defines the driving ability of the P70-P72.
0: Normal output.
1: Enhance the driving ability for LED.
5. IOCE (WDT Control Register)
7654321 0
- ODE WTE SLPC ROC - - /WUE
•Bit 0 (/WUE) Control bit used to enable the wake-up function of P60~P67, P74~P75, and P90~P91.
0: Enable the wake-up function.
1: Disable the wake-up function.
The /WUE bit can be read and written.
•Bit 3 (ROC) ROC is used for the R-option. Setting ROC to "1" will enable the status of R-option pins (P80, P81)
to be read by the controller. Clearing ROC will disable the R-option function. Otherwise, the R-option function
is introduced. Users must connect the P81 pin or/and P80 pin to VSS by a 560KΩexternal resistor (Rex). If Rex
is connected/disconnected with VDD, the status of P80 (P81) will be read as "0"/"1". Refer to Fig. 7(b). The ROC
bit can be read and written.
•Bit 4 (SLPC) This bit is set by hardware at the falling edge of wake-up signal and is cleared in software. SLPC is
used to control the operation of oscillator. The oscillator is disabled (oscillator is stopped, and the controller
enters the SLEEP2 mode) on the high-to-low transition and is enabled (the controller is awakened from SLEEP2
mode) on the low-to-high transition. In order to ensure the stable output of the oscillator, once the oscillator is enabled
again, there is a delay for approximately 18 ms (oscillator start-up timer, OST) before the next instruction of program
being executed. The OST is always activated by wake-up from sleep mode whether the Code Option bit WTC is "0"
or not.After waking up, the WDT is enabled if Code Option WTC is "1". The block diagram of SLEEP2 mode and
wake-up caused by input triggered are depicted in Fig. 5. The SLPC bit can be read and written.
•Bit 5 (WTE) Control bit used to enable Watchdog Timer.
The WTE bit is used only if WTC, the CODE option bit, is "1". If the WTC bit is "1", then WDT can
be disabled/enabled by the WTE bit.
0: Disable WDT.
1: Enable WDT.
The WTE bit is not used if WTC, the CODE option bit WTC, is "0". That is, if the WTC bit is "0", WDT is
always disabled no matter what the WTE bit is.
The WTE bit can be read and written.

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EM78P451
•Bit 6 (ODE) Open-drain control bit.
0: Both P76 and P77 are normally I/O pins.
1: Both P76 and P77 pins have the open-drain function inside.
The ODE bit can be read and written.
•Bits 1~2 and 7 Not used.
6. IOCF (Interrupt Mask Register)
7654321 0
- - - - T1IE SPIIE EXIE TCIE
•Bit 0 (TCIE) TCIF interrupt enable bit.
0: disable TCIF interrupt
1: enable TCIF interrupt
•Bit 1 (EXIE) EXIF interrupt enable bit.
0: disable EXIF interrupt
1: enable EXIF interrupt
•Bit 2 (SPIIE) SPI interrupt enable bit.
0: disable SPI interrupt
1: enable SPI interrupt
•Bit 3 (T1IE) T1IE interrupt enable bit.
0: disable T1IE interrupt
1: enable T1IE interrupt
•Bits 4~7 Not used.
•Individual interrupt is enabled by setting its associated control bit in IOCF to "1".
•The IOCF register could be read and written.
Fig. 5 Block diagram of sleep mode and wake-up circuits on I/O ports

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EM78P451
VI.3 TCC/WDT Presacler
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available only for either the TCC
or the WDT at the same time and the PAB bit of the CONT register is used to determine the prescaler assignment. The
PSR0~PSR2 bits determine the prescaler ratio. The prescaler will be cleared by instructions which write to TCC each
time, when assigned to TCC mode.The WDTand prescaler, if assigned to the WDTmode, will be cleared by the WDTC
and SLEP instructions. Fig. 6 depicts the circuit diagram of TCC/WDT.
•R1(TCC) is an 8-bit timer/counter. TCC will increase by one in every instruction cycle (without prescaler).
•The watchdog timer is a free running on-chip RC oscillator. The WDT will keep running even the oscillator driver
has been turned off (i.e. in sleep mode). During the normal operation or the sleep mode, aWDT time-out (if enabled)
will cause the device to reset. The WDT can be enabled or disabled at any time during the normal mode by software
programming (if Code Option bit WTC is "1"). Refer to WTE bit of IOCE register. With no presacler, the WDT
time-out period is approximately 18 ms.
VI.4 I/O Ports
The I/O registers, from Port 5 to Port 9, are bi-directional tri-state I/O ports. P60~P67, P74~P75, and P90~P91 have the
internal pull-high and wake-up function programmable in software. P76~P77 have open-drain output by software control.
P80~P81 are the R-option pins which are enabled by software. While the R-option function is used, to use P80 and
P81 as output pins is recommended. During the period of R-option being enabled, P80 and P81 must be programmed as
input pins. If an external resistor is connected to P80 (P81) for the R-option function, the current consumption, if
necessary, should be aware of being in the power-saving applications.
The I/O ports can be defined as "input" or "output" pins by the I/O control registers (IOC5~IOC9) under program
control. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in
Fig. 7. Note that the reading paths are different between input and output while reading the data from the I/O port.
Fig. 6 Block diagram of TCC WDT

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EM78P451
Fig. 7 The circuit of I/O port and I/O control register
Fig. 8 Block diagram of Reset of controller
VI.5 SERIAL PERIPHERAL INTERFACE MODE
1. Overview & Features
Overview:

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EM78P451
Fig. 9, Fig. 10, and Fig. 11 show how EM78P451 to communicate with other devices by SPI module. If EM78P451 is a
master controller, it sends clock through the SCK pin.Acouple of 8-bit data are transmitted and received at the same time.
If EM78P451, however, is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be
shifted on a basis of both the clock rate and the selected edge.
Features:
•Operation in either Master mode or Slave mode.
•Three-wire or four-wire synchronous communication; that is, full duplex.
•Programmable baud rate of communication.
•Programming clock polarity.
•Interrupt flag available for the read buffer full.
•Up to 8 MHz ( maximum ) bit frequency.
Fig. 9 Single SPI Master / Slave Communication
Fig. 10 The SPI configuration of Single-master and Multi-slave
SDI
SDO
SCK
/SS
P50
P51
P52
P53
EM78P451
Master
SDO SDI SCK /SS
Slave Device 1
SDO SDI SCK /SS
Slave Device 2
SDO SDI SCK /SS
Slave Device 3
SDO SDI SCK /SS
Slave Device 4
Vdd

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2. Function Description
The following describes the function of signal how to carry out the SPI communication:
•P93/SDO: Serial Data Out.
•P92/SDI: Serial Data In.
•P94/SCK: Serial ClocK.
•P95//SS: /Slave Select (Option ). This pin (/SS) may be required during a slave mode.
•RBF: Set by Buffer Full Detector, and reset in software.
•RBFIF: Set by Buffer Full Detector, and reset in software.
•Buffer Full Detector: Setting to 1, while an 8-bit shift is complete.
•SSE: Loading the data to the SPISW register, and beginning to shift
•SPIS reg.: Shifting byte out and in. The MSB will be shifted first. Both the SPIS register and the
SPIW register are loaded at the same time. Once data being written to, SPIS starts
transmission / reception. The received data will be moved to the SPIR register, as the
shift of the 8-bit data is complete. The RBF (Read Buffer Full ) flag and the RBFI
(Read Buffer Full Interrupt) flag are set.
•SPIR reg.: Read buffer. The buffer will be updated as the 8-bit shift is complete. The data must
be read before the next reception is finished. The RBF flag is cleared as the SPIR
register read.
•SPIW reg.: Write buffer. The buffer will deny any write until the 8-bit shift is complete. The SE
bit will be kept in 1 if the communication is still under going. This flag must be
cleared as the shift is finished. Users can determine if the next write attempt is available.
•SBRS2~SBRS0: Programming the clock frequency/rates and sources.
•Clock Select: Selecting either the internal clock or the external clock as the shifting clock.
SDI
SDO
SCK
/SS
P51
P52
P53
P54
EM78P451
Master 1
or
Slave 1
SDO SDI SCK /SS
Slave 2 for master 1
SDO SDI SCK /SS
Slave 3 for Master 1/2
SDO SDI SCK /SS
Slave 4 for Master 1/2
SDO SDI SCK /SS
Slave 5 for Master 2
SDI
SDO
SCK
/SS
P51
P52
P53
P54
EM78P451
Master 2
or
Slave 6
Fig. 11 The SPI configuration of Single-mater and Multi-slave

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EM78P451
•Edge Select: Selecting the appropriate clock edges by programming the ES bit.
3. Signal & Pin Description
The four pins, SDI, SDO, SCK, and /SS, which are shown in Fig. 12, will be explained in detail as follows:
SDI/P92 (Pin 7):
•Serial Data In.
•Receive data serially; Most Significant Bit (MSB) first, Least Significant Bit (LSB) last.
•Defined as high-impedance, if not selected.
•Program the same clock rate and the same clock edge to latch on both the master device and slave device,
•The received byte will update the transmitted byte.
•Both the RBF bit and the RBFI bit (located in Register 0x0D) will be set as the SPI operation is complete.
•Timing is shown in Fig. 12 and Fig. 13 .
SDO/P93 (Pin 8):
•Serial Data Out.
•Transmit data serially; Most Significant Bit (MSB) first, Least Significant Bit (LSB) last.
•Program the same clock rate and the same clock edge to latch on both the master device and slave device.
•The received byte will update the transmitted byte.
•The ES (located in Register 0x0D) bit will be reset as the SPI operation is complete.
•Timing is shown in Fig. 12 and Fig. 13 .
SCK/P94 (Pin 9):
•Serial Clock.
•Generated by a master device.
•Synchronize the data communication on both the SDI pin and the SDO pin.
•The ES (located in Register 0x0D) is used to select the edge to communicate.
•The SBRS0~SBRS2 (located in Register 0x0D) are used to determine the baud rate of communication.
•The ES, SBRS0, SBRS1, and SBRS2 bits have no effect in the slave mode.
•Timing is show in Fig. 12 and Fig. 13.
/SS/P95 (Pin 10):
•Slave Select; negative logic.
•Generated by a master device to signify the slave(s) to receive data.
•Goes low before the first cycle of SCK appears and remains low until the last (eighth) cycle is complete.
•Ignores the data on the SDI and SDO pins while /SS is high, because the SDO is no longer driven.
•Timing is shown in Fig. 12 and Fig. 13 .
4. Programming the related registers
As the SPI mode is defined, the related registers of this operation are shown in Table 2 and Table 3.

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Table 2 Related control registers of the SPI mode
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0D *SPIC/RD ES/0 SPIE/0 SRO/0 SPISE/0 0/0 SBR2/0 SBR1/0 SBR0/0
0x0F INTC/IOCF 0 0 0 0 T1IE/0 SPIIE/0 EXIE/0 TCIE/0
<Note>*Bit name/initial valve
Table 3 Related status/data registers of the SPI mode
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0X0A SPIRB/RA SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0
0x0B SPIWB/RB SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0
0x0C SPIS/RC 0 0 0 T1IF OD3/0 OD4/0 RBFIF/0 RBF/0
SPIRB: SPI Read Buffer. Once the serial data is received completely, it will load to SPIRB from SPISR, and the RBF bit and
the RBFIF bit in the SPIS register will be set also.
SPIWB: SPI Write Buffer. As a transmitted data is loaded, the SPIS register start to shift the data.
SPIC: SPI Control Register. Table 4 shows the initial values at power on reset.
Table 4 Initial values of the SPIC register
SPIC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name CES SPIE SRO SSE 0 SBRS2 SBRS1 SBRS0
Power-on Reset 0 0 0 0 0 0 0 0
•CES (bit 7): Clock Edge Select bit
1 = Data shifts out on falling edge, and shifts in on rising edge. Data is held during the high level.
0 = Data shifts out on rising edge, and shifts in on falling edge. Data is held during the low level.
•SPIE (bit 6): SPI Enable bit
1= Enable SPI mode
0= Disable SPI mode
•SRO (bit 5): SPI Read Overflow bit
1 = A new data is received while the previous data is still being held in the SPIB register. In this situation, the data in
SPIS register will be destroyed. To avoid setting this bit, users had better to read SPIRB register even if the
transmission is implemented only.
0 = No overflow.
<Note>: This can only occur in slave mode.
•SSE (bit 4): SPI Shift Enable bit
1 = Start to shift and keep on 1 while the current byte is still being transmitted.
0 = Reset as soon as the shifting is complete, and the next byte is ready to shift.
<Note>: This bit has to be reset in software.
Table 5 SBRS (bit 2~bit 0): SPI Baud Rate Select bits
SBRS2(Bit 2) SBRS1(Bit 1) SBRS0(Bit 0) ModeBaud Rate
0 0 0 Master Fosc/2
0 0 1 Master Fosc/4
0 1 0 Master Fosc/8
0 1 1 Master Fosc/16
1 0 0 Master Fosc/32
1 0 1 Slave /SS enable
1 1 0 Slave /SS disable
1 1 1 Master TMR1/2

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EM78P451
<Note> In master mode, /SS is disabled.
SPIS: SPI Status register
•RBFI (bit 1): Read Buffer Full Interrupt flag
1 = Received is finished, SPIB is full, and an interrupt occurs if enabled.
0 = Received is not finished yet, and SPIB is empty.
•RBF (bit 0): Read Buffer Full flag
1 = Received is finished, and SPIB is full.
0 = Received is not finished yet, and SPIB is empty.
ODC: Open Drain Control register
•OD3 (bit 3): Open Drain Control bit(P93)
1 = Open drain enabled for SDO.
0 = Open drain disabled for SDO.
•OD4 (bit 2): Open Drain Control bit(P94)
1 = Open drain enabled for SCK.
0 = Open drain disabled for SCK.
INTC: Interrupt control register
•SPIIE (bit 2): SPI Interrupt Enable Control bit
1 = SPI Interrupt enabled.
0 = SPI Interrupt disabled.
5. SPI Mode Timing
The edge of SCK is selected by programming bit, CES. The waveform shown in Fig. 12 can be used no matter
EM78P451 is either in a master mode or in a slave mode with /SS disabled. However, the waveform in Fig. 13 can
only be implemented in a slave mode with /SS enabled.
Fig. 12 SPI Mode with /SS disabled

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6. SoftwareApplication of SPI
Example of SPI
;Define RAM
R_0 == 0 ;Indirect Addressing Register
PSW == 3 ;Status Register
RSR == 4 ;RAM Select Register
P9 == 9 ;Port 9
SPIRB == 0XA ;SPI Read Buffer
SPIWB == 0XB ;SPI Write Buffer
SPIS == 0XC ;SPI Status Register
SPIC == 0XD ;SPI Contolr Register
R_3F == 0X3F ;Interrupt Status Register
I_A == 0X13 ;SavingACC during interrupt
I_PSW == 0X14 ;Saving PSW during interrupt
;Define the control register
C_P9 == 0X9 ;Control Register of Port 9
C_INT == 0XF ;Interrupt Control Register
C_WDT == 0XD ;Enable Watchdog Timer<bit 4>
;Define bit
RUN == 4 ;SPIC<bit 4>
Fig. 13 SPI Mode with /SS enabled

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;Define pin
C_WDT ==0XD ;Enable Watchdog Timer<bit 4>
SS ==5 ;Port9<bit 5>
ORG 0x02
INT_VECT: ;The initial address of interrupt subroutine
MOV I_A,A ;Save Acc
SWAP I_A ;No status flags effected
SWAPA PSW ;Save PSW, and no status flags effected as well
MOV I_PSW, A ;
BS P9,5 ;SPI disabled by setting //SS(port9<bit 5>) to 1
;The following three bits must be cleared in order
BC SPIS, 0 ;RBF=0 (SPIS<bit 0>)
BC SPIS, 1 ;RBFI= 0 (SPIS<bit 0>)
BC R_3F, 2 ;SPIIE=0 (R_3F<bit 2>)
; (User Program)
SWAPA I_PSW ;
MOV PSW, A ;Recover PSW
SWAPA I_A ;Recover ACC
RETI
SPI: DISI ;Disable interrrupt
JBS RX, BX ;Mode select
JMP SLAVE ;If true, go to the MASTER mode;
;else go to the SLAVE mode
MASTER: MOV A,@0bXXXXX1XX ;Set SDI to be input, “X”:users define
IOWP9 ;
MOV A,@0b010001000’;The initial value of SPIC as a master mode
MOV SOIC, A ;
SLAVE: MOV A, @0bXX1XX1XX; Set SDI to be input, “X”:users define
IOWP9
MOV A, @0b01000101; The initial value of SPIC as a Slave mode
MOV SPIC, A ;
;Initiate the system configuration
MOV A, @0b00000111;
CONTW
MOV A, @0b00000100; Enable the SPI interrupt function
IOW C_INT ;
CLR R_3F ; Clear all the interrupt flags

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BS P9, 5 ; SPI disabled by setting /SS(port9<bit 5>) to 1
ENI ; Enable the interrupt function
; (User Program)
DISI
; In the SLAVE mode, trying to keep the RUN bit to 1 as possible.
JBC SPIC, RUN ; Check if RUN==0
JMP START TO RUN;
BS SPIC, RUN ; Set the RUN bit to 1
START TO RUN: ;
ENI ; Enable the interrupt function
; (User Program)
;The MASTER mode is being implemented
BC P9, SS ; Enable the SPI function by setting /SS to 0
; (User Program)
MOV SPIWB, A ; Load the transmitted value to SPIWB
; (User Program)
BS SPIC, RUN ; Start to execute the SPI function
; (User Program)
EOP ; End of program
ORG0XFFF ; The initial address
JMP SPI ; Go to the SPI program
VI.6 Timer
1. Overview
Timer1( TMR1 ) is an eight-bit clock counter with a programmable prescaler. It is designed for the SPI module as a
baud rate clock generator. TMR1 can be read and written and cleared on any reset conditions. If employed, it can be
turned down for power saving by setting TMR1EN bit [T1CON<2>] to 0.
2. Function Description
Fig. 14 shows TIMER1 block diagram. Each signal and block are described as following:

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Fig. 14 TIMER1 block diagram
OSC/4: Input clock.
Prescaler: Option of 1:1, 1:4, 1:8, or 1:16 defined by T1CLK1 and T1CLK2(T1CON<1, 0>). It is
cleared while a value is written to TMR1, T1CON or any kind of reset.
PWP: Pulse width preset register; the desired width of baud clock is written in advance.
TMR1: Timer 1 register; TMR1 increases until it matches with PWP, and then resets to 0. If it is
chosen optionally in the SPI mode, its output is fed as a shift clock.
Comparator: To change the output status while the match occurs. The TMR1IF flag will be set at the
same time.
3. Programming the related registers
As the TMR1 is defined, the related registers of this operation are shown in Table 6 and Table 7.
Table 6 Related control registers of the TMR1
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0C SPIS/RC 0 0 0 T1IF OD3 OD4 RBFIF RBF
0x0F INTC/IOCF 0 0 0 0 T1IE SPIIE EXIE TCIE
Table 7 Related status/data registers of the TMR1
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0X0E TMR1/RE TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10
0x0F PWP/RF PWP7 PWP6 PWP5 PWP4 PWP3 PWP2 PWP1 PWP0
0x0C T1CON/IOCC 0 0 0 0 0 T1E T1P1 T1P0
<Note>*Bit name/initial valve
Table 8 The rate of FOSC for timer1
TIP1 TIP0 RATE
001:1
011:4
101:8
1 1 1:16