Epson S5U1C33001H User manual

S5U1C33001H (Ver. 4)
S1C33 Family In-Circuit Debugger
■OVERVIEW
The S5U1C33001H (In-Circuit Debugger for the S1C33 Family) is a hardware tool (emulator) that allows software to be
efficiently developed for the S1C33 Family of 32-bit Single-Chip Microcomputers. It provides a software development
environment by communicating with the S1C33xxx chip.
This manual primarily explains how to use the S5U1C33001H. For details on the debugger (gdb.exe) functions and com-
mands, refer to the "Debugger" section in the "S5U1C33001C Manual (C Compiler Package for S1C33 Family)".
The figure below shows an external view of the S5U1C33001H.
Figure 1 S5U1C33001H External View
Note: Do not open the case as it may cause a malfunction.
Precautions before using the S5U1C33001H
Please read the sections shown below before getting started with the S5U1C33001H. These sections, especially (2)
and (3), describe the answers to frequently asked questions.
(1) "Components Included with Package" section
Make sure all of the listed items are included with your package.
(2) "Connecting the S5U1C33001H and the Host Computer" section
Install the USB driver before the S5U1C33001H can be used.
(3) "Connecting the Target System" section
Please pay particular attention to the Notes.

2
S5U1C33001H (Ver. 4)
Table 1 ICD Models and Differences
Function Model
C33 cores supported
Interface with the host PC
Data download speed ∗1
(maximum rate:DCLK = 40 MHz)
Clock frequency to communicate with the
target ∗1
Core clock frequency for using the trace
function ∗1
Maximum trace capacity
Flash programmer function
Firmware update function
Debugger mode
Bus trace function ∗4
Bus break trigger trace function ∗4
TRC IN pin input signal trace function ∗4
User logic signal trace function ∗4
Target power supply
Target reset signal output
Target system I/O interface voltage
RESET/WRITE switch
DIP switch
Jumper switch for monitoring power supply
LEDs for flash programmer
Target system interface connector
Target system interface method
Target power supply connector
S5U1C33000H
C33 STD core
C33 Mini core
C33 PE core
Serial and parallel I/F
Serial I/F: Approx. 8KB/s
Parallel I/F: Approx. 30KB/s
1 MHz to 40 MHz
1 MHz to 60 MHz (3.3 V)
(4 or 10-pin cable)
128K clock cycles
–
–
ICD2 mode
–
–
–
–
–
–
3.3 V
–
4 bits
–
–
10 pins
4 pins, 10 pins
–
S5U1C33001H (Ver. 3)
C33 STD core
C33 Mini core
C33 PE core
USB 1.1
About 65KB/s
(About 50KB/s at 20 MHz)
1 MHz to 40 MHz
1 MHz to 60 MHz (3.3 V)
(4 or 10-pin cable)
1M clock cycles
Available
–
ICD3 mode
–
–
–
–
–
–
3.3 V
Available
8 bits
Available
Available
10 pins
4 pins, 10 pins
–
S5U1C33001H (Ver. 4)
C33 STD core
C33 Mini core
C33 PE core
C33 ADV core
USB 1.1
About 65KB/s
(About 50KB/s at 20 MHz)
1 MHz to 40 MHz ∗3
1 MHz to 100 MHz (3.3 V) ∗2, ∗3
(4 or 10-pin cable,
or 30-pin coaxial cable)
1M clock cycles
Available
Available
ICD3 mode
Available
Available
Available
Available
3.3 V and 1.8 V
Available
3.3 V or 1.8 V
Available
8 bits
Available
Available
10 pins, 30 pins
4 pins, 10 pins, 30 pins
6 pins
∗1Indicates the specifications for 3.3-V I/O. The upper-limit value may be lowered by environment noise, temperature condition, S1C33
model, unevenness in quality, etc.
Note: In the model with the C33 STD or Mini core embedded, the maximum CPU core clock frequency is 60 MHz but the
maximum BCU (bus) clock frequency is 40 MHz. When operating the CPU with a clock higher than 40 MHz, the BCU
clock must be setup to 1/2 CPU core clock (#X2SPD = 0).
∗2The maximum frequency may be half or less of the described value when the I/O voltage is 1.8 V.
∗3Supports 32 kHz by firmware update.
∗4These functions are available only when the core that supports them is used (see the table below).
Table 2 Correspondence between C33 Core and Debug Functions
Function Core
DCLK while the program is halted
DCLK while the program is being executed
PC trace method
Switching the DCLK-core clock ratio
(DCLK while the program is halted)
Address setup for the debug unit
Area break function
Bus break function
Bus trace function
Bus break trigger trace function
TRC IN pin input signal trace function
User logic signal trace function
Use of MMU in debug mode
C33 STD/Mini
= Bus clock
= Core clock
Level 1
–
–
–
–
–
–
–
–
–
C33 PE
= Core clock ×set value
∗5
= Core clock
Level 1
Available
Available
–
–
–
–
–
–
–
C33 ADV
= Core clock ×set value
∗5
= Core clock
Level 2
Available
–
Available
Available
Available
Available
Available
Available
∗6
Available
∗51/1 to 1/8 (1/4 by default) can be selected by the DIP switch. See "DCLK-core clock ratio setting" in the "DIP Switches" section.
∗6Available only when the S1C33 model that supports the user logic signal trace function is used.
Level 2 is a PC trace method upwardly compatible with Level 1. It realizes higher analytical accuracy than Level 1.
Functions that are not included in the table above can be used regardless of the core model.

3
S5U1C33001H (Ver. 4)
■FUNCTIONAL OUTLINE
The functions of the S5U1C33001H are outlined below.
(1)Break functions
• PC break function
• Data break function
• Forced break function
• External forced break function (BRK IN pin input)
• Area break function
• Bus break function
-Logical or physical address is selectable.
(2)Trace functions
• Normal PC trace function/normal bus trace function
-Either the 1M clock cycles after a go command or the last 1M clock cycles before a break can be traced.
-The bus trace function allows selection of logical or physical addresses.
• Area PC trace function/area bus trace function
-Only the area between trace trigger 1 and trace trigger 2 is traced.
-Up to 1M clock cycles can be traced.
-The bus trace function allows selection of logical or physical addresses.
• Bus break trigger trace function
• TRC IN pin input signal trace function
• User logic signal trace function
(3)Measurement of the target program execution time
• The total time within an area can be measured in area trace mode.
(4)Flash memory writing function
(5)Flash programmer function
(6)Data transfer rate
• Execution rate: About 65KB/s
(7)Power supply to the target system
• 3.3 V and 1.8 V. The power supply monitoring function is available.
(8)Reset signal output to the target system
(9)Firmware update function
■OPERATING ENVIRONMENT
As the host computer, the S5U1C33001H uses a PC with a USB port (USB 1.1) available. Windows 2000 or Windows XP
is recommended for the OS.

4
S5U1C33001H (Ver. 4)
■COMPONENTS INCLUDED WITH PACKAGE
The following shows the components included with the package:
(1) S5U1C33001H (main unit) ......................................................... 1
(2) USB cable................................................................................... 1
(3) Target system interface cable (10-pin) ...................................... 1
(4) Target system interface cable (4-pin) ........................................ 1
(5) Target system interface cable (30-pin) ...................................... 1
(6) Target system interface connectors (10-pin) ............................. 4 (straight ×2, low-angle ×2)
(7) Target system interface connectors (4-pin) ............................... 4 (straight ×2, low-angle ×2)
(8) Target system interface connectors (30-pin) ............................. 2 (low-angle ×2)
(9) AC cable ..................................................................................... 1
(10)Target system power supply cable (6-pin)................................. 1
(11)Target system power supply connector (6-pin) ......................... 1 (low-angle)
(12)User registration card................................................................. English/Japanese, 1 each
(13)Warranty card............................................................................. English/Japanese, 1 each
(14)Usage precautions ..................................................................... English/Japanese, 1 each
(15)Manual download guide ............................................................. English/Japanese, 1 each
The items specified below are not included with the package. These items must be prepared separately.
(16)S5U1C33001H (Ver. 4) Manual (S1C33 Family In-Circuit Debugger) (this PDF, downloadable from the SEIKO EPSON HP)
(17)Debugger (gdb.exe) for the S1C33 Family (included in the S1C33 Family C Compiler Package)
(18)Debugger manual for the S1C33 Family (included in the S1C33 Family C Compiler Package)
•S5U1C33001H (main unit)
•AC cable • USB cable
•User registration card
•Warranty card
•Usage precautions
•Manual download guide
•Target system interface
cables •Target system connectors
•Target system power supply
cable •Target system power supply connector
10 pins–10 pins
10 pins–4 pins
6 pins–6 pins
30 pins–30 pins
10 pins (straight) × 2
English Japanese
Registration
..............
..........
............
........
10 pins (low angle) × 2
4 pins (straight) × 2
4 pins (low angle) × 2
6 pins (low angle)
30 pins (low angle) × 2
•••••
•••••
••••••
•••••
•••••
••••
••••
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
EMU/ERASE
TRC FULL/WRITE
POWER
OK
BUSY
ERROR UVCC VCC OUT
RESET/
WRITE
VCCSEL
TRCFULL
EMUOUT
TRGOUT
TRCIN
BRKIN
GND
Figure 2 Package Components

5
S5U1C33001H (Ver. 4)
■NAME AND FUNCTION OF EACH PART
●Operation Panel
The following shows an external view of the S5U1C33001H's operating section and the name of each part.
USB connector
IO
•••••
•••••
Front panel
Rear panel
Side panel (Left)
Target system interface connectors
Target system power supply connector
AC input connector
LEDs DIP switch Jumper Monitor pins
RESET/WRITE switch
Power switch
••••••
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
EMU/ERASE
TRC FULL/WRITE
POWER
OK
BUSY
ERROR UVCC VCC OUT
RESET
WRITE
VCCSEL
TRCFULL
EMUOUT
TRGOUT
TRCIN
BRKIN
GND
Figure 3 External View of Operating Section

6
S5U1C33001H (Ver. 4)
●DIP Switches
Note: Before setting the DIP switch, be sure to turn off the power to the S5U1C33001H.
The DIP switch assembly on the S5U1C33001H front panel is used to set the following conditions: DCLK setting, flash
programmer mode, target connection diagnostic function, flash programmer verification mode, and DSIO output level.
The figure below shows an external view of the DIP switch assembly.
1234
OPEN
ON
5 6 78
Figure 4 DIP Switch
• Flash programmer mode setting
DIP switches 1 and 7 enable/disable the flash programmer mode.
Table 3 DIP SW1 and SW7 Settings
SW1
OPEN
OPEN
ON
ON
SW7
OPEN
ON
OPEN
ON
Setting
Flash programmer mode disabled (default)
Flash programmer mode disabled
Flash programmer mode enabled (erase and write mode)
Flash programmer mode enabled (verify mode)
• DCLK - core clock ratio setting
DIP switches 2 and 3 set the ratio of the DCLK to the core clock frequencies.
Table 4 DIP SW2 and SW3 Settings
SW2
OPEN
OPEN
ON
ON
SW3
OPEN
ON
OPEN
ON
Setting
1/4 core clock (default)
1/2 core clock
1/1 core clock
1/8 core clock
These switches set the DCLK - core clock ratio while the program execution is halted. Select an appropriate value so
that the DCLK frequency will not exceed 40 MHz. If DCLK exceeds 40 MHz, the S5U1C33001H will not be able to
communicate with the target system normally; it may result in a target system failure.
While the program is being executed, the DCLK is set to the same frequency with the core clock. The upper-limit
frequency in this case is 100 MHz to perform tracing. There is no limit when tracing is not performed.
• Trace function setting
DIP switches 4 and 5 enable/disable the trace function.
Table 5 DIP SW4 and SW5 Settings
SW4
OPEN
OPEN
ON
ON
SW5
OPEN
ON
OPEN
ON
Setting
PC trace enabled, bus trace disabled (default)
PC trace disabled, bus trace disabled
PC trace enabled, bus trace enabled
Illegal value
• Target system connection diagnostics setting
DIP switch 6 selects whether the target system connection diagnostics function is used or not.
Table 6 DIP SW6 Setting
SW6
OPEN
ON
Setting
The target system connection test is run when the debugger is started. (default)
The target system connection test is omitted when the debugger is started.
• DSIO output level setting
DIP switch 8 sets the DSIO output level.
Table 7 DIP SW8 Setting
SW8
OPEN
ON
Setting
DSIO output level: 3.3 V (default)
DSIO output level: 1.8 V

7
S5U1C33001H (Ver. 4)
●RESET/WRITE Switch
On
5 6 7 8
RESET
WRITE
VCC SEL
Front panel
Figure 5 RESET/WRITE Switch
This switch functions as both the S5U1C33001H reset switch and as the erase/write switch when the S5U1C33001H is in
flash programmer mode.
●VCC SEL Jumper
Front panel
5 6 7 8
RESET
WRITE
VCC SEL
UVCC VCC OUT
UVCC VCC OUT
Figure 6 VCC SEL Jumper
This jumper selects whether the power supply monitoring function for the power supplied to the target system is used or not.
The power supply monitoring function stops power supply to the target system when the input to the TARGET_VCC pin in
the target power supply connector is 0 V.
Table 8 VCC SEL Setting
Jumper setting
UVCC
VCC OUT
Description
The power supply monitoring function is used
The power supply monitoring function is not used
●Monitor Pins
Front panel
TRC FULL
EMU OUT
TRG OUT
TRC IN
BRK IN
GND
Figure 7 Monitor Pins
• TRC FULL output pin
This is the trace full state output pin. This pin outputs a high level when the trace memory becomes full.
• EMU OUT output pin
This pin outputs a low level when the EMU/ERASE LED is lit (that is, when the program is being executed) and outputs
the 5 V level when that LCD is off (during a break). This signal can be used as the protect signal for the S5U1C33xxxM
emulation memory.
• TRG OUT output pin
The TRG OUT pin outputs the trace trigger signal that indicates the beginning and end of tracing. When using area trace
mode in the S5U1C33001H, two trigger points (trace area start and end addresses) are set up. The TRG OUT pin
outputs a high level when the program execution address reaches the set trace trigger point. Also it outputs a high level
while program execution is suspended. Refer to the "Debugger" section in the "S5U1C33001C Manual (C Compiler
Package for S1C33 Family)" for details on using the trace function.
The figure below shows output timing examples of this signal. Note that the program must be executed in the order of
trace trigger points 1 and 2 to generate trace triggers. The following figure shows conditions that will generate trace
triggers as well as those that will not.

8
S5U1C33001H (Ver. 4)
CPU operating clock
TRG OUT pin output
Trace trigger
point 1
Target program is in Stop state. Target program is in Run state.
Trace trigger
point 2
CPU operating clock
TRG OUT pin output
Trace trigger
point 1 Trace trigger
point 2 Trace trigger point 1 Trace trigger point 2
CPU operating clock
TRG OUT pin output
Trace trigger
point 1 Trace trigger
point 1 Trace trigger point 2 Trace trigger point 2
CPU operating clock
TRG OUT pin output
Trace trigger
point 2 Trace trigger
point 1 Trace trigger point 2 Trace trigger point 1
Figure 8 TRG OUT Output Timing Examples
• TRC IN input pin
This pin inputs an external trace signal. The input signal can also be traced when the bus trace is performed.
• BRK IN input pin
If a low-level signal is input to this pin when the target program is being executed, the target program execution is
suspended. After a low level is input to the BRK IN terminal, a break will occur after a few instructions have been
executed.
Note: Do not apply any voltages other than the following to the BRK IN pin: 0 V (low level), 3.3 to 5.0 V (high level),
or open.
• GND pin
To monitor the signals output from the above pins, connect the GND of a measuring instrument such as an oscilloscope
to this pin. If the ground level between the S5U1C33001H and the target system is unstable (particularly when the 4-pin
cable is used), this pin can be used to stabilize the ground level.

9
S5U1C33001H (Ver. 4)
●LEDs
Front panel
1 2 3 4 5 6 7 8
EMU/ERASE
TRC FULL/WRITE
POWER
OK
BUSY
ERROR
Figure 9 LEDs
• POWER (power-on LED, green)
This LED lights up when power is properly supplied to the S5U1C33001H by placing the power switch on the rear panel
in the "I" position. If this LED does not light up even when the power switch is turned on, check if the AC cable is properly
connected.
• TRC FULL/WRITE (trace memory full/flash memory write LED, yellow)
This LED lights up when the S5U1C33001H trace memory is filled by the target program execution. However, it does not
light up if the trace function is disabled by DIP switches 4 and 5. For enabling/disabling the trace function using the DIP
switch, refer to "Trace function setting" in the "DIP Switches" section.
Note: The TRC FULL LED that lights up does not go off until the S5U1C33001H starts sampling of trace data by
restarting the target program.
The WRITE LED lights during writing to the target system flash memory and goes off when the writing completes. The
ERASE LED also lights during verification.
• EMU/ERASE (emulation/flash memory erase LED, red)
This LED lights up when the debugger executes a program execution command, and indicates that the target program
is being executed.
Furthermore, it lights up if the target system power is off or the target system is not connected to the S5U1C33001H
when the S5U1C33001H is turned on. In this case, this LED goes off by turning the target system on. If the target system
is not connected, connect it to the S5U1C33001H after turning the S5U1C33001H off, and then turn the target system
and S5U1C33001H on. In break mode, this LED goes off and the S5U1C33001H can communicate with the S1C33xxx
chip.
The ERASE LED lights when the target system flash memory is being erased and goes off when the erase operation
completes. The WRITE LED also lights during verification.
• OK (flash programmer mode OK LED, green)
This LED lights in flash programmer mode when a target system flash memory write, erase, or verify operation com-
pletes with no error occurred.
• BUSY (flash programmer mode BUSY LED, yellow)
This LED lights in flash programmer mode when a target system flash memory write, erase, or verify operation is in
progress. It also lights during initialization after power is turned on.
• ERROR (flash programmer mode ERROR LED, red)
This LED lights in flash programmer mode when an error occurs during a target system flash memory write, erase, or
verify operation.

10
S5U1C33001H (Ver. 4)
●Power-Supply Operation Section
USB connector
IO
Rear panel
AC input connector Power switch
Figure 10 Power-Supply Operation Section
• Power switch
This is the power switch of the S5U1C33001H. The S5U1C33001H turns on when this switch is set to the "I" position.
• AC power connector
Plug the AC cable in this connector.
• USB connector
This connector is used to connect a USB cable.
●Target System Interface Connectors
•••••
•••••
Side panel (Left)
Target system interface connectors
Target system power supply connector
••••••
Figure 11 Target System Interface Connectors
• 10-pin target system interface connector
The target system is connected using the 10-pin or 10 to 4-pin cable.
• 30-pin target system interface connector
The target system is connected using the 30-pin cable.
Note: Use one connector only from either the 10-pin or 30-pin target system interface connectors.
• Target system power supply connector
This connector can supply power and output a reset signal to the target system using the 6-pin cable.

11
S5U1C33001H (Ver. 4)
■CONNECTING THE S5U1C33001H AND THE HOST COMPUTER
●Connecting the AC Cable
The S5U1C33001H uses a 3-wire (grounded) AC power cable.
Connect the AC frame ground of the host computer and the S5U1C33001H to a common frame ground as shown in the
figure below.
Host computer
AC line
Frame ground line
AC cable
S5U1C33001H (rear panel)
AC connector
IO
Figure 12 AC and Frame Ground Lines
●Connecting the USB Cable
The connectors at each end of the USB cable are type A (for the host computer) and type B (for the S5U1C33001H).
Turn on the S5U1C33001H power and connect the USB cable to the host computer. The host computer will request that the
USB driver be installed.
Use the procedure described in the next section to install the USB driver.
Note: The USB driver is located in the directory in which the S5U1C33001C (S1C33 Family C Compiler Package) is
installed: C:\gnu33\utility\drv_usb.
Host computer
S5U1C33001H (rear panel)
IO
USB connector
USB
Figure 13 Connecting the USB Cable

12
S5U1C33001H (Ver. 4)
●USB Driver Installation Procedure
(1) When the USB cable is first connected to the host computer, the following window will be displayed.
(2) Install the USB driver by following the directions displayed by the wizard.
Specify "C:\gnu33\utility\drv_usb" as the USB driver directory.
The device manager will be displayed as shown below when the USB driver has been installed correctly.
Note: If the window above is not displayed correctly, reinstall the USB driver.

13
S5U1C33001H (Ver. 4)
■CONNECTING THE TARGET SYSTEM
Use the 30-pin, 10-pin or 4-pin target system interface cable supplied with the S5U1C33001H package to connect the target
system. The target system must have a connector for connecting the above cable. For this, use the 30-pin, 10-pin or 4-pin
target connector supplied with the S5U1C33001H package or an equivalent connector. The pin assignment of the target
connector is shown in the tables below. For each signal pin number of the S1C33xxx chip, refer to the "S1C33xxx Technical
Manual" of the specific model.
TARGET I/F
TARGET
VCC I/F
Target system
S1C33xxx
Target I/F cable
(10-10 pins or 10-4 pins)
Target I/F cable
(30-30 pins)
oror
Target connector
(30 pins)
Target connector
(10 pins or 4 pins)
S5U1C33001H
EPSON
Figure 14 Connecting the Target System
Table 9 Pin Assignment of Target Connectors
No.
1
2
3
4
5
6
7
8
9
10
Pin name
DCLK
GND
DSIO
GND
DST2
GND
DST1
GND
DST0
DPCO
I/O
I
–
I/O
–
I
–
I
–
I
I
I/O
I
–
I/O
I
Pin function
Clock for debugging
Power supply (GND)
Serial I/O signal for debugging
Power supply (GND)
Debug status 2 signal
Power supply (GND)
Debug status 1 signal
Power supply (GND)
Debug status 0 signal
PC signal
10-pin connector •••••
•••••
1
2
9
10
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin name
GND
DCLK
GND
DSIO
GND
DST2
GND
DST1
GND
DST0
GND
DPCO
GND
DTS4
DTS3
I/O
–
I
–
I/O
–
I
–
I
–
I
–
I
–
I
I
Pin function
Power supply (GND)
Clock for debugging
Power supply (GND)
Serial I/O signal for debugging
Power supply (GND)
Debug status 2 signal
Power supply (GND)
Debug status 1 signal
Power supply (GND)
Debug status 0 signal
Power supply (GND)
PC signal
Power supply (GND)
Bus trace status 4 signal
Bus trace status 3 signal
No.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Pin name
DTS2
DTS1
DTS0
GND
DTD7
DTD6
DTD5
DTD4
GND
DTD3
DTD2
DTD1
DTD0
GND
DBT
I/O
I
I
I
–
I
I
I
I
–
I
I
I
I
–
I
Pin function
Bus trace status 2 signal
Bus trace status 1 signal
Bus trace status 0 signal
Power supply (GND)
Bus trace data 7 signal
Bus trace data 6 signal
Bus trace data 5 signal
Bus trace data 4 signal
Power supply (GND)
Bus trace data 3 signal
Bus trace data 2 signal
Bus trace data 1 signal
Bus trace data 0 signal
Power supply (GND)
Bus break trigger signal
30-pin connector
No.
1
2
3
4
Pin name
DCLK
GND
DSIO
DST2
Pin function
Clock for debugging
Power supply (GND)
Serial I/O signal for debugging
Debug status 2 signal
4-pin connector ••••
14
30 1

14
S5U1C33001H (Ver. 4)
Notes: • The signals connected to the S5U1C33001H are very high-speed signals, so the target connector must
mounted within 5 cm from the S1C33xxx. If there is more distance between the connector and the
S1C33xxx chip, the S5U1C33001H may not work properly.
•A33 Ωresistor must be connected in series to the DSIO signal line between the connector and the
S1C33xxx chip. The resistor should be placed as close to the S1C33xxx as possible.
•Be sure to use the supplied 30-pin, 10-pin or 4-pin cable for connecting the target system to the
S5U1C33001H. Using another cable may cause a malfunction. Furthermore, do not use the 30-pin cable
and 10-pin or 4-pin cable simultaneously.
•Disable the trace function of the S5U1C33001H using DIP switch 4 in the following cases:
-when using the 4-pin cable and connector.
-when the signals (DST0, DST1, DPCO) necessary for tracing are not connected even if the 30-pin or 10-
pin cable and connector is used.
-when the trace function is not used due to some reason even if the 30-pin or 10-pin cable and connector
is used and all the signals are connected.
•The 4-pin connector does not have a projection for preventing reverse insertion. Check the cable marker
of pin 1 to be sure the insertion of connector is proper when connecting it to the target system.
1
Target system10-4 pin cable
1
2
3
4
1
2
3
4
Figure 15 Connecting with 4-pin Connectors

15
S5U1C33001H (Ver. 4)
■START-UP METHOD (POWER-ON SEQUENCE)
To start up the S5U1C33001H system, follow the sequence described below:
(1) Turn the S5U1C33001H on.
POWER LED (green) lit
OK LED (green) lit
EMU/ERASE LED (red) lit
(2) Turn the target system on.
EMU/ERASE LED (red) goes out
This indicates that the target system was connected correctly.
(3) Start up the debugger (gdb.exe) on the host computer in ICD mode.
To terminate the S5U1C33001H system, follow the sequence described below:
(1')Terminate the debugger (gdb.exe) on the host computer.
(2')Turn the target system off.
(3')Turn the S5U1C33001H off.
Notes: • Normally the S5U1C33001H system can work properly when the target system is turned on first and then
the S5U1C33001H. However, the power-on sequence described above is recommended since the system
may not work properly if the target system is in indeterminate operation or in runaway status.
•If the debugger (gdb.exe) is terminated after the S5U1C33001H is turned off, the debugger may not work
properly with "Cannot open ICD33 usb driver." displayed on the screen when it is re-invoked. In this case,
turn on or reset the S5U1C33001H after terminating the debugger (gdb.exe) once, and then re-invoke the
debugger.
For details on how to invoke/terminate the debugger, refer to the "Debugger" section in the "S5U1C33001C Manual (C
Compiler Package for S1C33 Family)". Furthermore the debugger (gdb.exe) must be invoked after turning all the power of
the system on.
Check the following if the debugger reports a target down error, which means that communication between the
S5U1C33001H and the target system is not functioning.
• If the target system power is turned on after the S5U1C33001H is turned on:
After the S5U1C33001H power is turned on, a forced break will be applied continuously to the target system. After the
target system is turned on, the S1C33xxx chip is reset. The S1C33xxx chip enters debug mode and starts communica-
tion with the S5U1C33001H. If multiple power on/reset cycles occur caused by switch bounce when the target is turned
on, the communication between the S5U1C33001H and the target system may be disconnected after the second reset.
Design the target system so that switch bounce does not occur and the system starts up only once. Furthermore, if the
reset is applied with either the power or the oscillator in an unstable state (for example, if the reset is applied within the
first few ms after the power is turned on), the S1C33xxx chip operation will also be unstable. In this case the system will
not enter debug mode and communication between the S5U1C33001H and the target system will not be possible. Apply
the reset only after an adequate stabilization time has elapsed. Refer to the "S1C33xxx Technical Manual" for more
information on the reset operation.
• If the S5U1C33001H is turned on after the target system power is turned on:
When the S5U1C33001H is turned on, it issues a forcible break to the free-running target system. The S1C33xxx chip
enters debug mode and starts communication with the S5U1C33001H. If a boot program was not loaded into ROM, the
S1C33xxx chip cannot respond to the forced break since the S1C33xxx chip is in the runaway state, so communication
is impossible. Load a boot program that operates correctly into boot ROM so that the target system will not be in the
runaway state.

16
S5U1C33001H (Ver. 4)
• If the initial connection operation fails
In this case, add a reset switch to the target system and start the system in the following sequence:
(1) Turn the target system on
(2) Hold down the reset switch on the target system and turn the S5U1C33001H on
(3) Release the reset switch to clear the reset state.
This will allow the system to operate reliably. This is because this sequence reliably reproduces the conditions in the "If
the S5U1C33001H is turned on after the target system power is turned on" item above. If it is not possible to connect,
install a reset switch on the target system. We recommend adding the reset switch at the system design stage.
• RESET/WRITE switch on the S5U1C33001H
Besides turning power on and off, the S5U1C33001H can be reset using the on-board RESET/WRITE switch.
Also the RESET/WRITE switch changes the signal output from the TARGET_RESET pin in the target system power
supply connector (see next section).

17
S5U1C33001H (Ver. 4)
■POWER SUPPLY AND RESET SIGNAL OUTPUT TO THE TARGET SYSTEM
The S5U1C33001H includes the capability of supplying power and outputting a reset signal to the target system.
Table 10 Pin Assignment of the Target System Power Supply Connector
Pin name
Vcc (3.3 V)
Vcc (1.8 V)
Vss
TARGET_VCC
Vss
TARGET_RESET
Pin No.
1
2
3
4
5
6
Function
Target system power supply pin (3.3V)
Target system power supply pin (1.8V)
Target system power supply pin (GND)
Target system power supply monitor input pin
Target system power supply pin (GND)
Target system reset output pin
The TARGET_VCC pin is used for the target power monitoring function. When this function is enabled, the S5U1C33001H
stops supplying power to the target system if the input voltage of the TARGET_VCC pin goes to 0 V.
The TARGET_RESET signal changes according to the RESET/WRITE switch operation.
When the RESET/WRITE switch is off: 3.3 V is output
When the RESET/WRITE switch is on: 0 V is output
When using the TARGET_RESET signal for resetting the target system, a reset circuit as shown in the figure below is
recommended.
S5U1C33001H
TARGET_RESET
Target system
S1C33xxx
Pull-up resistor
Reset switch
Target
reset
circuit
3.3 V
#RESET
Figure 16 Example of Reset Circuit
The RESET/WRITE switch operation does not affect supplying power to the target system.
Note that the maximum current that can be supplied is 10 mA.
∗The S5U1C33001H power supply circuit includes a PolySwitch (resettable fuse) that shuts down the power supply to the
target system when the output current exceeds 500 mA (it is automatically reset when the output current returns within the
range).

18
S5U1C33001H (Ver. 4)
■FIRMWARE UPDATE PROCEDURE
The S5U1C33001H has a firmware update function using the debugger (gdb.exe). The following show the procedure to
update the S5U1C33001H firmware.
Note: Before the firmware can be updated, the USB driver must be installed.
(1) Connect the S5U1C33001H with the target system using the 4-pin, 10-pin or 30-pin cable.
The firmware update function is implemented as a part of target system debug function. Therefore, the target system
must be connected to the S5U1C33001H, although the target system is not actually used for the update.
(2) Connect the S5U1C33001H with the host computer using the USB cable.
(3) Invoke the debugger (gdb.exe)
• To invoke at the command prompt:
>start /w gdb -nw --c33_no_ver
• To invoke from gwb33
Just click the [GDB] button with nothing selected.
(4) Enter the commands shown below after the debugger starts up.
(gdb) target icd usb
(gdb) c33 firmupdate icd33dmt.sa
(5) The update operation has completed when the OK LED is lit.
Terminate the debugger (gdb.exe) and turn the S5U1C33001H off then on again.

19
S5U1C33001H (Ver. 4)
■TARGET SYSTEM CONNECTION TEST
The S5U1C33001H can diagnose whether it can communicate with the target system or not when the debugger (gdb.exe)
starts up. This function can be omitted or executed using the DIP switch.
• Omitting the target system connection test
If SW6 of the DIP switch located on the S5U1C33001H front panel is placed in the ON (lower) position, the
S5U1C33001H omits the target system connection test when the debugger (gdb.exe) starts up.
• Executing the target system connection test
If SW6 of the DIP switch located on the S5U1C33001H front panel is placed in the OPEN (upper) position, the
S5U1C33001H executes the target system connection test when the debugger (gdb.exe) starts up.
When the target system connection test is completed normally, the following is displayed on the debugger screen:
Connecting with target ... done
CPU type and debug unit address setting ... done
Initializing ............. done
CPU type and debug unit address setting ... done
CPU cold resetting ....... done
Target connection test ... done ←display when terminated normally.
ICD hardware version ... 30 ("omitted" will appear if the connection test is omitted.)
ICD software version ... 3.5
CPU type and debug unit address setting ... done
CPU cold resetting ....... done
Boot address ............. 0xc00000
Note: Always be sure to turn off the power to the S5U1C33001H before setting the DIP switch.
If an error message is displayed after the target system connection test is executed, failure may have oc-
curred in the target system. Check to see whether the target system is working properly or not.
Normally enable the target system connection test.

20
S5U1C33001H (Ver. 4)
■PRECAUTIONS
●Restrictions on Debugging
The debugging using the S5U1C33001H is subject to the restrictions specified below.
• Operation of the internal peripheral circuits
The peripheral circuits of the S1C33xxx stop operating when the debugger (gdb.exe) on the host computer is ready to
accept commands, that is, unless the target program is running. For this reason, the peripheral circuits do not operate in
real time when the target program is executed in the single-step mode. For details on single-step execution, refer to the
"Debugger" section in the "S5U1C33001C Manual (C Compiler Package for S1C33 Family)".
• Interrupts when the target program is not running
If an interrupt request to the C33 core is generated by the target system when the target program is not running, interrupt
processing is paused. The interrupt that has been paused is serviced immediately before the target program is executed
or immediately after one instruction is executed after the debugger (gdb.exe) on the host computer has directed that the
target program be executed.
• Interrupts when the target program is executed in a single step
If an interrupt request to the C33 core is generated by the target system during single-step execution of the target
program, including functions and subroutines (STEP), the interrupt request is paused. During single-step execution of
the target program, not including functions and subroutines (NEXT), an interrupt request received within a function or
subroutine is serviced without being paused and an interrupt received in other parts of the program is paused as with the
STEP command. The interrupt that has been paused is serviced immediately before the target program is executed or
immediately after one instruction is executed after the debugger (gdb.exe) on the host computer has directed that the
target program be executed. For details on single-step execution (STEP and NEXT), refer to the "Debugger" section in
the "S5U1C33001C Manual (C Compiler Package for S1C33 Family)".
• Break functions
The S5U1C33001H and the debugger support multiple break functions.
The timing at which a break occurs is classified into the following two categories depending on the break function.
(1) Break functions that suspend the target program before the instruction in which the cause of the break occurred is
executed
Software PC break, hardware PC break
(2) Break functions that suspend the target program after several instructions are executed from the instruction in which
the cause of the break occurred
Data break, area break, bus break
For details on break functions, refer to the "Debugger" section in the "S5U1C33001C Manual (C Compiler Package for
S1C33 Family)".
• Trace function
Note that the trace function in the S5U1C33001H has the following restrictions. Furthermore, refer to the technical
information of the trace function ("Implementation of the PC Trace Function" and "Implementation of the Bus Trace
Function").
(1) The S5U1C33001H PC trace function can trace only instruction execution cycle information. Note that data access
(read/write) information cannot be traced. When the target system uses the S1C33 model in which a C33 core that
supports the bus trace function is embedded, data read/write information can be traced.
(2) Be aware that the trace function cannot be used when it is disabled using the DIP switch. For enabling/disabling the
trace function using the DIP switch, refer to "Trace function setting" in the "DIP Switches" section.
(3) There are certain functional limitations to the PC trace function that are due to the analysis procedure being imple-
mented in software. Refer to "Implementation of the PC Trace Function" section and the "S5U1C33001C Manual (C
Compiler Package for S1C33 Family)" for more information.
(4) Be aware that the trace function cannot be used when using the 4-pin cable to connect the target system to the
S5U1C33001H.
(5) Be aware that the bus trace function cannot be used when using the 10-pin cable to connect the target system to the
S5U1C33001H.