Excalibur DAS-429PCI/Mx User manual

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311 Meacham Avenue Elmont NY 11003 Tel. [phone] Fax [phone]
e-mail: [email protected] website: www.mil-1553.com
DAS-429PCI/Mx
Multi-channel ARINC 429
Test and Simulation Board
for PCI Systems
User’s Manual
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Table of Contents
DAS-429PCI/Mx: User’s Manual page i
Table of Contents
1 Introduction
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2
1.2 Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
1.2.1 Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
1.2.2 Board Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
1.3 Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
1.4 PCI Configuration Space Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.5 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7
1.5.1 Vendor Identification Register (VID) . . . . . . . . . . . . . . . . . . . . . .1-7
1.5.2 Device Identification Register (DID) . . . . . . . . . . . . . . . . . . . . . .1-7
1.5.3 PCI Command Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
1.5.4 PCI Status Register (PCISTS). . . . . . . . . . . . . . . . . . . . . . . . . . .1-9
1.5.5 Revision Identification Register (RID) . . . . . . . . . . . . . . . . . . . .1-10
1.5.6 Class Code Register (CLCD) . . . . . . . . . . . . . . . . . . . . . . . . . .1-10
1.5.7 Cache Line Size Register (CALN) . . . . . . . . . . . . . . . . . . . . . . .1-11
1.5.8 Latency Timer Register (LAT) . . . . . . . . . . . . . . . . . . . . . . . . . .1-11
1.5.9 Header Type Register (HDR). . . . . . . . . . . . . . . . . . . . . . . . . . .1-12
1.5.10 Built-In Self-Test Register (BIST) . . . . . . . . . . . . . . . . . . . . . .1-12
1.5.11 Base Address Registers (BADR). . . . . . . . . . . . . . . . . . . . . . .1-13
1.5.12 Expansion ROM Base Address Register (XROM). . . . . . . . . .1-15
1.5.13 Interrupt Line Register (INTLN) . . . . . . . . . . . . . . . . . . . . . . . .1-15
1.5.14 Interrupt Pin Register (INTPIN) . . . . . . . . . . . . . . . . . . . . . . . .1-16
1.5.15 Minimum Grant Register (MINGNT) . . . . . . . . . . . . . . . . . . . .1-16
1.5.16 Maximum Latency Register (MAXLAT) . . . . . . . . . . . . . . . . . .1-16
1.6 PCI Global Interrupt Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-17
1.6.1 PCI Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . .1-17
1.6.2 PCI Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .1-17
2 Module Operation
2.1 Module General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.2 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.3 Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
2.3.1 Global Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . .2-4
2.3.2 Global Interrupt Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
2.3.3 Global Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . .2-5
2.4 Module Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
2.4.1 Start/Stop Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
2.4.2 Module Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.4.3 Firmware Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.4.4 Channel Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
2.4.5 Receiver Data Storage Mode Register . . . . . . . . . . . . . . . . . . . .2-9
2.4.6 Interrupt Status Busy Register. . . . . . . . . . . . . . . . . . . . . . . . . .2-10
2.4.7 Reset Time Tag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
2.4.8 Module ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
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Table of Contents
page ii Excalibur Systems
2.5 Receiver Merge Mode Control Registers . . . . . . . . . . . . . . . . . . . . . .2-11
2.5.1 Receiver Merge Start Pointer . . . . . . . . . . . . . . . . . . . . . . . . . .2-11
2.5.2 Receiver Merge End Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11
2.5.3 Receiver Merge Current Pointer . . . . . . . . . . . . . . . . . . . . . . . .2-11
2.5.4 Receiver Merge Filter Table Start Address . . . . . . . . . . . . . . . .2-11
2.5.5 Receiver Merge Word Count . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11
2.5.6 Receiver Merge Buffer Wraparound Register . . . . . . . . . . . . . .2-12
2.5.7 Receiver Merge Word Count Trigger Register . . . . . . . . . . . . .2-12
2.5.8 Receiver Merge Interval Count Trigger Register . . . . . . . . . . . .2-12
2.5.9 Receiver Merge Label Trigger Register. . . . . . . . . . . . . . . . . . .2-13
2.5.10 Receiver Merge Configuration Register . . . . . . . . . . . . . . . . .2-13
2.5.11 Receiver Merge Interrupt Condition Register . . . . . . . . . . . . .2-14
2.5.12 Receiver Merge Status Register . . . . . . . . . . . . . . . . . . . . . . .2-14
3 Transmit Mode
3.1 Transmit Channel Control Register Block Maps . . . . . . . . . . . . . . . . .3-2
3.1.1 Channel 2 Control Register Block Map . . . . . . . . . . . . . . . . . . . .3-2
3.1.2 Channel 5 Control Register Block Map . . . . . . . . . . . . . . . . . . . .3-2
3.2 Transmit Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
3.2.1 Channel x Configuration Register . . . . . . . . . . . . . . . . . . . . . . . .3-3
3.2.2 Channel x Transmit Instruction Stack Pointer . . . . . . . . . . . . . . .3-3
3.2.3 Channel x Transmit Instruction Counter . . . . . . . . . . . . . . . . . . .3-4
3.2.4 Channel x Transmit Loop Counter. . . . . . . . . . . . . . . . . . . . . . . .3-4
3.2.5 Channel x Transmit Current Word Register. . . . . . . . . . . . . . . . .3-4
3.2.6 Channel x Transmit Current Loop Register . . . . . . . . . . . . . . . . .3-4
3.2.7 Channel x Interrupt Condition Register . . . . . . . . . . . . . . . . . . . .3-5
3.2.8 Channel x Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5
3.3 Transmit Instruction Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6
3.3.1 Control Word Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
3.3.2 Word Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
3.3.3 Interword Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
3.3.4 Transmit Data Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
3.4 Transmit Data Block Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
4 Receive/ Monitor Mode
4.1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.1.1 Sequential Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.1.2 Look-Up Table Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.1.3 Merge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.2 Sequential/Merge Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.2.1 Receive Buffer Storage Sequence . . . . . . . . . . . . . . . . . . . . . . .4-3
4.2.2 Receive Data Word Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.2.3 Time Tag Word Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
4.2.4 Receive Sequential Mode Filter Table Diagram . . . . . . . . . . . . .4-6
4.2.5 Receive Sequential Mode Status Word . . . . . . . . . . . . . . . . . . . .4-7
4.2.6 Receive Merge Mode Status Word . . . . . . . . . . . . . . . . . . . . . . .4-7
4.3 Look-up Table Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8
4.3.1 Receive Look-Up Table Storage Sequence . . . . . . . . . . . . . . . .4-8
4.3.2 Receive Look-Up Table Mode Diagram . . . . . . . . . . . . . . . . . . .4-8
4.3.3 Receive Look-Up Table Status/Control Word . . . . . . . . . . . . . . .4-9
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Table of Contents
DAS-429PCI/Mx: User’s Manual page iii
4.4 Receive Channel Control Register Block Maps . . . . . . . . . . . . . . . . .4-10
4.4.1 Channel 0 Control Register Block Map . . . . . . . . . . . . . . . . . . .4-10
4.4.2 Channel 1 Control Register Block Map . . . . . . . . . . . . . . . . . . .4-11
4.4.3 Channel 3 Control Register Block Map . . . . . . . . . . . . . . . . . . .4-12
4.4.4 Channel 4 Control Register Block Map . . . . . . . . . . . . . . . . . . .4-13
4.5 Receive Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . .4-14
4.5.1 Channel x Configuration Register . . . . . . . . . . . . . . . . . . . . . . .4-14
4.5.2 Channel x Receive Data Start Pointer . . . . . . . . . . . . . . . . . . . .4-15
4.5.3 Channel x Receive Data End Pointer . . . . . . . . . . . . . . . . . . . .4-15
4.5.4 Channel x Receive Data Current Pointer . . . . . . . . . . . . . . . . .4-15
4.5.5 Channel x Receive Look-up Table Start Address . . . . . . . . . . .4-15
4.5.6 Channel x Receive Filter Table Start Address. . . . . . . . . . . . . .4-15
4.5.7 Channel x Receive Data Word Count Register . . . . . . . . . . . . .4-16
4.5.8 Channel x Receive Buffer Wraparound Register. . . . . . . . . . . .4-16
4.5.9 Channel x Receive Data Word Counter Trigger Register . . . . .4-16
4.5.10 Channel x Receive Interval Counter Trigger Register . . . . . . .4-16
4.5.11 Channel x Receive Label Trigger Register . . . . . . . . . . . . . . .4-17
4.5.12 Channel x Interrupt Condition Register . . . . . . . . . . . . . . . . . .4-17
4.5.13 Channel x Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-18
5 Mechanical and Electrical Specifications
5.1 Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
5.2 LED Indicators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
5.3 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
5.3.1 Connector J1 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
5.3.2 Connector J1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
5.3.3 Connector J1 Communication I/O Signals Description . . . . . . . .5-4
5.3.4 PCI Bus Edge Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . .5-5
6 Ordering Information
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Table of Contents
page iv Excalibur Systems
Figures
Figure 1-1 DAS-429PCI/Mx Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Figure 1-2 M429R4T2 Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . 1-3
Figure 1-3 DAS-429PCI/Mx Memory Structure. . . . . . . . . . . . . . . . . . . . . . 1-5
Figure 1-4 PCI Configuration Space Header . . . . . . . . . . . . . . . . . . . . . . . 1-6
Figure 2-1 Module M429R4T2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . 2-3
Figure 2-2 Global Registers Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Figure 2-3 Module Control Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Figure 3-1 Channel 2 Control Register Block Map . . . . . . . . . . . . . . . . . . . 3-2
Figure 3-2 Channel 5 Control Register Block Map . . . . . . . . . . . . . . . . . . . 3-2
Figure 3-3 Transmit Instruction Stack Structure . . . . . . . . . . . . . . . . . . . . . 3-6
Figure 3-4 Transmit Data Words memory Format . . . . . . . . . . . . . . . . . . . 3-8
Figure 3-5 Data Bytes In Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Figure 3-6 32-bit ARINC Word Bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Figure 4-1 Receive Sequential Mode Buffer Structure . . . . . . . . . . . . . . . . 4-3
Figure 4-2 Receive Data Word Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Figure 4-3 Receive Word Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Figure 4-4 Time Tag Word Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Figure 4-5 Receive Sequential Mode Filter Table. . . . . . . . . . . . . . . . . . . . 4-6
Figure 4-6 Receive Look-up Table Mode Structure . . . . . . . . . . . . . . . . . . 4-8
Figure 4-7 Channel 0 Control Register Block Map . . . . . . . . . . . . . . . . . . 4-10
Figure 4-8 Channel 1 Control Register Block Map . . . . . . . . . . . . . . . . . . 4-11
Figure 4-9 Channel 3 Control Register Block Map . . . . . . . . . . . . . . . . . . 4-12
Figure 4-10 Channel 4 Control Register Block Map . . . . . . . . . . . . . . . . . . 4-13
Figure 5-1 DAS-429PCI/Mx Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Figure 5-2 Connector J1 Layout (Front View). . . . . . . . . . . . . . . . . . . . . . . 5-2
Tables
Table 1-1 Address nvRAM/EPROM Boot Values . . . . . . . . . . . . . . . . . . . . 1-13
Table 5-1 Connector J1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Table 5-2 Connector J1 Communication I/O Signals Description . . . . . . . . . 5-4
Table 5-3 PCI Bus Edge Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
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Chapter 1 Introduction
DAS-429PCI/Mx: User’s Manual page 1 - 1
1 Introduction
Chapter 1 provides an overview of the DAS-429PCI/Mx avionics communication
board. The following topics are covered:
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2
1.2 Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
1.2.1 Software Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
1.2.2 Board Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
1.3 Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
1.4 PCI Configuration Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.5 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7
1.5.1 Vendor Identification Register (VID) . . . . . . . . . . . . . . . . . . . . . .1-7
1.5.2 Device Identification Register (DID). . . . . . . . . . . . . . . . . . . . . . .1-7
1.5.3 PCI Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
1.5.4 PCI Status Register (PCISTS) . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9
1.5.5 Revision Identification Register (RID) . . . . . . . . . . . . . . . . . . . .1-10
1.5.6 Class Code Register (CLCD). . . . . . . . . . . . . . . . . . . . . . . . . . .1-10
1.5.7 Cache Line Size Register (CALN) . . . . . . . . . . . . . . . . . . . . . . .1-11
1.5.8 Latency Timer Register (LAT) . . . . . . . . . . . . . . . . . . . . . . . . . .1-11
1.5.9 Header Type Register (HDR). . . . . . . . . . . . . . . . . . . . . . . . . . .1-12
1.5.10 Built-In Self-Test Register (BIST). . . . . . . . . . . . . . . . . . . . . . .1-12
1.5.11 Base Address Registers (BADR) . . . . . . . . . . . . . . . . . . . . . . .1-13
1.5.12 Expansion ROM Base Address Register (XROM). . . . . . . . . .1-15
1.5.13 Interrupt Line Register (INTLN) . . . . . . . . . . . . . . . . . . . . . . . .1-15
1.5.14 Interrupt Pin Register (INTPIN) . . . . . . . . . . . . . . . . . . . . . . . .1-16
1.5.15 Minimum Grant Register (MINGNT) . . . . . . . . . . . . . . . . . . . .1-16
1.5.16 Maximum Latency Register (MAXLAT) . . . . . . . . . . . . . . . . . .1-16
1.6 PCI Global Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-17
1.6.1 PCI Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . .1-17
1.6.2 PCI Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .1-17
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Chapter 1 Introduction
page 1 - 2 Excalibur Systems
1.1 Overview
The DAS-429PCI/Mx is a modular ARINC-429 memory-mapped, multi-channel
(up to 24) test, simulation, and monitor board for PCI systems. The
DAS-429PCI/Mx provides a total solution for developing and testing ARINC-429
interfaces and for performing system simulation of the ARINC-429 bus, both in
the lab and in the field.
The DAS-429PCI/Mx is based on the latest Surface Mount Technology, which
substantially reduces the area required. The DAS-429PCI/Mx comes configured
with 2(x) transmit and 4(x) receive channels (where x = number of modules
ordered). The channels are organized in four independent modules (P/N:
M429R4T2), each configured with 4 receive and 2 transmit channels. Each
module contains an on board hi-speed controller and 16K x 16 true
dual-port RAM. Each module is accessed through a paging mechanism and
operates independently. Each module can be set up to generate interrupts to the
host in a variety of circumstances through an extensive interrupt structure. Both
transmit and receive channels may be programmed for Hi (100Khz) or Lo
(12.5Khz) speed bit rates. In addition, either odd or even parity may be
programmed for transmit channels.
All control registers and data blocks can be accessed directly in real time. The
board supports filtering of receive data and multiple data storage modes. Status
and time tag information are appended to each word. The transmit channels
operate via a transmitter “instruction” stack which allows scheduling of data
transmissions and reduces the need for host computer intervention. The
DAS-429PCI/Mx comes complete with C driver software libraries, including
source code.
The DAS-429PCI/Mx is ideally suited for developing, simulating, testing and
monitoring ARINC-429 interfaces for multi-channel applications requiring a
single PCI board.
DAS-429PCI/Mx Board Features:
See Chapter 6: Ordering Information for exact part numbers.
Up to 24 ARINC-429 channels (Receive and
Transmit)
Eurocard 3U size
Compatible with PCI computers
Easy to install and operate
Organized in 4 modules, each containing:
4 Receive channels
2 Transmit channels
16k ×16 true dual-port RAM
On board 32 bit processor
12.5Khz bit and 100Khz bit data rates
Selectable even/odd parity
Programmable interword gap
Real time operation
Transmission modes:
One-shot
Loop
N-times
Two Receive/Monitor modes:
Sequential
Look-up table
32 bit time tagging per word
Merge mode stores data from multiple receive
channels in one buffer
Label filtering
Start triggers
Receive count interval triggers
Interrupt and polling modes of operation
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Chapter 1 Introduction
DAS-429PCI/Mx: User’s Manual page 1 - 3
Figure 1-1 below illustrates the DAS-429PCI/Mx’s block diagram
Figure 1-1 DAS-429PCI/Mx Block Diagram
Figure 1-2 below illustrates the block diagram of a single M429R4T2 module.
Figure 1-2 M429R4T2 Module Block Diagram
PCI
BUS
CNTRL
CNTRL
ADDR/DATA
ADDR/DATA
20 MHz
PCI
INTERFACE
CONTROLLER
ARINC-429
CONNECTIONS
J1
ARINC-429
MODULE #0
(M429R4T2)
ARINC-429
MODULE #1
(M429R4T2)
ARINC-429
MODULE #2
(M429R4T2)
ARINC-429
MODULE #3
(M429R4T2)
RX0(i)*
TX0(j)**
RX1(i)
TX1(j)
RX2(i)
TX2(j)
RX3(i)
TX3(j)
40 MHz
OSC
* i - Receive channel index (0,1,3,4)
** j - Transmit channel index (2,5)
LOCAL
BUS
20MHz
ADDR/
DATA
CNTRL
MC68340
Micro-
Controller
Local Bus
Interface
RX3
RX4
TX5
16K x 16
Dual Port
RAM
128K x 16
Program
RAM
128K x 8
Boot
Flash
ENC/DEC
ENC/DEC
Logic
Block
FPGA
ARINC-429
DRIVER
ARINC-429
DRIVER ARINC-429
CHANNELS
RX0
RX1
TX2
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Chapter 1 Introduction
page 1 - 4 Excalibur Systems
1.2 Installation
DAS-429PCI/Mx installation includes installing the software for each system
and installing the board.
1.2.1 Software Installation
The DAS-429PCI/Mx is delivered with software compatible with several
operating systems. For information about installing the accompanying software
drivers, see the appropriate ReadMe.pdf on the Excalibur Installation CD that
came with your board.
1.2.2 Board Installation
Installation of the DAS-429PCI/Mx board is similar to that of all PCI “Local
Bus” boards. The DAS-429PCI/Mx complies with the “Plug and Play”
specification of the PCI standard, and as such its absolute address is determined
by the BIOS at system start-up.
Warning Wear a suitably grounded electrostatic discharge wristband whenever
handling an Excalibur board.
To install the DAS-429PCI/Mx:
1. Make certain the computer power source is disconnected.
Insert the DAS-429PCI/Mx board into any PCI compatible slot.
2. Attach the mating connector (wired with the ARINC-429 connections) to
the board. The cables may be connected to and disconnected from the board
while power to the computer is turned on, but not while the board is
transmitting over the bus.
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Chapter 1 Introduction
DAS-429PCI/Mx: User’s Manual page 1 - 5
1.3 Memory Structure
There are two distinct areas of memory in the DAS-429PCI/Mx. The first area,
the PCI Configuration Space Header Region, is located in a fixed location in host
memory and contains all information necessary for the Plug and Play operation
of the board. The address of this region is fixed in the hardware.
The second area, the Control/Data Region, contains dual-port RAM and the
Control Registers used in setting up the board as a ARINC-429 interface. The
Control/Data Region is divided into five memory Pages (Pages 0-4). A Page is a
block of memory which has been assigned a unique base address by the Plug and
Play BIOS. The base address of each Page is determined by the BIOS following
power-up and is written into the Base Address Registers 0-4 located in the PCI
Configuration Space Header. The memory structure is shown below in
Figure 1-3.
Figure 1-3 DAS-429PCI/Mx Memory Structure
Note: Throughout this manual the following terms are used interchangeably:
Page 1 and Module 0
Page 2 and Module 1
Page 3 and Module 2
Page 4 and Module 3
Page 1/Module 0 refers to ARINC-429 Module 0
Page 2/Module 1 refers to the optional ARINC-429 Module 1
Page 3/Module 2 refers to the optional ARINC-429 Module 2
Page 4/Module 3 refers to the optional ARINC-429 Module 3
If you have the DAS-429PCI/M1, DAS-429PCI/M2 or DAS-429PCI/M3
boards, ignore references to the modules not included on your board.
See Chapter 6: Ordering Information for exact part numbers.
PCI Configuration Space
Header Region
256 bytes PCI Bus Plug and Play Parameters
Control/Data Region 64 bytes - Page 0 PCI Global Interrupt Control Registers
16K × 16 - Page 1 Module 0 (4 Rx and 2 Tx 429 channels)
16K ×16 - Page 2 Module 1 (4 Rx and 2 Tx 429 channels)
16K ×16 - Page 3 Module 2 (4 Rx and 2 Tx 429 channels)
16K ×16 - Page 4 Module 3 (4 Rx and 2 Tx 429 channels)
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Chapter 1 Introduction
page 1 - 6 Excalibur Systems
1.4 PCI Configuration Space Header
The DAS-429PCI/Mx includes a PCI Configuration Space Header, as required by
the PCI specification. The registers contained in this header enable software to
set up the Plug and Play operation of the board, and set aside system resources.
The PCI Configuration Space Header contents are stored in on-board
non-volatile memory (nvRAM), at the factory. You should not alter the contents
of the nvRAM. When you power-up, this ‘Boot-Load’ nvRAM is automatically
loaded into the PCI Configuration Space Header.
MAX_LAT MIN_GNT Interrupt Pin Interrupt Line 3C H
Reserved = 0s 38 H
Reserved = 0s 34 H
Expansion ROM Base Address (not used) 30 H
Reserved =0s 2C H
Reserved =0s 28 H
Base Address Register #5 (not used) 24 H
Base Address Register #4 (not used) 20 H
Base Address Register #3 (not used) 1C H
Base Address Register #2 (Control/Data Region Page 2) 18 H
Base Address Register #1 (Control/Data Region Page 1 14 H
Base Address Register #0 (Control/Data Region Page 0 10 H
BIST Header Type = 0 Latency Timer Cache Line Size 0C H
Class Code Rev ID 08 H
Status Register Command Register 04 H
Device ID Vendor ID 00 H
31 24 23 16 15 08 07 00
Figure 1-4 PCI Configuration Space Header
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Chapter 1 Introduction
DAS-429PCI/Mx: User’s Manual page 1 - 7
1.5 PCI Configuration Registers
This section describes the registers contained in the PCI Header Space.
The Vendor Identification register contains the PCI Special Interest Group
vendor identification number assigned to Excalibur Systems.
.
The Device Identification register contains the vendor assigned device
identification number.
1.5.1 Vendor Identification Register (VID) Address: 00–01 (H)
Power-up value 1405 H
Boot-load External nvRAM offset 040–41 H
Attribute Read Only
Size 16 bits
Bit Description
00-15 1405 H
1.5.2 Device Identification Register (DID) Address: 02–03 (H)
Power-up value 2000 H
Boot-load External nvRAM offset 042–43 H
Attribute Read Only
Size 16 bits
Bit Description
00-15 2000 H
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Chapter 1 Introduction
page 1 - 8 Excalibur Systems
The PCI Command register contains the PCI Command.
1.5.3 PCI Command Register Address: 04–05 (H)
Power-up value 0000 H
Boot-load Not used
Attribute Read/Write (R/W on bits 6, Read Only for all others)
Size 16 bits
Bit Bit Name Description
10-15 Reserved Set to 0s
09 Fast Back-to Back
Enable
Always set to 0
08 System Error Enable When set to 1, this bit permits the PCI Controller to drive
the open drain output pin, SERR#. This bit is cleared to 0
upon RESET#. The SERR# pin driven active normally
signifies a parity error on the address/control bus.
07 Wait Cycle Enable Always set to 1
06 Parity Error Enable When set to 1, this bit allows this controller to check for
parity errors. When a parity error is detected, the PCI bus
signal PERR# is asserted. This bit is cleared (parity
testing disabled) upon the assertion of RESET#.
05 Palette Snoop Enable Always set to 0
04 Memory Write and
Invalidate Enable
Always set to 0
03 Special Cycle Enable Always set to 0
02 Bus Master Enable Always set to 0
01 Memory Access Enable This bit allows the PCI Controller to decode and respond
as a target for memory regions that may be defined in one
of the three base address registers. This bit is initialized
to 0 upon the assertion of signal pin RESET#.
00 I/O Access Enable This bit allows the PCI Controller to decode and respond
as a target to I/O cycles which are to regions defined by
any one of the three base address registers. This bit is
initialized to 0 upon the assertion of signal pin RESET#.
PCI Command Register
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Chapter 1 Introduction
DAS-429PCI/Mx: User’s Manual page 1 - 9
The PCI Status register contains the PCI status information. Most status bits in
this register are designated as “write clear,” meaning that in order to clear a
given bit, the bit must be written as a 1. All bits written with a 0 are left
unchanged. These bits are identified below as (R/WC), while those which are
Read Only are shown as (RO).
1.5.4 PCI Status Register (PCISTS) Address: 06–07 (H)
Power-up value: 0080 H
Boot-load: Not used
Attribute: Read Only (RO), Read/Write Clear (RWC)
Size: 16 bits
Bit Bit Name Description
15 Detected Parity Error
(R/WC)
This bit is set whenever a parity error is detected. It functions
independently from the state of Command Register Bit 6. This bit
may be cleared by writing a 1 to this location.
14 Signaled System
Error (R/WC)
This bit is set whenever the device asserts the signal SERR#. This
bit can be reset by writing a 1 to this location.
13 Received Master
Abort (R/WC)
This bit is set whenever a bus master abort occurs. This bit can be
reset by writing a 1 to this location.
12 Received Target
Abort (R/WC)
This bit is set whenever this device has one of its own initiated
cycles terminated by the currently addressed target. This bit can be
reset by writing a 1 to this location.
11 Signaled Target
Abort (R/WC)
This bit is set whenever this device aborts a cycle when addressed
as a target. This bit can be reset by writing a 1 to this location.
09-10 Device Select
(DEVSEL#) Timing
Status (RO)
These bits are read-only and define the signal behavior of
DEVSEL# from this device when accessed as a target.
Bit 09 Bit 10 Description
0 0 Fast (PCI Controller)
0 1 Medium
10Slow
11Reserved
08 Data Parity Reported
(R/WC)
This bit is set upon the detection of a data parity error for a transfer
involving the PCI Controller as the master. The Parity Error Enable
bit (D6 of the Command Register) must be set in order for this bit to
be set. Once set, it can only be cleared by either writing a 1 to this
location or by the assertion of the signal RESET#.
07 Fast Back-to-Back
Capable (RO)
When equal to 1, this indicates that the device can accept fast
back-to-back cycles as a target.
00-06 Reserved (RO) Always returns 0s
PCI Status Register
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Chapter 1 Introduction
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The Revision Identification register contains the revision identification number
of the DAS-429PCI/Mx.
The Class Code register is divided into three one-byte fields, residing in the
following locations:
• Base class - 0B H
• Sub-class - 0A H
• Programming interface - 09 H
The Class Codes of the DAS-429PCI/Mx are set as indicated below:
1.5.5 Revision Identification Register (RID) Address: 08 (H)
Power-up value: 00 H
Boot-load: External nvRAM/EPROM offset 048 H
Attribute Read only
Size: 8 bits
Bit Description
00-07 Revision identification number
Revision Identification Register
1.5.6 Class Code Register (CLCD) Address: 09–-0B (H)
Power-up value: FF0000 H
Boot-load: External nvRAM offset 049–4B H
Attribute Read only
Size: 24 bits
Bit Address Fields Value Description
00-07 0B H Base Class 07H Simple communication controller
00-07 0A H Sub-Class 80H Other communications device
00-07 09 H Prog I/F 00H Register Level Programming Interface
Class Code Register
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Chapter 1 Introduction
DAS-429PCI/Mx: User’s Manual page 1 - 11
The Cache Line Size Register is hardwired to 0.
The Latency Timer register has meaning only for bus masters and therefore is
not used with the DAS-429PCI/Mx.
1.5.7 Cache Line Size Register (CALN) Address: 0C (H)
Power-up value: 00 H, hardwired
Boot-load: Not used
Attribute: Read only
Size: 8 bits
Bit Description
00-07 Cache Line Size (RO)
Cache Line Size Register
1.5.8 Latency Timer Register (LAT) Address: 0D (H)
Power-up value: 00 H
Boot-load: External nvRAM offset 04D H
Attribute: Read/Write bits 03–07; Read only bits
Size: 8 bits
Bit Bit Name Description
03-07 Latency Timer Value (R/W) Always set to 0
00–02 Always returns to 0
Latency Timer Register
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Chapter 1 Introduction
page 1 - 12 Excalibur Systems
The Header Type register consists of two fields:
Bits 00–06 define the format for bytes 10 H – 3F H of the device configuration
header
Bit 07 = 0 established that the PCI controller is a single function PCI device.
The Built-In Self-Test register is not implemented in the DAS-429PCI/Mx.
1.5.9 Header Type Register (HDR). Address: 0E (H)
Power-up value: 00 H
Boot-load: External nvRAM offset 04E H
Attribute: Read only
Size: 8 bits
Bit Description
07 0 PCI Controller is a single function PCI device
00–06 Always returns 0
Header Type Register
1.5.10 Built-In Self-Test Register (BIST) Address: 0F (H)
Power-up value: 00 H
Boot-load: External nvRAM/EPROM offset 04F H
Attribute:
Read only: bits 07 and 00–05
Write only: bit 06 as PCI bus
Size: 8 bits
Bit Bit Name Description
07 BIST Capable (RO) Always returns 0
06 Start BIST (WO) Always set to 0
04–05 Reserved Always returns 0
00–03 User Defined Completion
Code (RO)
Always returns 0
Built-in Self-Test Register
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Chapter 1 Introduction
DAS-429PCI/Mx: User’s Manual page 1 - 13
The Base Address Registers are used by the system BIOS to determine the
number, size and base addresses of memory pages required by the board, within
host address space.
The host determines the page base addresses by interrogating these registers
after BIOS power-up initialization. Bit zero of each field is used to select whether
the space required is to be decoded as memory (bit 00 = 0) or I/O (bit 00 = 1). The
absolute base addresses of these pages are determined from information written
back to the Base Address Registers, by the BIOS (see also “Determining Base
Address Size”).
Up to five memory pages are required by the DAS-429PCI/Mx: one for each
ARINC-429 module present and one for the PC Global Interrupt Control
Registers (see the table below).
Note: The contents of Base Address Register 0 are not loadable from nvRAM.
DETERMINING BASE ADDRESS SIZE
The address space defined by a given base address register is determined by
writing all 1s to a given base address register from the PCI bus and then reading
that register back. The number of 0s returned starting from D4 for memory space
and D2 for I/O space toward the high-order bits reveals the amount of address
space desired. The table below gives the required nvRAM/EPROM boot values
corresponding to Pages 1–4.
.
1.5.11 Base Address Registers (BADR) Address: 10, 14, 18, 1C, 20, 24 (H)
Power-up value: FFFFFFC1 H for offset 10 H; 00000000 H for all other registers
Boot-load: External nvRAM offset 50 H, 54 H, 58 H, 5C H, 60 H (BADRO–4)
Attribute: Read/Write: high bits; Read only: Low bits
Size: 32 bits
Register Offset Size Function
Base Address Register 0 (PAGE 0) 10H 64Byte PCI Global Interrupt Control Registers
Base Address Register 1 (PAGE 1) 14H 32Kb ARINC-429 Module 0
Base Address Register 2 (PAGE 2) 18H 32Kb ARINC-429 Module 1
Base Address Register 3 (PAGE 3) 1CH 32Kb ARINC-429 Module 2
Base Address Register 4 (PAGE 4) 20H 32Kb ARINC-429 Module 3
Base Address Registers Definitions
PAGE nvRAM Offset nvRAM Contents
PAGE 1 50 H FFFF8000 H
PAGE 2 54 H FFFF8000 H
PAGE 3 58 H FFFF8000 H
PAGE 4 5C H FFFF8000 H
Table 1-1 Address nvRAM/EPROM Boot Values
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