Excalibur Excalibur EPXA1 Quick user guide

MNL-EPXA1DEVBD-1.1
EPXA1 Development Board
101 Innovation Drive
San Jose, CA 95134
[phone]
http://www.altera.com
Hardware Reference Manual
September 2002
Version 1.1

ii Altera Corporation
EPXA1 Development Board Hardware Reference Manual
Copyright 2002 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all
other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera
products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights.
Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on
any published information and before placing orders for products or services. All rights reserved.

Altera Corporation iii
About this Manual
This manual provides comprehensive information about the Altera®
EPXA1 development board.
Table 1 shows the manual revision history.
How to Find
Information
■The Adobe Acrobat Find feature allows you to search the contents of
a PDF file. Click on the binoculars icon in the top toolbar to open the
Find dialog box.
■Bookmarks serve as an additional table of contents.
■Thumbnail icons, which provide miniature previews of each page,
provide a link to the pages.
■Numerous links, shown in green text, allow you to jump to related
information.
Table 1. Revision History
Date Description
August 2002 First publication
September 2002 Minor amendments

iv Altera Corporation
About this Manual EPXA1 Development Board Hardware Reference Manual
How to Contact
Altera
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at http://www.altera.com.
For technical support on this product, go to
http://www.altera.com/mysupport. For additional information about
Altera products, consult the sources shown in Table 2.
Note:
(1) You can also contact your local Altera sales office or sales representative.
Table 2. How to Contact Altera
Information Type USA & Canada All Other Locations
Technical support http://www.altera.com/mysupport/ http://www.altera.com/mysupport/
(800) 800-EPLD (3753)
(7:00 a.m. to 5:00 p.m.
Pacific Time)
[phone] (1)
(7:00 a.m. to 5:00 p.m.
Pacific Time)
Product literature http://www.altera.com http://www.altera.com
Altera literature services [e-mail] (1) [e-mail] (1)
Non-technical customer
service
[phone] [phone]
(7:30 a.m. to 5:30 p.m.
Pacific Time)
FTP site ftp.altera.com ftp.altera.com

Altera Corporation v
EPXA1 Development Board Hardware Reference Manual About this Manual
Typographic
Conventions
The EPXA1 Development Board Hardware Reference Manual uses the
typographic conventions shown in Table 3.
Table 3. Conventions
Visual Cue Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \QuartusII directory, d: drive, chiptrip.gdf file.
Bold italic type Book titles are shown in bold italic type with initial capital letters. Example:
1999 Device Data Book.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75
(High-Speed Board Design).
Italic type Internal timing parameters and variables are shown in italic type. Examples: tPIA, n+ 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title” References to sections within a document and titles of Quartus II Help topics are
shown in quotation marks. Example: “Configuring a FLEX 10K or FLEX 8000 Device
with the BitBlaster™Download Cable.”
Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix _n, e.g., reset_n.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\quartusII\qdesigns\tutorial\chiptrip.gdf. Also, sections
of an actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■Bullets are used in a list of items when the sequence of the items is not important.
The checkmark indicates a procedure that consists of one step only.
The hand points to information that requires special attention.
The angled arrow indicates you should press the Enter key.
The feet direct you to more information on a particular topic.

Notes:

Altera Corporation vii
Contents
About this Manual ..................................................................................iii
How to Find Information ............................................................................................................iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ............................................................................................................. v
EPXA1 Development Board ........................................................................9
Features .............................................................................................................................................9
Functional Overview .......................................................................................................................9
EPXA1 Development Board Components .................................................................................10
EPXA1 Device .........................................................................................................................10
Prototyping Area ....................................................................................................................11
Interfaces .................................................................................................................................13
Development Board Expansion ...........................................................................................20
Jumper Configuration ...................................................................................................................23
Clocks ...............................................................................................................................................24
Jumper Configuration for the Clock Inputs .......................................................................26
Sources for the Stripe Clock Reference ...............................................................................27
Sources for CLK3 & CLK4 ....................................................................................................28
Device Configuration ....................................................................................................................28
Booting from Flash Memory ................................................................................................28
Using the Quartus II Software .............................................................................................29
JTAG Interfaces ..............................................................................................................................29
Power Supply .................................................................................................................................30
Test Points & Test Pads .................................................................................................................32
Signals ..............................................................................................................................................33
UART .......................................................................................................................................33
Expansion Headers ................................................................................................................34
Configuration/Debugging Interfaces .................................................................................37
Development Board Pin-Outs ......................................................................................................38
Configuration .........................................................................................................................39
SDR SDRAM Interface ..........................................................................................................40
EBI ............................................................................................................................................42
UART1 & UART2 ...................................................................................................................44
Fast I/O Pins ...........................................................................................................................44
Test Points ...............................................................................................................................45
Test Pads ..................................................................................................................................45
Prototyping Area ....................................................................................................................46
Expansion Header I/O Pins .................................................................................................47
General Usage Guidelines ............................................................................................................48

viii Altera Corporation
Contents Excalibur EPXA1 Development Board Hardware Refewrence Manual
Anti-Static Handling ..............................................................................................................48
Power Consumption ..............................................................................................................48
Test Core Functionality .........................................................................................................49
Unused I/O Pins ....................................................................................................................50

Altera Corporation 9
Specifications
1
EPXA1 Development Board
Features ■Powerful development board for embedded processor FPGA designs
–Features an EPXA1F484 device
–Supports intellectual property-based (IP-based) designs using a
microprocessor
■Industry-standard interconnections
–10/100 megabits per second (Mbps) Ethernet
–Two RS-232 ports
■Memory subsystem
–8 Mbytes of flash memory
–32 Mbytes of single data rate (SDR) SDRAM
■Multiple clocks for communications system design
■Multiple ports for configuration and debugging
–IEEE Std. 1149.1 Joint Test Action Group (JTAG)
–Support for configuring the EPXA1 device using flash memory,
with a MasterBlaster™or ByteBlasterMV™cable
–Multi-ICE header for debugging
■Expansion headers for greater flexibility and capacity
–5-V standard expansion header
–5-V long expansion card header
■Additional user-interface features
–One user-definable 8-bit dual in-line package (DIP) switch block
–Four user-definable push-button switches, plus reset switch
–Ten user-definable LEDs, plus function-specific LEDs
■Test points provided to facilitate system development
Functional
Overview
The EPXA1 development board is a powerful, low-cost, product which
you can use as a desktop hardware platform to start developing
embedded systems immediately. In addition, the board can be used for
system prototyping, emulation, hardware and software development or
other special requirements. The development board provides a flexible,
powerful debug and development environment to support the
development of systems using Excalibur™devices.

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EPXA1 Development Board Hardware Reference Manual
EPXA1
Development
Board
Components
This section describes the components on the EPXA1 development board,
which is shown in Figure 1.
Figure 1. EPXA1 Development Board Layout
EPXA1 Device
The EPXA1 development board features the lowest-cost member of the
Excalibur family, the EPXA1. The EPXA1 device contains an ARM922T™
32-bit RISC microprocessor combined with an APEX™20KE FPGA in a
484-pin FineLine BGA™package.
Table 1 on page 10 lists the main features of the device.
Table 1. EPXA1 Device Features
Feature Capacity
Maximum system gates 263,000
Typical gates 100,000
LEs 4,160
ESBs 26
Maximum RAM bits 53,248
Maximum macrocells 416
Maximum user I/O pins 186

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EPXA1 Development Board Hardware Reference Manual
In addition, the EPXA1 device provides a variety of peripherals, as listed
in Table 2.
Refer to the Excalibur Devices Hardware Reference Manual for details about
EPXA1 devices.
Prototyping Area
This area can be used to develop and test custom circuitry, such as I/O
interfaces, using the EPXA1 development board. The prototyping area has
both 3.3-V and 5-V supply, plus ground connections, 32 I/O pins that
facilitate connection to the Excalibur device, and a reset pin in a 6 ×15
matrix. Figure 2 shows the prototyping area on the development board.
Table 2. EPXA1 Device Peripherals
Peripheral Description
ARM922T 32-bit RISC processor For speed grade –1: up to 200 MHz
For speed grade –2: up to 166 MHz
Interrupt controller Used for the interrupt system
Internal single-port SRAM 32 Kbytes
Internal dual-port SRAM 16 Kbytes
SDRAM controller Interfaces between the internal system bus and SDRAM
External SDRAM Refer to the Excalibur Devices Hardware Reference Manual for details of
supported sizes
Expansion bus interface (EBI) Interfaces to the flash memory and the Ethernet
External flash memory Refer to the Excalibur Devices Hardware Reference Manual for details of
supported sizes
Watchdog timer Protects the system against software failure
UART Facilitates serial communication
Reset controller Resets the device

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EPXA1 Development Board Hardware Reference Manual
Figure 2. Prototyping Area on the EPXA1 Development Board
Figure 3 on page 13 shows how the pins are located in the prototyping
area.
A1

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EPXA1 Development Board Hardware Reference Manual
Figure 3. Pin Layout in the Prototyping Area
See Table 37 on page 46 for details of the prototyping area pin-outs.
Interfaces
Table 3 lists the interfaces supported by the EPXA1 development board.
5V
GND
3.3 V
RESET_n
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
PROTOIO_n
NC
Table 3. Development Board Interfaces
Interface Description
10/100 Ethernet with full- and half-
duplexing
This interface consists of an RJ45 connector and transformer
connected to the EPXA1 using an external MAC/PHY device connected
to the EBI
Expansion headers These headers are used to connect Altera daughter cards or customer-
designed daughter cards to develop and test custom circuitry
IEEE Std. 488 RS-232 serial interfaces This is a 250-kbps true RS-232 data terminal equipment (DTE) interface
Debugging/programming ports The board supports in-circuit debugging by means of the MasterBlaster,
ByteBlasterMV, or Multi-ICE cables

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EPXA1 Development Board Hardware Reference Manual
Serial I/O Interfaces
There can be two UARTs in the EPXA1 device. A dedicated UART is
located in the embedded stripe; optionally, an additional IP UART can be
implemented in the FPGA. If the IP UART is used, it is connected to 3.3-V
standard EPXA1 I/O pins. Each UART is connected to a transceiver (U6
for the embedded stripe UART and U1 for the IP UART) to translate
LVTTL voltage for RS-232 compatibility at up to 250 Kbps. Each UART
also has its own DB9 male RS-232 connector wired as a DTE.
The transceiver uses a 3.3-V power supply. If the RS-232 input
pins are used as outputs, contention occurs because the bus
transceiver is always active. If these pins are not used as part of
a design, ensure that they remain in the high-impedance state.
All unused I/O pins can be set to tri-state mode in the Quartus II
software (see “Unused I/O Pins”on page 50).
See Table 23 on page 33 for information on the RS-232 signals.
Table 4 shows the UART interface characteristics.
Table 5 lists the UART LEDs on the EPXA1 development board.
Table 4. UART Interface Characteristics
Features I/O Pins Voltage (V)
UART 1 TX, RX & Control 8 3.3
UART 2 TX, RX & Control 8 3.3
Table 5. UART LEDs
Board
Reference
Signal Description
D2 TXD This LED indicates activity on the line
D3 RXD This LED indicates activity on the line
D4 XA-TXD This LED indicates activity on the line
D7 XA-RXD This LED indicates activity on the line

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EPXA1 Development Board Hardware Reference Manual
10/100 Ethernet Parallel Interface
On the EPXA1 development board, the Ethernet interface consists of an
integrated MAC/PHY device and an RJ45 connector which includes the
transformer and LEDs.
Table 6 lists the LEDs built into the RJ45 connector.
Note:
(1) Although the default setting for LEDA ‘10/100 link detected’, the user can program
the LEDA and LEDB select signals by writing to the LED select signal registers.
The Ethernet and flash memory device share addresses and data on the
EBI.
Memory Interfaces
The EPXA1 development board supports the following types and
capacities of on-board memory, as listed in Table 7.
Figure 4 on page 16 shows the location of the on-board memory.
Table 6. Ethernet LEDs
Board Reference Signal Description
RJ1 LEDA LEDA Green LED. This defaults to being set on when the
10/100 link is detected (1)
RJ1 LEDB LEDB Unused (1)
Table 7. Development Board Memory Characteristics
Type Address Lines Data Lines Control Lines Memory Organization Size
SDR SDRAM 13 16 10 4 M ×16 ×4 banks 32 Mbytes; 16-bit
Flash 22 16 5 2 ×4 Mbytes 8 Mbytes

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EPXA1 Development Board Hardware Reference Manual
Figure 4. EPXA1 Development Board On-Board Memory
Two flash memory chips, FLASH1 and FLASH2, are connected to the EBI
of the EPXA1 development board (see Figure 5).
Figure 5. Flash Memory Interface
SDRAM (pin 1 indicated)Flash memory (pin 1s indicated)
EPXA1
EBI
A1-A22
D0-D15
OE, WE, CE
A0-A21
Flash Memory (2 x 4 Mbyte)
EBI_CS0 EBI_CS1
FLASH1 FLASH2 PHY/MAC

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EPXA1 Development Board Hardware Reference Manual
LED & Switch Interfaces
The EPXA1 development board provides a variety of LED and switch
interfaces. Some are user-definable and some are function-specific.
Figure 6 shows the location of LEDs and switches on the development
board.
Figure 6. Switches & LEDs on the EPXA1 Development Board
User-Defined LEDs
On the EPXA1 development board, there are ten user-definable LEDs in a
graph-type LED package, DG1. They connect directly to the EPXA1 device
I/O pins and can be used for any kind of application.
Table 8 on page 18 lists the user LEDs on the development board.
Ethernet
TX/RX LEDs
UART LEDs
NPOR
SOFT_RESET_N
SW6 (pin 1 indicated)
Voltage LEDs User LEDs (LED 0 indicated)
Push-button switches
SW2, SW3, SW4, SW5

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EPXA1 Development Board Hardware Reference Manual
Function-Specific LEDs
LEDs are also used for specific application functions, such as the
configuration, RS-232 and Ethernet interfaces. Table 9 lists the function-
specific LEDs, their power supply status, their connection details, and
their functions.
Table 8. DG1 LED Interface Characteristics
LED Reference EPXA1 I/O Pin Signal Voltage (V)
DG1_J W17 USER_LED9 3.3
DG1_I W18 USER_LED8 3.3
DG1_H W20 USER_LED7 3.3
DG1_G W21 USER_LED6 3.3
DG1_F W22 USER_LED5 3.3
DG1_E Y17 USER_LED4 3.3
DG1_D Y18 USER_LED3 3.3
DG1_C Y19 USER_LED2 3.3
DG1_B Y20 USER_LED1 3.3
DG1_A Y21 USER_LED0 3.3
Table 9. Function-Specific LED Usage
Signal Board Reference EPXA1 I/O Pin
(or Board
Connector)
Description Voltage (V)
INIT_DONE D15 K7 Used by FPGA initialization; signifies
that initialization is complete
3.3
VCC_5V D12 5-V power indicator 5
VCC_3V3 D13 3.3-V power indicator 3.3
VCC_1V8 D14 1.8-V power indicator 1.8
TXD D2 FPGA UART signal indicator 3.3
RXD D3 FPGA UART signal indicator 3.3
XA-TXD D4 Embedded stripe UART signal indicator 3.3
XA-RXD D7 Embedded stripe UART signal indicator 3.3
TX RJ1 Ethernet signal indicator 3.3
RX RJ1 Ethernet signal indicator 3.3

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EPXA1 Development Board Hardware Reference Manual
Switch Interfaces
The EPXA1 development board provides eight user-definable, active-low
switches in a dip-switch block, four debounced push-button switches, and
two dedicated reset switches. Table 10 documents the interface
characteristics of the dip-switch block, SW6.
Tables 11 and 12 detail the push-button switches on the development
board.
Table 10. SW6 Dip Switch Connections (Active-Low)
Switch Name EPXA1 I/O Pin Signal Voltage (V)
SW6_1 V20 USER_SW7 3.3
SW6_2 V19 USER_SW6 3.3
SW6_3 V18 USER_SW5 3.3
SW6_4 V17 USER_SW4 3.3
SW6_5 V16 USER_SW3 3.3
SW6_6 U21 USER_SW2 3.3
SW6_7 U20 USER_SW1 3.3
SW6_8 U19 USER_SW0 3.3
Table 11. Push-Button Switches
Push Button EPXA1 I/O
Pin
Signal Use Voltage
(V)
SW1 H1 NPOR Active-low switch that generates a full power-on reset
when pressed for more than two seconds
3.3
SW7 R4 N_CONFIG Active-low switch that generates a warm reset 3.3
Table 12. User-Definable Push-Button Switches
Push Button EPXA1 I/O Pin Signal Voltage (V)
SW2 U18 USER_PB0 3.3
SW3 U17 USER_PB1 3.3
SW4 U16 USER_PB2 3.3
SW5 T18 USER_PB3 3.3

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EPXA1 Development Board Hardware Reference Manual
Development Board Expansion
The EPXA1 development board hosts the EPXA1 device and two 5-V
expansion headers, which are implemented on the board for use with
expansion cards. There are two types of expansion header on the EPXA1
development board:
■Standard expansion header—a set of three 0.1-inch, two-row header
pins (7 ×2, 10 ×2, 20 ×2)
■Long expansion header—the same set of three 0.1-inch, two-row
header pins (7 ×2, 10 ×2, 20 ×2) plus an extra 20 ×2 header pins
Figure 7 on page 20 shows the location of the expansion headers on the
EPXA1 development board.
Figure 7. EPXA1 Development Board Expansion Header Connectors
The expansion header interfaces can be used to interface to special-
function daughter cards; contact your Altera representative for details of
the daughter cards available for use with the expansion header interfaces.
By using the EPXA1 I/O pins and the power-supply pins on the
expansion headers, you can design expansion cards to your specific
requirements using the I/O pins on the EPXA1 device and power supplies
from the EPXA1 development board.
Pin 1
Pin 1