Explore EP9134 User manual
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User Guide — EP9134_UG V0.7
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1
4 Ports HDMI 1.3 Splitter
EP9134
User Guide
V0.7
Original Release Date: Aug. 27, 2007
Explore
Revised: Nov. 23, 2009
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2
Revision History
Version
Number
Revision
Date Author Description of Changes
0.0 Aug/27/2007 Jerry Chen Initial Version
0.1 Jan/11/2008 Ether Lai Revised Version
0.2 Mar/14/2008 Ether Lai Revise Register Description; Change package type;
0.3 May/08/2008 Ether Lai Revise Register Description; Revise Pin Definition; Revise Power Consumption;
Change package type to E-PAD LQFP;
0.4 Jul/23/2009 Ether Lai
Remove redundant register descriptions;
Clarify HDMI version -- specification and CTS;
Revise Package Diagram;
0.5 Aug/18/2009 Ether Lai Revise Package Diagram to E-PAD;
0.6 Oct/23/2009 Ether Lai Fix Typo in EXT_SWING pin descriptions;
0.7 Nov/23/2009 Ether Lai
Fix Typo in DC Analogue Specification and Figure 2-3;
Fix typo in section 3.1, section 3.2.1, section 3.3.1.7 and table 3-1;
Revise the thermal resistance;
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3
Section 1 Introduction
1.1 Overview
The EP9134 is a 4-Port DVI/HDMI splitter with integrated HDCP decryption/encryption engines and is
compliant with HDMI Rev 1.3a and HDCP Rev 1.2 specifications. The EP9134 receives DVI/HDMI
inputs, process HDCP decryption and encryption and transmits the data to 4 DVI/HDMI ports. The chip
uses an external EE to store the encrypted HDCP receiver/transmitter keys.
1.2 Features
• DVI Specification 1.0 Compliant
• Compliant with HDMI 1.3a specification and HDMI 1.3c Compliance Test Specification (CTS)
• Integrated HDCP decryption/encryption engines which are compliant with HDCP Rev 1.2
specification
• Encrypted HDCP keys store in external serial EE
• Wide Frequency Range: 25MHz - 225MHz
• Support 12-bit Deep Color up to 1080p
• Supports 1 DVI/HDMI input port and 4 DVI/HDMI output ports
• Supports conversion of HDMI signaling to DVI signaling
• Supports HDCP Repeater
• Cascadable to make more than 4 output ports
• 128-Pin E-PAD LQFP (Pb-Free)
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Section 2 Overview
2.1 Block Diagram
Figure 2-1 Block Diagram
SDA1
SCL1
EXT_RSTb
IIC Slave
Registers
&
Logics
DVI/HDMI
Receiver
EXT_SWING
HDCP Keys
RX0+/-
RX1+/-
RX2+/-
RXC+/-
DVI/HDMI
Transmitter
SDA3
SCL3 IIC Slave
SDA2
SCL2 IIC Master
HDCP Keys DVI/HDMI
Transmitter
HDCP Keys
TX00+/-
TX10+/-
TX20+/-
TXC0+/-
TX01+/-
TX11+/-
TX21+/-
TXC1+/-
HDCP Keys
DVI/HDMI
Transmitter HDCP Keys DVI/HDMI
Transmitter
TX02+/-
TX12+/-
TX22+/-
TXC0+/-
TX03+/-
TX13+/-
TX23+/-
TXC1+/-
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2.2 Pin Diagram
Figure 2-2
reserved 32
VSSE 31
VDDE 30
SDA2 29
SCL2 28
SDA1 27
SCL1 26
VSS 25
VDD18 24
EXT_RSTb 23
A2 22
A1 21
A0 20
VSS 19
VSS 18
VDD18 17
VDD18 16
AVSS 15
AVSS 14
TX22+ 13
TX22- 12
AVDD 11
TX12+ 10
TX12- 9
AVSS 8
AVSS 7
TX02+ 6
TX02- 5
AVDD 4
TXC2+ 3
2TXC2-
1
AVSS
EXT_SWING01
64
PVDD
63
PVSS
62
AVSS
61
AVSS
60
TX21+
59
TX21-
58
AVDD
57
TX11+
56
TX11-
55
AVSS
54
AVSS
53
TX01+
52
TX01-
51
AVDD
50
TXC1+
49
TXC1-
48
AVSS
47
AVSS
46
VSS
45
VSS
44
VDD18
43
VDD18
42
HTPLG3
41
AVDD
71
72
73
TX10+74
75
AVSS
76
AVSS
77
PVSS
78
PVDD
79
EXT_RES
80
AVDD
81
RXC-
82
RXC+
83
AVSS
84
RX0-
85
86
RX0+
87
AVSS
88
89
AVDD90
AVSS91
RX1-92
RX1+93
AVDD94
RX2-95
RX2+96
AVSS97
_AVSS98
_AVSS99
_AVSS100
_AVSS101
_AVSS102
103
104
105
106
107
108
109
110
111
112
113
114
TX03+
115
AVSS
116
AVSS
117
TX13-
118
TX13+
119
AVDD
120
AVDD
121
TX23-
122
TX23+
123
AVSS
124
AVSS
125
PVSS
126
127
128
PVSS
PVDD
PVDD
EXT_SWING23
AVSS
HTPLG2
40
TX10-
AVSS
AVSS
TX20+
TX20-
39
AVSS
_AVSS
_AVSS
AVSS
AVSS
TXC3-
TXC3+
AVDD
AVDD
TX03-
reserved 33
SCL3 34
SDA3 35
M0_RDY 36
HTPLG0 37
HTPLG1 38
70 TX00+
69 TX00-
68 AVDD
67 TXC0+
66 TXC0-
65 AVSS
Pin Diagram
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2.3 Pin Description
Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open.
Table 2-1 IIC Pins
NAME IN /
OUT DESCRIPTION
SCL1 IN IIC SCL signal for receiver port DDC
SDA1 IO IIC SDA signal for receiver port DDC (open drain)
SCL2 OUT IIC SCL signal for EE interface (open drain)
SDA2 IO IIC SDA signal for EE interface (open drain)
SCL3 IN IIC SCL signal for internal registers access
SDA3 IO IIC SDA signal for internal registers access (open drain)
A2, A1, A0 IN Determine the lowest 3-bit of the IIC address for IIC Port 3 (SCL3/SDA3)
Table 2-2 Misc. Pins
NAME IN /
OUT DESCRIPTION
EXT_RSTb IN External Reset (Active LOW). A HIGH level indicates normal operation and a
LOW level causes all the logic on the chip to be reset.
M0_RDY OUT HDCP M0 Ready Signalling Output. This pin is set to HIGH while the AKSV is
written to receiver.
reserved IN Must be tied LOW for normal operation.
Table 2-3 Receiver Pins
NAME IN /
OUT DESCRIPTION
RX0-
RX0+
RX1-
RX1+
RX2-
RX2+
Analog
Differential Data Input Pairs for receiver port
RXC-
RXC+ Differential Clock Input Pairs for receiver port
EXT_RES Analog DVI/HDMI External Termination Resistor.
Table 2-4 Transmitter Pins
NAME IN /
OUT DESCRIPTION
TX00-
TX00+
TX10-
TX10+
TX20-
TX20+
Analog
Differential Data Output Pairs for transmitter port 0
TXC0-
TXC0+ Differential Clock Output Pairs for transmitter port 0
HTPLG0 IN
Hot Plug Input
This pin is used to monitor the "HOT PLUG" signal for transmitter port 0. Note:
This input is only 3.3V tolerant and has no internal debouncer circuit.
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TX01-
TX01+
TX11-
TX11+
TX21-
TX21+
Analog
Differential Data Output Pairs for transmitter port 1
TXC1-
TXC1+ Differential Clock Output Pairs for transmitter port 1
HTPLG1 IN
Hot Plug Input
This pin is used to monitor the "HOT PLUG" signal for transmitter port 1. Note:
This input is only 3.3V tolerant and has no internal debouncer circuit.
EXT_SWING01 Analog Voltage Swing Adjust for Port 0/1. A resistor should tie this pin to AVDD. This
resistance determines the amplitude of the voltage swing.
TX02-
TX02+
TX12-
TX12+
TX22-
TX22+
Analog
Differential Data Output Pairs for transmitter port 2
TXC2-
TXC2+ Differential Clock Output Pairs for transmitter port 2
HTPLG2 IN
Hot Plug Input
This pin is used to monitor the "HOT PLUG" signal for transmitter port 2. Note:
This input is only 3.3V tolerant and has no internal debouncer circuit.
TX03-
TX03+
TX13-
TX13+
TX23-
TX23+
Analog
Differential Data Output Pairs for transmitter port 3
TXC3-
TXC3+ Differential Clock Output Pairs for transmitter port 3
HTPLG3 IN
Hot Plug Input
This pin is used to monitor the "HOT PLUG" signal for transmitter port 3. Note:
This input is only 3.3V tolerant and has no internal debouncer circuit.
EXT_SWING23 Analog Voltage Swing Adjust for Port 2/3. A resistor should tie this pin to AVDD. This
resistance determines the amplitude of the voltage swing.
Table 2-5 Power and Ground Pins
NAME IN /
OUT DESCRIPTION
VDDE PWR Digital Power, 3.3V
VSSE GND Digital Ground
VDD18 PWR Core Power, 1.8V
VSS GND Core Ground
AVDD PWR Analog Power, 3.3V
AVSS GND Analog Ground
PVDD PWR Analog Power for PLL, 3.3V
PVSS GND Analog Ground for PLL
Table 2-4 Transmitter Pins
NAME IN /
OUT DESCRIPTION
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_AVSS GND Analog Ground
Table 2-5 Power and Ground Pins
NAME IN /
OUT DESCRIPTION
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2.4 Electrical Characteristics
Absolute Maximum Conditions
Symbol Parameter Min Typ Max Units
Vcc33 3.3V Supply Voltage -0.3 4.0 V
Vcc18 1.8V Supply Voltage -0.3 2.5 V
VIInput Voltage -0.3 Vcc + 0.3 V
VOOutput Voltage -0.3 Vcc + 0.3 V
TJJunction Temperature 125 qC
TSTG Storage Temperature -40 125 qC
TJA Thermal Resistance (Junction to Ambient) 43 qC/W
TJC Thermal Resistance (Junction to Case) 6 qC/W
1 Permanent device damage may occur if absolute maximum conditions are exceeded.
2 Functional operation should be restricted to the conditions described under Normal Operating Conditions.
Normal Operating Conditions
Symbol Parameter Min Typ Max Units
Vcc33 3.3V Supply Voltage 3.14 3.3 3.6 V
Vcc18 1.8V Supply Voltage 1.71 1.8 1.98 V
VCCN Supply Voltage Noise1-0.3 100 mVp-p
TAAmbient Temperature (with power applied) 0 25 70 qC
1 Guaranteed by design.
DC Digital I/O Specifications (under normal operating conditions unless otherwise specified)
Symbol Parameter Conditions Min Typ Max Units
VIH High-level Input Voltage 2.0 V
VIL Low-level Input Voltage 0.8 V
VOH High-level Output Voltage 2.4 V
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DC Analogue Specifications (under normal operating conditions unless otherwise specified)
Symbol Parameter Conditions Min Typ Max Units
VOD
Differential Voltage
Single ended peak to peak amplitude
RLOAD = 50 ohm
REXT_SWING = 182 ohm 510 550 590 mV
VDOH Differential High-level Output Voltage1AVDD V
IDOS Differential Output Short Circuit Current VOUT = 0V; TX_TERM bit is 0 5 uA
IPD Power-Down Current225qC Ambient
3V3 2 mA
1V8 1 mA
ICCD
Supply Current
(25qC Ambient, TX0/TX1/TX2/TX3 are Active
REXT_RES = 511 ohm, REXT_SWING = 182 ohm,
TX_TERM bit is 1)
1080p Resolution (8-bit)
3V3 579 mA
1V8 110 mA
1080p Resolution (12-bit)
3V3 633 mA
1V8 161 mA
1 Guaranteed by design.
2 Assumes all HDMI/DVI I/O ports are not connected and all digital inputs are silent.
Receiver AC Specifications (under normal operating conditions unless otherwise specified)
Symbol Parameter Conditions Min Typ Max Units
TDPS Intra-Pair (+ to -) Differential Input Skew
1. Guaranteed by design.
10.4 Tbit
TCCS Channel to Channel Differential Input Skew11.0 Tpixel
TIJIT Differential Input Clock Jitter Tolerance2,3
2. Jitter defines as per DVI 1.0 Specification, Section 4.6 Jitter Specification.
3. Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electronical Measurement Procedures
0.3 Tbit
TPDL
Delay from OUT_EN Low to High Impedance
outputs 10 ns
THSC Link Disabled (Tx power down) to LINK_ON Low4250 ms
TFSC Link Enabled (DE Active) to LINK_ON High125 40 DE
edges
VOL Low-level Output Voltage 0.4 V
IOL Output Leakage Current High Impedance -10 10 uA
VID Differential Input Voltage 150 1000 mV
NOTES:
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Transmitter AC Specifications (under normal operating conditions unless otherwise specified)
Symbol Parameter Conditions Min Typ Max Units
SLHT Differential Swing Low-to-High Transition Time
CLOAD = 5pF,
RLOAD = 50 ohm,
REXT_SWING = 300 ohm
170 200 230 ps
SHLT Differential Swing High-to-Low Transition Time
CLOAD = 5pF,
RLOAD = 50 ohm,
REXT_SWING = 300 ohm
170 200 230 ps
Figure 2-3 Differential Output Timing Definition
SLHT SHLT
80% VOD
20% VOD
AVDD
TX+
TX-
5pF
50ohm
VOD = ABS{(TX+) - (TX-)}
4. Measured when transmitter was powered down.
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Section 3 Detail Functional Descriptions
3.1 General
The chip provides an IIC (SCL3/SDA3) serial bus interface to communicate with the host. The IIC address
for this slave IIC interface is "0111_A2_A1_A0_x" (where x=1 for read and x=0 for write). A2, A1 and A0
are programmable by pins
3.2 IIC Interface
The IIC bus interface uses a Serial Data line (SDA at pin SDA3) and a Serial Clock Line (SCL at pin SCL3)
for data transfer. The chip acts as a slave for receiving and transmitting data over the serial interface. All
devices connected to the IIC bus must have open drain or open collector outputs. Logic AND function is
exercised on both lines with external pull-up resistors, the value of these resistors is system dependent.
When the serial interface is not active, the logic levels on SCL and SDA are pulled HIGH by external
pull-up resistors.
Data received or transmitted on the SDA line must be stable at the positive edge of SCL. If the SDA changes
state while SCL is HIGH, the IIC interface interprets that action as a START or STOP sequence. Data on
SDA must change only when SCL is LOW.
The standard IIC traffic protocol is illustrated in the following Figure:
Figure 3-1 IIC Bus Transmission Protocol
SCL
SDA
Start
Signal
Ack
Bit
12345678
MSB LSB
12345678
MSB LSB
Stop
Signal
No
SCL
SDA
1234567 8
MSB LSB
12 5 678
MSB LSB
Repeated
34
9 9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0
Calling Address Read/ Data Byte
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
New Calling Address
99
XX
Ack
Bit
Write
Start
Signal
Start
Signal
Ack
Bit
Calling Address Read/
Write
Stop
Signal
No
Ack
Bit
Read/
Write
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3.2.1 Basic Protocol
For EP9134, there are six components to serial bus operation:
• START Signal
• Slave Address Byte
• Base Register Address Byte
• Data Byte for Read/Write
• STOP Signal
• Repeated Start Signal
When the serial interface is inactive (SCL and SDA are HIGH), communication are initiated by a START
signal which is a HIGH-to-LOW transition on SDA while SCL is HIGH. The first eight bits of data
transferred after a START signal comprising a seven bit slave address (the seven MSB bits) and a single
R/W bit (the LSB bit). The R/W bit indicates the direction of data transfer, "1" means read from device and
"0" means write to device. If the transmitted slave address matches the address of the device, the EP9134
sends the acknowledge by asserting SDA Low on the ninth SCL pulse. Else, the EP9134 does not assert the
acknowledge.
Writing data to specific control registers of the chip requires that the 8-bits address of the control register
is written after the slave address has been acknowledged. This control register address is the base address
for the subsequent write operations. The base address auto-increments by one for each byte of data written
after the data byte intended for the base address. The acknowledge bit will be sent on the ninth SCL pulse
after every 8-bits data received.
Data are read from the control registers of the chip in a similar manner. Reading requires two data transfer
operations:
The base address must be written with the R/W bit of the slave address byte LOW to set up a
sequential read operation.
Reading (the R/W bit of the slave address byte HIGH) begins at the previously established base
address. The address of the read register auto-increments after each byte is transferred.
To terminate a read/write sequence to the chip, a STOP signal must be sent. A STOP signal comprises a
LOW-to-HIGH transition of SDA while SCL is HIGH.
A repeated start signal occurs when the master device driving the serial interface generates a START signal
without first generating a STOP signal to terminate the current read/write sequence. This can be used to
change the mode of communication (read, write) between the slave and master without releasing the bus.
3.2.2 Examples of the read/write sequence
Write to One Control Register
• START Signal
• Slave Address Byte (R/W bit = LOW)
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• Base Address Byte
• Data Byte to Base Address
• STOP Signal
Write to Multiple Control Registers
• START Signal
• Slave Address Byte (R/W bit = LOW)
• Base Address Byte
• Data Byte to Base Address
• Data Byte to (Base Address + 1)
• Data Byte to (Base Address + 2)
• ...................................................
• Data Byte to (Base Address + N)
• STOP Signal
Read from One Control Register
• START Signal
• Slave Address Byte (R/W bit = LOW)
• Base Address Byte
• Repeated START Signal
• Slave Address Byte (R/W = HIGH)
• Data Byte from Base Address
• STOP Signal
Read from Multiple Control Registers
• START Signal
• Slave Address Byte (R/W bit = LOW)
• Base Address Byte
• Repeated START Signal
• Slave Address Byte (R/W = HIGH)
• Data Byte from Base Address
• Data Byte from (Base Address + 1)
• Data Byte from (Base Address + 2)
• .......................................................
• Data Byte from (Base Address + N)
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• STOP Signal
3.3 Description of the Control Registers
The following table shows all the control registers of the DVI/HDMI Transmitter EP9134:
Table 3-1 IIC Control Registers
Addr Mode Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RESET
$05 R/W - - TMDS_SAMP[5:0] 05h
$06 R/W TX_TERM DPRE_EM TX_BW TX_PEAK CPRE_EM RX_EQ RX_BW RX_TERM 00h
$07 R/W RX_LINK_ON RX_DE_ON RX_HDMI RX_ENC_ON RX_PU - TX_SEL[1:0] 08h
$08 R/W TX_MUTE RX_VSYNC --- -
TX_ENC_OPT TX_PU 01h
$09 R -- - - - TX_RSEN TX_HTPLG -00h
$0A R/W DK[3:1] DKEN ----80h
$0E R/W -- - - - - TX_EESS TX_HDMI 01h
$0F R/W TX_AKSV_RDY TX_ENC_ON -TX_RPTR --
TX_RI_RDY TX_ENC_EN 00h
$10 R/W TX_BKSV_1 XXh
$11 R/W TX_BKSV_2 XXh
$12 R/W TX_BKSV_3 XXh
$13 R/W TX_BKSV_4 XXh
$14 R/W TX_BKSV_5 XXh
$15 R/W TX_AN_1 XXh
$16 R/W TX_AN_2 XXh
$17 R/W TX_AN_3 XXh
$18 R/W TX_AN_4 XXh
$19 R/W TX_AN_5 XXh
$1A R/W TX_AN_6 XXh
$1B R/W TX_AN_7 XXh
$1C R/W TX_AN_8 XXh
$1D R TX_AKSV_1 XXh
$1E R TX_AKSV_2 XXh
$1F R TX_AKSV_3 XXh
$20 R TX_AKSV_4 XXh
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$21 R TX_AKSV_5 XXh
$22 R TX_RI_1 XXh
$23 R TX_RI_2 XXh
$25 R TX_M0_1 XXh
$26 R TX_M0_2 XXh
$27 R TX_M0_3 XXh
$28 R TX_M0_4 XXh
$29 R TX_M0_5 XXh
$2A R TX_M0_6 XXh
$2B R TX_M0_7 XXh
$2C R TX_M0_8 XXh
$40R00000 00
RX_M0_RDY 00h
$41 R RX_M0_1 XXh
$42 R RX_M0_2 XXh
$43 R RX_M0_3 XXh
$44 R RX_M0_4 XXh
$45 R RX_M0_5 XXh
$46 R RX_M0_6 XXh
$47 R RX_M0_7 XXh
$48 R RX_M0_8 XXh
$50 W RX_Bcaps 91h
$51 W RX_Bstatus[7:0] 00h
$52 W - - - - RX_Bstatus[11:8] 00h
$60 W RX_SHA-1_HASH_0 XXh
$61 W RX_SHA-1_HASH_1 XXh
$62 W RX_SHA-1_HASH_2 XXh
$63 W RX_SHA-1_HASH_3 XXh
$64 W RX_SHA-1_HASH_4 XXh
$65 W RX_SHA-1_HASH_5 XXh
$66 W RX_SHA-1_HASH_6 XXh
$67 W RX_SHA-1_HASH_7 XXh
$68 W RX_SHA-1_HASH_8 XXh
$69 W RX_SHA-1_HASH_9 XXh
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3.3.1 Register Descriptions
Detailed usage of these IIC registers is described in the following section.
3.3.1.1 TMDS Control Register 0
Table 3-2 TMDS Control Register 0
$05
bit 7 6 5 4 3 2 1 0
R00 TMDS_SAMP[5:0]
W
Reset: 0 0 0 0 0 1 0 1
TMDS_SAMP[5:0] — TMDS Sampling Logic Control Parameters
This register is recommended to be programmed with the value 0x09 after the power on sequence if the
expected supported TMDS clock frequency is up to 225MHz (1080p, 12 bits deep color). The
TMDS_SAMP[0] is fixed to 1 always.
$6A W RX_SHA-1_HASH_10 XXh
$6B W RX_SHA-1_HASH_11 XXh
$6C W RX_SHA-1_HASH_12 XXh
$6D W RX_SHA-1_HASH_13 XXh
$6E W RX_SHA-1_HASH_14 XXh
$6F W RX_SHA-1_HASH_15 XXh
$70 W RX_SHA-1_HASH_16 XXh
$71 W RX_SHA-1_HASH_17 XXh
$72 W RX_SHA-1_HASH_18 XXh
$73 W RX_SHA-1_HASH_19 XXh
$80 ~
$CF W RX_KSV_FIFO XXh
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3.3.1.2 TMDS Control Register 1
Table 3-3 TMDS Control Register 1
$06
bit 7 6 5 4 3 2 1 0
RTX_TERM DPRE_EM TX_BW TX_PEAK CPRE_EM RX_EQ RX_BW RX_TERM
W
Reset: 0 0 0 0 0 0 0 0
TX_TERM — HDMI Transmitter Internal Termination Control
1 = Internal Termination is ON
0 = Internal Termination is OFF
DPRE_EM — HDMI Transmitter Data Channel Pre-emphasis Control
1 = Transmitter Data Channel Pre-emphasis is ON
0 = Transmitter Data Channel Pre-emphasis is OFF
TX_BW — HDMI Transmitter PLL Bandwidth Control
1 = TX PLL Bandwidth is 1MHz
0 = TX PLL Bandwidth is 1.6MHz
TX_PEAK — HDMI Transmitter Active Peaking Control
1 = TX Active Peaking is ON
0 = TX Active Peaking is OFF
CPRE_EM — HDMI Transmitter Clock Channel Pre-emphasis Control
1 = Transmitter Clock Channel Pre-emphasis is ON
0 = Transmitter Clock Channel Pre-emphasis is OFF
RX_EQ — HDMI Receiver Equalizer Bias Current Control
1 = EQ Bias Current is 125uA
0 = EQ Bias Current is 100uA
RX_BW — HDMI Receiver Bandwidth Control
1 = 2MHz
0 = 4MHz
RX_TERM — HDMI Receiver Clock Channel Termination Control
1 = Receiver Clock Channel Termination is 100:
0 = Receiver Clock Channel Termination is 50:
This register is recommended to be programmed with the value 0xC0 after the power on sequence if the
expected supported TMDS clock frequency is up to 225MHz (1080p, 12 bits deep color). Also, if long
cable is supported, the recommended setting will be 0xA0. The transmitter will consume more current if
the control bit TX_TERM is set to 1.
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3.3.1.3 Control Register 0
Table 3-4 Control Register 0
$07
bit 7 6 5 4 3 2 1 0
RRX_LINK_ON RX_DE_ON RX_HDMI RX_ENC_ON RX_PU - TX_SEL[1:0]
W--
--
Reset: - - - - 1 0 0 0
RX_LINK_ON — Receiver Link On
This bit indicates whether a valid signal appears at the clock input of the receiver port. This bit is valid
even when the receiver is powered off.
1 = Clock presents at the input of the receiver port
0 = No clock is detected at the input of the receiver port
RX_DE_ON — Receiver DE On
This bit indicates whether DE signal is toggling at the receiver port. This bit is valid only when the
receiver is powered on.
1 = DE signal is toggling at the receiver port
0 = DE signal is not toggling at the receiver port
RX_HDMI — Receiver HDMI signal
This bit indicates whether the receiver port is receiving DVI or HDMI signal
1 = HDMI
0 = DVI
RX_ENC_ON — Receiver Decryption On
This bit indicates whether the HDCP decryption is active at the receiver port.
1 = HDCP decryption at the receiver port is active
0 = HDCP decryption at the receiver port is not active
RX_PU — Receiver Power Down Control Bit
This bit controls the power of the receiver port
1 = Normal operation.
0 = Power down Mode.
TX_SEL[1:0] — Transmitter Port Select for IIC Access
The 4 transmitter ports share the same IIC register address. This register is used to select which
transmitter port is addressed for IIC access.
00 = Port 0 is selected
01 = Port 1 is selected
10 = Port 2 is selected
11 = Port 3 is selected
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