Fibocom L850-GL Installation instructions

FIBOCOM L850-GL Series
Hardware Guide
Version: V1.1.5
Date: 2020-06-20

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FIBOCOM L850-GL Series Hardware Guide Page 2 of 59
Applicability Type
No. Product Model Description
1 L850-GL-00 NA
2 L850-GL-01 NA
3 L850-GL-02 NA
4 L850-GL-03 NA
5 L850-GL-05 NA
6 L850-GL-10 L850-GL-10 series (except L850-GL-10-06)
7 L850-GL-10-06 NA
8 L850-GL-12 NA
9 L850-GL-20 NA

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FIBOCOM L850-GL Series Hardware Guide Page 3 of 59
Copyright
Copyright © 2020 Fibocom Wireless Inc. All rights reserved.
Without the prior written permission of the copyright holder, any company or individual is prohibited to
excerpt, copy any part of or the entire document, or distribute the document in any form.
Notice
The document is subject to update from time to time owing to the product version upgrade or other reasons.
Unless otherwise specified, the document only serves as the user guide. All the statements, information
and suggestions contained in the document do not constitute any explicit or implicit guarantee.
Trademark
The trademark is registered and owned by Fibocom Wireless Inc.

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FIBOCOM L850-GL Series Hardware Guide Page 4 of 59
Change History
Version Author Date Remark
V1.1.5 Shu Ying 2020-06-20
● Section 3.3.1, add FCPO# controlling GPIO request
● Section 3.4.1.2, change PEWAKE# pull high resistor to
100KΩ
V1.1.4 Li Senhao 2020-04-01 ● Section 3.1.2, add GPIO design request
● Section 3.3.4, add CLKREQ# and PEWAKE# requests
V1.1.3 Guan Xiangyang 2019-12-26
● Section 3.3.1.2, add minimum PCIe detection time
note
● Section 3.3.5, add timing application instruction
● Section 3.4.1.2, add a pull-up resistor on CLKREQ#
● Section 3.9, add note about the direction of MIPI signal
● Section 4.1.4, add RF connector assembly
● Section 4.5, update GNSS performance table
V1.1.2 Guan Xiangyang 2019-09-06 Add L850-GL-20 product model
V1.1.1 Guan Xiangyang 2019-08-22
● Add L850-GL-10-06 and L850-GL-20 part numbers
● Section 2.2, list supporting RF bands of all product
● Section 3.4, add Chrome OS support in USB interface
● Section 3.3, add note of PERST# control timing in USB
● Section 4.3, modify LTE Band5 TX power range
V1.1.0 Lei Daijun 2019-05-05
● Section 3.2.3, update power consumption
● Section 3.3, update module control timing
● Section 4.5, update GNSS consumption
● Section 3.3.4.1, add D0 L1.2 timing
● Section 3.9, modify MIPI-RFFE power domain
● Section 5.6, update packing
● Section 3.4.1.2, fix Figure 3-12 abnormal display in
PDF converting
V1.0.9 Lei Daijun 2018-08-06 Add L850-GL-12 part no
V1.0.8 Lei Daijun 2018-07-13 Modify band 30 TX power range of L850-GL-03 serial
module
V1.0.7 Lei Daijun 2018-06-26
● Update package
● Add note about PERST#/CLK_REQ# 3.3V support
● Add antenna of B30 requirement, update power
consumption and RX sensitivity
V1.0.6 Lei Daijun 2018-02-26 ● Modify COEX pin define
● Delete L850-GL-02 product model

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Version Author Date Remark
V1.0.5 Lei Daijun 2018-01-16
● Modify CA combinations and TDD data throughput
● Modify description of power consumption condition
● Optimize power on/off/reset timing
V1.0.4 Lei Daijun 2017-12-06 Update Storage and packing and PCIe signal
description, power consumption, CA combine
V1.0.3 Lei Daijun 2017-07-26
● Update timing of power on/off and reset
● Update PCIe, add USB support
● Update power consumption, TX power, RX sensitivity
and other data
V1.0.2 Lei Daijun 2017-02-09 ● Update the content of PCIe
● Add the power Consumption of 3CA
V1.0.1 Lei Daijun 2016-12-16 ● Modify the PCIe Interface Application;
● Update the Pin Definition: change pin65 to NC
V1.0.0 Lei Daijun 2016-12-08 Initial version

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FIBOCOM L850-GL Series Hardware Guide Page 6 of 59
Contents
1Foreword ........................................................................................................................9
1.1 Introduction..................................................................................................................... 9
1.2 Reference Standard ....................................................................................................... 9
1.3 Related Documents........................................................................................................ 9
2Overview ......................................................................................................................10
2.1 Introduction................................................................................................................... 10
2.2 Specification ................................................................................................................. 10
2.3 CA Combinations.......................................................................................................... 12
2.4 Application Framework................................................................................................. 13
2.5 Hardware Block Diagram ............................................................................................. 14
3Application Interface...................................................................................................15
3.1 M.2 Interface ................................................................................................................ 15
3.1.1 Pin Map........................................................................................................................15
3.1.2 Pin Definition................................................................................................................16
3.2 Power Supply ............................................................................................................... 20
3.2.1 Power Supply...............................................................................................................20
3.2.2 Logic Level...................................................................................................................22
3.2.3 Power Consumption ....................................................................................................22
3.3 Control Signal............................................................................................................... 25
3.3.1 Module Start-Up...........................................................................................................25
3.3.1.1 Start-up Circuit ............................................................................................................................ 25
3.3.1.2 Start-up Timing Sequence........................................................................................................... 26
3.3.2 Module Shutdown ........................................................................................................27
3.3.3 Module Reset...............................................................................................................28
3.3.4 PCIe Link State............................................................................................................29
3.3.4.1 D0 L1.2........................................................................................................................................ 30
3.3.4.2 D3cold L2 ...................................................................................................................................... 30
3.3.5 Timing Application........................................................................................................32
3.4 IPC Interface ................................................................................................................ 32
3.4.1 PCIe Interface..............................................................................................................33
3.4.1.1 PCIe Interface Definition ............................................................................................................. 33
3.4.1.2 PCIe Interface Application ........................................................................................................... 34
3.4.2 USB Interface ..............................................................................................................35

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3.4.2.1 USB Interface Definition .............................................................................................................. 36
3.4.2.2 USB2.0 Interface Application....................................................................................................... 36
3.4.2.3 USB3.0 Interface Application....................................................................................................... 36
3.5 USIM Interface ............................................................................................................. 37
3.5.1 USIM Pins....................................................................................................................37
3.5.2 USIM Interface Circuit..................................................................................................38
3.5.2.1 N.C. SIM Card Slot...................................................................................................................... 38
3.5.2.2 N.O. SIM Card Slot...................................................................................................................... 38
3.5.3 USIM Hot-Plug.............................................................................................................39
3.5.4 USIM Design................................................................................................................39
3.6 Status Indicator ............................................................................................................ 40
3.6.1 LED#1 Signal...............................................................................................................40
3.7 Interrupt Control ........................................................................................................... 41
3.7.1 W_DISABLE1# ............................................................................................................41
3.7.2 BODYSAR ...................................................................................................................41
3.8 Clock Interface ............................................................................................................. 41
3.9 ANT Tunable Interface ................................................................................................. 42
3.10 Configuration Interface ................................................................................................. 42
4Radio Frequency .........................................................................................................44
4.1 RF Interface.................................................................................................................. 44
4.1.1 RF Interface Functionality ............................................................................................44
4.1.2 RF Connector Characteristic........................................................................................44
4.1.3 RF Connector Dimension.............................................................................................44
4.1.4 RF Connector Assembly ..............................................................................................46
4.2 Operating Band ............................................................................................................ 48
4.3 Transmitting Power ...................................................................................................... 49
4.4 Receiver Sensitivity ...................................................................................................... 50
4.5 GNSS ........................................................................................................................... 51
4.6 Antenna Design............................................................................................................ 52
5Structure Specification ...............................................................................................54
5.1 Product Appearance..................................................................................................... 54
5.2 Dimension of Structure................................................................................................. 54
5.3 M.2 Interface Model...................................................................................................... 55
5.4 M.2 Connector.............................................................................................................. 55

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5.5 Storage......................................................................................................................... 56
5.5.1 Storage Life .................................................................................................................56
5.6 Packing......................................................................................................................... 56
5.6.1 Tray Package...............................................................................................................56
5.6.2 Tray Size......................................................................................................................59

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FIBOCOM L850-GL Series Hardware Guide Page 9 of 59
1 Foreword
1.1 Introduction
The document describes the electrical characteristics, RF performance, dimensions and application
environment, etc. of L850-GL (hereinafter referred to as L850). With the assistance of the document and
other instructions, the developers can quickly understand the hardware functions of L850 modules and
develop products.
1.2 Reference Standard
The design of the product complies with the following standards:
3GPP TS 34.121-1 V8.11.0: User Equipment (UE) conformance specification; Radio transmission
and reception (FDD); Part 1: Conformance specification
3GPP TS 34.122 V11.13.0: Technical Specification Group Radio Access Network; Radio
transmission and reception (TDD)
3GPP TS 36.521-1 V11.4.0: User Equipment (UE) conformance specification; Radio transmission
and reception; Part 1: Conformance testing
3GPP TS 21.111 V10.0.0: USIM and IC card requirements
3GPP TS 51.011 V4.15.0: Specification of the Subscriber Identity Module -Mobile Equipment (SIM-
ME) interface
3GPP TS 31.102 V10.11.0: Characteristics of the Universal Subscriber Identity Module (USIM)
application
3GPP TS 31.11 V10.16.0: Universal Subscriber Identity Module (USIM) Application Toolkit(USAT)
3GPP TS 36.124 V10.3.0: Electro Magnetic Compatibility (EMC) requirements for mobile terminals
and ancillary equipment
3GPP TS 27.007 V10.0.8: AT command set for User Equipment (UE)
3GPP TS 27.005 V10.0.1: Use of Data Terminal Equipment - Data Circuit terminating Equipment
(DTE - DCE) interface for Short Message Service (SMS) and Cell Broadcast Service (CBS)
PCI Express M.2 Specification Rev1.2
1.3 Related Documents
FIBOCOM Design Guide_RF Antenna

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FIBOCOM L850-GL Series Hardware Guide Page 10 of 59
2 Overview
2.1 Introduction
L850 is a highly integrated 4G WWAN module which uses M.2 form factor interface. It supports LTE
FDD/LTE TDD/WCDMA systems and can be applied to most cellular networks of mobile carrier in the
world.
2.2 Specification
Specification
Operating Band
L850-GL-00, L850-GL-01,
L850-GL-02, L850-GL-03,
L850-GL-05, L850-GL-10
series (except L850-GL-
10-06)
L850-GL-12
L850-GL-20
LTE FDD: Band 1, 2, 3, 4, 5, 7, 8, 11, 12, 13, 17, 18,
19, 20, 21, 26, 28, 29, 30, 66
LTE TDD: Band 38, 39, 40, 41
WCDMA/HSPA+: Band 1, 2, 4, 5, 8
L850-GL-10-06
LTE FDD: Band 2, 4, 5, 13
GNSS
Support GPS, GLONASS, BDS
LTE
3GPP Release 11
UMTS
3GPP Release 8
Data Transmission
LTE FDD 450Mbps DL(Cat 9)/50Mbps UL(Cat 4)
LTE TDD
347Mbps DL(Cat 9)/30Mbps UL(Cat 4)
When LTE TDD achieves maximum DL rate, its UL
rate can reach 10Mbps only
UMTS/HSPA+
UMTS: 384 kbps DL/384 kbps UL
DC-HSPA+: 42Mbps DL(Cat 24)/5.76Mbps UL(Cat6)
Power Supply DC 3.135V~4.4V, Typical 3.3V
Temperature
Normal operating temperature: -10°C~+55°C
Extended operating temperature: -20°C~+65°C
Storage temperature: -40°C~+85°C
Physical
characteristics
Interface: M.2 Key-B
Dimension：30×42×2.3mm
Weight: About 6.2 g

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Interface
Antenna Connector
WWAN Main Antenna ×1
WWAN Diversity Antenna ×1
Function Interface
USIM 3V/1.8V
PCIe Gen1 ×1
USB 2.0
USB 3.1 Gen1 (Base on Android/Linux)
W_Disable#
BodySAR
LED
Clock
Tunable antenna
I2S (Reserved)
I2C (Reserved)
Software
Protocol Stack IPV4/IPV6
AT commands 3GPP TS 27.007 and 27.005
Firmware update PCIe
Other feature
Multiple carrier
Windows MBIM support
Windows update
Note:
When temperature goes beyond normal operating temperature range of -10°C~+55°C, RF
performance of module may be slightly off 3GPP specifications. For normal operating
temperature, LTE FDD Band 4 and 13 can support temperature ranging from -20°C to +60°C.

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FIBOCOM L850-GL Series Hardware Guide Page 12 of 59
2.3 CA Combinations
CA Combinations
L850-GL-00, L850-GL-01, L850-GL-02, L850-GL-03, L850-GL-05, L850-GL-10 series (except L850-
GL-10-06),L850-GL-12, L850-GL-20
2CA
Inter-band
1+3, 5, 8, 11, 18, 19, 20, 21, 26
2+4, 5, 12, 13, 17, 29, 30, 66
3+5, 7, 8, 19, 20, 28
4+5, 12, 13, 17, 29, 30
5+7, 30, 66
7+20, 28
8+11
12+30
13+66
29+30
Intra-band (non-contiguous) 2, 3, 4, 7, 41
Intra-band (contiguous) 2, 3, 7, 40, 41
3CA
Inter-band
1+3+7, 1+3+8，1+3+19, 1+3+20, 1+3+28, 1+7+20,
1+7+28, 1+8+11, 1+19+21
2+4+5, 2+4+13, 2+5+30, 2+12+30, 2+29+30, 2+5+66,
2+13+66
3+7+20, 3+7+28
4+5+30, 4+12+30, 4+29+30
2 intra-band (non-contiguous)
plus inter-band
2+2+5, 2+2+13
4+4+5, 4+4+13
2 intra-band (contiguous)
plus inter-band
2+2+29
3+3+1, 3+3+5, 3+3+7, 3+3+20, 3+3+28
2+66+66, 5+66+66, 13+66+66
7+7+3, 7+7+28
Intra-band (non-contiguous) 41, 66
Intra-band (contiguous) 40, 41, 66

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CA Combinations
L850-GL-10-06
2CA
Inter-band
2+4, 5, 13
4+5, 13
Intra-band (non-contiguous) 2, 4
Intra-band (contiguous) 2
3CA
Inter-band 2+4+5, 2+4+13
2 intra-band (non-contiguous)
plus inter-band
2+2+5, 2+2+13
4+4+5, 4+4+13
2.4 Application Framework
The peripheral applications for L850 module are shown in Figure 2-1:
Module
SIM USB2.0
Power
Supply ON/OFF# RESET#
Control
EINT Indicator
Host application
Main ANT Div ANT
SIM
Card
PCIe USB3.1
Figure2-1 Application framework

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2.5 Hardware Block Diagram
The hardware block diagram in Figure 2-2 shows the main hardware functions of L850 module, including
baseband and RF functions.
Baseband contains the followings:
UMTS/LTE TDD/LTE FDD controller
PMU
NAND/internal LPDDR2 RAM
Application interface
RF contains the followings:
RF Transceiver
RF Power/PA
RF Front end
RF Filter
Antenna Connector
+3.3V
FULL_CARD_POWER_OFF#
RESET#
PCIe
USB2.0
USB 3.0
USIM
EINT
WOWWAN#
LED
I2S
I2C
CLOCK
Tunable ANT
Baseband
(UMTS/LTE TDD/LTE FDD controller)
PMU
TX
LPDDR2
RAM
NAND
Div
MB FEM
Main LB
FEMiD
PA DCDC
PA
Main RX
Div RX
RF Part
M.2 Key-B 75pin interface
Div ANT
Main ANT
GNSS/
Beidou
RF
Transceiver 1st
TCXO
RF
Transceiver 2nd
Div
LB FEM
Diplexer Diplexer
Main MB
FEMiD
TX
Main RX
Div RX
Duplexer
SAW
SAW
Figure 2-2 Hardware block diagram

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3 Application Interface
3.1 M.2 Interface
The L850 module applies standard M.2 Key-B interface, with a total of 75 pins.
3.1.1 Pin Map
Figure 3-1 Pin map
Note:
Pin “Notch” represents the gap of the gold fingers.

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3.1.2 Pin Definition
The pin definition is as follows:
Pin Pin Name I/O Reset Value Pin Description Type
1 CONFIG_3 O NC
NC, L850 M.2 module is configured as
the WWAN – PCIe, USB3.1 interface
type
-
2 +3.3V PI - Power input Power Supply
3 GND - - GND Power Supply
4 +3.3V PI - Power input Power Supply
5 GND - - GND Power Supply
6 FULL_CARD_
POWER_OFF# I PU Power enable, module power on input, internal pull up 3.3/1.8V
7 USB D+ I/O - USB data plus 0.3---3V
8 W_DISABLE1# I PD WWAN disable, active low 3.3/1.8V
9 USB D- I/O - USB data minus 0.3---3V
10 LED1# O T System status LED, output open drain,
3.3V 3.3V
11 GND - - GND Power Supply
12 Notch Notch
13 Notch Notch
14 Notch Notch
15 Notch Notch
16 Notch Notch
17 Notch Notch
18 Notch Notch
19 Notch Notch
20 I2S_CLK O PD I2S serial clock,
Reserved 1.8V
21 CONFIG_0 - GND
GND,
L850 M.2 module is configured as
the WWAN – PCIe, USB3.1 interface
type
-
22 I2S_RX I PD I2S serial receive data,
Reserved 1.8V

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FIBOCOM L850-GL Series Hardware Guide Page 17 of 59
Pin Pin Name I/O Reset Value Pin Description Type
23 WOWWAN# O PD Wake up host,
Reserved 1.8V
24 I2S_TX O PD I2S serial transmit data,
Reserved 1.8V
25 DPR I PU BodySAR detect, active low 3.3/1.8V
26 W_DISABLE2# I PU GNSS disable, active low,
Reserved 3.3/1.8V
27 GND - - GND Power Supply
28 I2S_WA O PD I2S word alignment/select,
Reserved 1.8V
29 USB3.0_TX- O - USB3.0 transmit data minus -
30 UIM_RESET O L SIM reset signal 1.8V/3V
31 USB3.0_TX+ O - USB3.0 transmit data plus -
32 UIM_CLK O L SIM clock signal 1.8V/3V
33 GND - - GND Power Supply
34 UIM_DATA I/O L SIM data input/output 1.8V/3V
35 USB3.0_RX- I - USB3.0 receive data minus -
36 UIM_PWR O - SIM power supply, 3V/1.8V 1.8V/3V
37 USB3.0_RX+ I - USB3.0 receive data plus -
38 NC - - NC -
39 GND - - GND Power Supply
40 GNSS_SCL I PU I2C serial clock input,
Reserved 1.8V
41 PETn0 O -
PCIe TX differential signal
Negative -
42 GNSS_SDA I/O PU I2C serial data input/output,
Reserved 1.8V
43 PETp0 O -
PCIe TX differential signal
Positive -
44 GNSS_IRQ O PD GNSS interrupt request output,
Reserved 1.8V
45 GND - - GND Power Supply

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Pin Pin Name I/O Reset Value Pin Description Type
46 SYSCLK O PD 26M clock output 1.8V
47 PERn0 I -
PCIe RX differential signal
Negative -
48 TX_BLANKING O PD PA blanking timer,
Reserved 1.8V
49 PERp0 I -
PCIe RX differential signal
Positive -
50 PERST# I PU
Asserted to reset module PCIe interface
default. If module went into core dump,
it will reset whole module, not only PCIe
interface.
Active low, internal pull up(10KΩ)
3.3V
51 GND - - GND Power Supply
52 CLKREQ# I/O PU
Asserted by device to request a PCIe
reference clock be available (active
clock state) in order to transmit data. It
also used by L1 PM Sub states
mechanism, asserted by either host or
device to initiate an L1 exit.
Active low, internal pull up(10KΩ)
3.3V
53 REFCLKN I -
PCIe reference clock signal,
Negative -
54 PEWAKE# O L
Asserted to wake up system and
reactivate PCIe link from L2 to L0, it
depends on system
whether supports wake up functionality.
Active low, open drain output and
should add external pull up(100KΩ) on
platform
3.3V
55 REFCLKP I -
PCIe reference clock signal,
Positive -
56 RFFE_SCLK O -
MIPI interface tunable ANT,
RFFE clock 1.8V
57 GND - - GND Power Supply
58 RFFE_SDATA O -
MIPI interface tunable ANT,
RFFE data 1.8V

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FIBOCOM L850-GL Series Hardware Guide Page 19 of 59
Pin Pin Name I/O Reset Value Pin Description Type
59 ANTCTL0 O - Tunable ANT CTRL0, bit0 1.8V
60 COEX3 I/O PD
Wireless coexistence between WWAN
and WiFi/BT modules, based on BT-
SIG
coexistence protocol. COEX_EXT_FTA,
Reserved
1.8V
61 ANTCTL1 O - Tunable ANT CTRL1, bit1 1.8V
62 COEX_RXD I T
Wireless coexistence between WWAN
and WiFi/BT modules, based on BT-
SIG
coexistence protocol. UART receive
signal(WWAN module side)
Reserved
1.8V
63 ANTCTL2 O - Tunable ANT CTRL2, bit2 1.8V
64 COEX_TXD O T
Wireless coexistence between WWAN
and WiFi/BT modules, based on BT-
SIG
coexistence protocol. UART transmit
signal(WWAN module side), Reserved
1.8V
65 NC - - NC -
66 SIM_DETECT I PD SIM detect, internal pull up(390KΩ),
active high 1.8V
67 RESET# I - WWAN reset input, internal pull
up(10KΩ), active low 1.8V
68 NC - - NC -
69 CONFIG_1 O GND
GND,
L850 M.2 module is configured as
the WWAN – PCIe, USB3.1 interface
type
-
70 +3.3V PI - Power input Power Supply
71 GND - - GND Power Supply
72 +3.3V PI - Power input Power Supply
73 GND - - GND Power Supply
74 +3.3V PI - Power input Power Supply
75 CONFIG_2 O GND
GND, L850 M.2 module is configured as
the WWAN – PCIe, USB3.1 interface
type
-

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FIBOCOM L850-GL Series Hardware Guide Page 20 of 59
Reset Value: The initial status after module reset, not the status when working.
H: High Voltage Level
L: Low Voltage Level
PD: Pull-Down
PU: Pull-Up
T: Tristate
OD: Open Drain
PP: Push-Pull
PI: Power Input
PO: Power Output
Note:
Digital IO pins CANNOT be connected to power directly.
The unused pins can be left floating.
All 3.3V ports are based on +3.3V power domain. When the power supply range is
3.135V~4.4V, the 3.3V ports voltage will follow the change of power supply range.
3.2 Power Supply
The power interface of L850 module is shown in the following table:
Pin Pin Name I/O Pin Description
DC Parameter (V)
Minimum
Value
Typical
Value
Maximum
Value
2, 4, 70, 72, 74 +3.3V PI Power supply input 3.135 3.3 4.4
36 UIM_PWR PO USIM power supply - 1.8V/3V -
L850 module uses PCIe interface. According to the PCIe specification, the PCIe Vmain should be used as
the +3.3V power source, not the Vaux. The Vaux is the PCIe backup power source and it is not sufficient
as the power supply. In addition, the DC/DC power supply other than PCIe ports should not be used as
the external power cannot control the module status through the PCIe protocol.
3.2.1 Power Supply
The L850 module should be powered through the +3.3V pins, and the power supply design is shown in
Figure 3-2: