Freescale Semiconductor QorIQ LS1021A-IOT User manual

QorIQ LS1021A-IOT Gateway
Reference Design Board Reference
Manual
Document Number: LS1021A-IOTRM
Rev. 0, 03/2015

QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015
2 Freescale Semiconductor, Inc.

Contents
Section number Title Page
Chapter 1
Introduction
1.1 Related documentation....................................................................................................................................................7
1.2 Silicon features................................................................................................................................................................8
1.3 Board features................................................................................................................................................................. 9
1.4 Block diagram.................................................................................................................................................................11
Chapter 2
Architecture
2.1 Processor.........................................................................................................................................................................15
2.2 Power.............................................................................................................................................................................. 15
2.2.1 MC34VR500......................................................................................................................................................18
2.2.2 Fuse programming power.................................................................................................................................. 18
2.2.3 Power sequence..................................................................................................................................................18
2.3 Deep sleep control...........................................................................................................................................................20
2.4 Reset................................................................................................................................................................................20
2.4.1 System reset....................................................................................................................................................... 22
2.4.2 RESET_REQ reset.............................................................................................................................................22
2.4.3 Reset sequence timing........................................................................................................................................22
2.5 Device configuration.......................................................................................................................................................22
2.6 Clocks............................................................................................................................................................................. 23
2.6.1 SYSCLK............................................................................................................................................................ 24
2.6.1.1 Single-Source SYSCLK.......................................................................................................................24
2.6.2 DDRCLK........................................................................................................................................................... 24
2.6.3 SerDes clocks.....................................................................................................................................................25
2.6.4 Ethernet clocks...................................................................................................................................................25
2.6.5 Codec SYS MCLK.............................................................................................................................................25
2.7 Memory controllers.........................................................................................................................................................25
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Section number Title Page
2.8 SerDes port......................................................................................................................................................................27
2.8.1 PCI Express support ..........................................................................................................................................28
2.8.2 SGMII support................................................................................................................................................... 29
2.8.3 SATA support.................................................................................................................................................... 29
2.9 Ethernet controllers.........................................................................................................................................................29
2.10 Ethernet management interfaces.....................................................................................................................................31
2.11 USB interface..................................................................................................................................................................32
2.12 Local bus.........................................................................................................................................................................33
2.13 2D ACE - display controller port....................................................................................................................................35
2.13.1 Programming display control unit......................................................................................................................35
2.14 I2C...................................................................................................................................................................................36
2.15 SPI interface....................................................................................................................................................................37
2.16 SDHC interface...............................................................................................................................................................38
2.17 Interrupt controller..........................................................................................................................................................39
2.18 Event pins....................................................................................................................................................................... 41
2.19 Serial ports...................................................................................................................................................................... 41
2.20 Audio port.......................................................................................................................................................................42
2.21 JTAG port....................................................................................................................................................................... 43
2.22 GPIO pins....................................................................................................................................................................... 44
2.23 Monitoring LEDs............................................................................................................................................................44
2.24 MBED.............................................................................................................................................................................45
Chapter 3
Expansion Headers and Ports
3.1 K22 expansion (internal).................................................................................................................................................47
3.2 Audio expansion (internal)............................................................................................................................................. 48
3.3 Arduino expansion (internal).......................................................................................................................................... 48
3.4 Rear panel expansion ports (external).............................................................................................................................50
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Section number Title Page
Chapter 4
CPLD System Controller Architecture
4.1 Key features of CPLD.....................................................................................................................................................54
4.2 Reset................................................................................................................................................................................55
4.3 CPLD register map ........................................................................................................................................................ 56
4.3.1 Memory map .....................................................................................................................................................56
4.3.2 BCSR registers map...........................................................................................................................................56
4.4 LCD FDI translator.........................................................................................................................................................57
Chapter 5
Board Configuration and Debug Support
5.1 Kit contents.....................................................................................................................................................................59
5.2 Case and PCB description...............................................................................................................................................60
5.3 Configuring switches and jumpers..................................................................................................................................63
5.4 Memory map ..................................................................................................................................................................65
5.5 CMSIS-DAP debug support........................................................................................................................................... 66
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Chapter 1
Introduction
The LS1021A-IoT gateway reference design is a purpose-built, small footprint hardware
platform equipped with a wide array of both high speed connectivity and low speed serial
interfaces engineered to support the secure delivery of IoT services to end-users in a
home, business, or other commercial location. The LS1021A-IOT Gateway reference
design offers an affordable, ready-made platform for rapidly deploying a secure,
standardized, and open infrastructure gateway platform for deployment of IoT services.
The reference design combines standards-based, open source software together with a
feature-rich IoT gateway design, to establish a common, open framework for secure IoT
service delivery and management.
Setting the LS1021A-IOT gateway platform apart is the wide assortment of high-speed
and serial-based connectivity it offers in a compact, highly secure design, delivering a
truly impressive level of versatility. An additional innovation of the gateway reference
design is its support for Arduino ShieldTM modules, which further enable the board to
support a wide variety of communication solutions offered by the family of Arduino
modules. High efficiency is achieved through the use of Freescale’s new ARM-based
LS1021A embedded processor, which delivers over 5,000 Coremarks of performance at a
typical power of under 3 watts. In addition to it’s outstanding performance efficiency and
high level of integration, the LS1021A-IoT gateway design offers HDMI, SATA2, and
USB3 connectors as well as a complete Linux software developer's package.
In addition to high efficiency, integration, and reliability, the LS1021A-IOT reference
platform supports a comprehensive level of security, which includes secure boot, Trust
Architecture, and tamper detection for both standby and active power modes. Together,
these features safeguard customer designs from the point of manufacture to the point of
deployment, providing continuous protection from malicious attacks and ensures end
products deliver the highest level of security and reliability.
The LS1021A-IOT board is lead-free and RoHS-compliant.
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1.1 Related documentation
For more information on the LS1021A-IOT board, see the additional resources listed in
the table below.
NOTE
Some of the documents listed below may be available only
under a non-disclosure agreement (NDA). To request access to
these documents, contact your local field applications engineer
or sales representative.
Table 1-1. Related documents
Document Description
LS1021A QorIQ Advanced Multicore Processor Data Sheet Provides information about electrical characteristics,
hardware design considerations, pin assignments, package,
and ordering information.
LS1021A QorIQ Integrated Multicore Processor Reference
Manual (LS1021ARM)
Provides a detailed description about LS1021A QorIQ
multicore processor and its features, such as memory map,
serial interfaces, power supply, chip features, and clock
information.
The SystemID Format for Power Architecture™ Development
Systems (AN3638)
Freescale Semiconductor Power Architecture™ technology-
based evaluation and development platforms may optionally
implement a "System ID" non-volatile memory device. This
device stores important configuration data about the board.
QorIQ LS1021A IOT Gateway Getting Started Guide
(LS1021A-IOTGS)
Explains how to connect the LS1021A-IOT card (700-28203
Rev B) and verify its basic operation. This document shows
the settings for switches, connectors, jumpers, push buttons,
and LEDs, and the instructions for getting a U-Boot terminal
up and running.
MBED documents https://developer.mbed.org/handbook/Serial
NOTE
Freescale Semiconductor, Inc. does not own the MBED
documents and they are mentioned solely for reference
purposes.
1.2 Silicon features
The LS1021A processor includes the following functions and features:
• Two (LS1021A) ARM Cortex-A7 cores based on Harvard architecture including
AMBA4 MPCORE™ Virtualization, each with separate ECC protected L1 32 KB I
cache and 32 KB D cache and a shared 512 KB L2 cache with ECC protection
Silicon features
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• Up to 1.0 GHz at 1.0 V with 32-bit ISA support
• Three levels of instructions: user, supervisor, and hypervisor
• Independent boot and reset
• Secure boot capability with QorIQ Trust Architecture and ARM TrustZone®
support
• Hierarchical interconnect fabric
• Cache Coherency Interconnect (CCI-400)
• 16 or 32-bit DDR3LP/DDR4 SDRAM memory controller with ECC
• Encryption/Decryption (SEC 5.x)
• RegEx pattern matching (PME 2)
• VeTSEC Ethernet interfaces
• Three 1 Gbit/s Ethernet controllers with IEEE 1588
• High speed peripheral interfaces
• Two PCI Express 2.0 controllers/ports running at up to 5 GHz
• Additional peripheral interfaces
• One SATA2 controller supporting up to 3 Gbit/s operation
• One USB 2.0/3.0 controller with integrated PHY and one USB 2.0 controller
with ULPI interface
• SD/SDXC/eMMC
• Two SPI controllers and one QuadSPI controller
• Three I2C controllers
• Four 16550-compliant UARTs and 6 LPUARTs
• Integrated flash controller (IFC)
• Integrated LCD controller 2D-ACE (only on LS1021A)
• Four FlexCAN controllers (only on LS1021A and LS1022A)
• Multicore programmable interrupt controller (PIC)
• One 8-channel DMA engine
• QUICC Engine block (LS1021A and LS1020A only)
• 32-bit RISC controller for flexible support of the communications peripherals
• Serial DMA channel for receive and transmit on all serial channels
• Two universal communication controllers, supporting TDM, HDLC, UART, and
ISDN
1.3 Board features
The features of the LS1021A-IOT reference board are as follows:
• Four lanes of SerDes connections supporting:
• Two PCI Express buses that support Gen 1 and Gen 2
Chapter 1 Introduction
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• One Gbit Ethernet SGMII interfaces
• One muxed SATA or Gbit Ethernet SGMII interface
• Integrated USB3 PHY with dedicated SerDes lane
• DDR Controller
• Supports data rates up to 1600 MHz
• Supports 1 GB un-buffered DDR3L SDRAM discrete devices (32-bit bus) with 4
bit ECC
• DDR power supplies 1.35 V to all devices with automatic tracking of VTT
• IFC/Local Bus
• QSPI: Serial NOR 128 MB
• CPLD: 8-bit registers in CPLD for system configuration
• Ethernet
• One Gbit Ethernet RGMII interface to 4-port switch with 4x 10/100/1000 RJ45
ports
• Two onboard SGMII PHYs with up to two 10/100/1G RJ45 ports (one muxed
with SATA)
• System logic CPLD
• Manages system power and reset sequencing
• Latch IFC address/data multiplexed signals for 8 bit config register access
• Signal mux/demux function (for example, LCD and UCC)
• GPIO routing
• IRQ routing
• Level shifter 3.3 V to 1.8 V (for example, JTAG)
• Switch control
• Clocks
• DDR clock (DDRCLK) - 66.667 MHz
• System clock (SYSCLK) - switch selectable to one of three settings: 96 MHz, 99
MHz and 100 MHz for system clock
• 100 MHz single-source DIFF_SYCLK input to processor, which supports core/
platform SYSCLK, DDR controller (DDRCLK), and USB controller (USBCLK)
• SerDes clocks (100 MHz) that provide clocks to all SerDes blocks and slots
• Power supplies
• 12 V input Supply 12 V @5 A
• PoE Class 0 (12.9W) - optional
• LT3976 - 12 V to 3.3 V for PMIC input supply
• LT3976 - 12 V to 5 V for SATA and USB ports
• ISL8201MIRZ - 3.3 V board supply including CPLD
• MC34VR500 Power Management IC (PMIC) supplying VDD and VDDC and
GVDD, VTT, VREF, O1VDD, OVDD, L1VDD, and LVDD
• 2x MAX8869
Board features
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