GE PCIE-5565PIORC* Application guide

GE
Intelligent Platforms
Publication No: 500-9367875565-000 Rev. A
Hardware Reference
PCIE-5565PIORC*
Ultrahigh Speed Fiber-Optic Reflective Memory
with Interrupts
THE PCIE-5565PIORC IS DESIGNED TO MEET THE EUROPEAN UNION (EU) RESTRICTION OF HAZARD-
OUS SUBSTANCE (ROHS) DIRECTIVE (2002/95/EC) CURRENT REVISION.


Document History
Hardware Reference Manual Document Number: 500-9367875565-000 Rev. ASeptember 23, 2011

Table of Contents 3
Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1 • Handling and Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1 Unpacking Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.2 Handling Precaution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.3 Switch S1 and S2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.3.1 Before Installation Switch S1 and S2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.4 Physical Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.5 Front Panel Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5.1 LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.6 Cable Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.6.1 Connector Specification (Singlemode and Multimode): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2 • Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.1 Basic Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.2 Front Bezel LED Indicators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.3 RFM-5565 Register Sets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.4 Reflective Memory RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.5 Interrupt Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.6 Network Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.7 Redundant Transfer Mode of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.8 Rogue Packet Removal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3 • Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1 PCI Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.2 Local Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.3 RFM Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.3.1 Board Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.3.2 Board ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.3.3 Board Revision Build Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.3.4 Node ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.3.5 Local Control and Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.3.6 Local Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
3.3.7 Network Target Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3.3.8 Network Target Node Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3.3.9 Network Interrupt Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
3.3.10 Interrupt 1 Sender Data FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
3.3.11 Interrupt 1 Sender ID FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
3.3.12 Interrupt 2 Sender Data FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.3.13 Interrupt 2 Sender ID FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.3.14 Interrupt 3 Sender Data FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.3.15 Interrupt 3 Sender ID FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

4 PCIE-5565PIORC Reflective Memory Board.
3.3.16 Interrupt 4 Sender Data FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.3.17 Interrupt 4 Sender ID FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.4 Example of a Block DMA Operation for RFM-5565. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.5 Example of a Scatter-Gather DMA Operation for RFM-5565. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
3.6 Example of a PCI PIO Sliding Window Operation for RFM-5565. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.7 Example of Network Interrupt Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
3.7.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
3.7.2 Servicing Network Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Maintenance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Compliance Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

List of Figures 5
List of Figures
Figure 1 Block Diagram of PCIE-5565PIORC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2 Typical Reflective Memory Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 1-1 S1 and S2 Location PCIE-5565PIORC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 1-2 Installing the PCIE-5565PIORC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 1-3 Low Profile and Standard Front Panels of the PCIE-5565PIORC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 1-4 LC Type Fiber-Optic Cable Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 1-5 Example: Six Node Ring Connectivity PCIE-5565PIORC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 2-1 Interrupt Circuitry Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 3-1 Block Diagram of the Network Interrupt Reception Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6 PCIE-5565PIORC Reflective Memory Board
List of Tables
Table 1-1 Example Node ID Switch S2 RFM-5565 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 1-2 Switch S1 Configuration RFM-5565 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 1-3 LED Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 1-4 Cable Specifications for Multimode and Singlemode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 3-1 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 3-2 PCI Configuration ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 3-3 PCI Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 3-4 PCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 3-5 PCI Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 3-6 PCI Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 3-7 PCI Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 3-8 PCI Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 3-9 PCI Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 3-10 PCI Built-in Self Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 3-11 PCI Base Address Register 0 for Access to Local Configuration Registers . . . . . . . . . . . . . . . . . . . . . . .34
Table 3-12 PCI Base Address Register 1 for Access to Local Configuration Registers . . . . . . . . . . . . . . . . . . . . . . .35
Table 3-13 PCI Base Address Register 2 for Access to RFM Control and Status Registers . . . . . . . . . . . . . . . . . . .35
Table 3-14 PCI Base Address Register 3 for Access to Reflective Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 3-15 PCI Base Address Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 3-16 PCI Base Address Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 3-17 PCI Cardbus CIS Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 3-18 PCI Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 3-19 PCI Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 3-20 PCI Expansion ROM Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 3-21 PCI Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 3-22 PCI Interrupt Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 3-23 PCI Interrupt Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 3-24 MSI Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 3-25 Message Control bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 3-26 Power Management Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 3-27 PCIe Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 3-28 PCIe Capabilities Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 3-29 Device Capabilities Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 3-30 Device Control Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 3-31 Device Status Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 3-32 Link Capabilities Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 3-33 Link Control Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 3-34 Link Status Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 3-35 Local Configuration and DMA Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Table 3-36 Mode/DMA Arbitration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

List of Tables 7
Table 3-37 Big/Little Endian Descriptor Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 3-38 Interrupt Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 3-39 INTCSR Interrupt Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 3-40 INTCSR Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 3-41 PCI Core/Features Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 3-42 DMA Channel 0 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 3-43 DMA Channel 0 PCI Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 3-44 DMA Channel 0 Local Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 3-45 DMA Channel 0 Transfer Size (Bytes) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 3-46 DMA Channel 0 Descriptor Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 3-47 DMA Channel 0 Command/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 3-48 DMA Channel 0 PCI Dual Address Cycles Upper Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 3-49 PCI PIO Direct Slave Local Address Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 3-50 PCI PIO Direct Slave Local Base Address (Remap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 3-51 Memory Map of the Local Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 3-52 Local Control and Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 3-53 Local Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 3-54 Local Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 3-55 Network Interrupt Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

8 PCIE-5565PIORC Reflective Memory Board
Overview
ThePCIE‐5565PIORC*isaPCIExpress(PCIe)memberofGE’sfamilyof
ReflectiveMemoryreal‐timefiber‐opticnetworkproductsthatsupportsbothlow
profileandstandardheightPCIeboards.TwoormorePCIE‐5565PIORCs,along
withothermembersofthisfamily,canbeintegratedintoanetworkusing
standardfiber‐opticcables.Eachboardinthenetworkisreferredtoasa“node.”
ReflectiveMemoryallowscomputers,workstations,PLCsandotherembedded
controllerswithdifferentarchitecturesanddissimilaroperatingsystemstoshare
datainrealtime.The5565familyofReflectiveMemory(referredtoasRFM‐5565
inthismanual)isfast,flexibleandeasytooperate.Dataistransferredbywriting
tomemory(SDRAM),whichappearstoresidegloballyinallboardsonthe
network.Onboardcircuitryautomaticallyperformsthedatatransfertoallother
nodeswithlittleornoinvolvementofanyhostprocessor.Ablockdiagramofthe
PCIE‐5565PIORCisshowninFigure1onpage9.
Features
Featuresinclude:
•Highspeed,easytousefiber‐opticnetwork(2.12Gbaudserially)
•x4lanePCIExpress1
•Nohostprocessorinvolvementintheoperationofthenetwork
•SelectableRedundantModeofOperation
•Upto256nodes
•Connectivitywithmultimodefiberupto300m,singlemodefiberupto
10km
•Dynamicpacketsize,4to64bytesofdataperpacket
•Fibernetworktransferrate43MByte/sto170MByte/s
•128/256MBytesSDRAMReflectiveMemorywithselectableparity
•IndependentDirectMemoryAccess(DMA)channel
•Fourgeneralpurposenetworkinterrupts;eachwith32bitsofdata
•ConfigurableendianconversionformultipleCPUarchitecturesonthesame
network
•SelectablePCIPIOwindowsizefrom2MByteto64MBytetofullinstalled
memorysize
•OperatingSystemsupport:Windows®2000,WindowsXP,Linux®and
VxWorks®
•RoHSCompliant

Overview 9
PCI Express Compliance
ThePCIE‐5565PIORCcomplieswithrequirementsofthePCIExpress
Specification,Revision1.1.
Vendor and Device Identification
ThePCIConfigurationregisterreservedforthevendorIDhasthevalueof$114A,
whichdesignatesGE.ThePCIConfigurationregisterreservedforthedeviceID
hasthevalueof$5565,whichisGE’sboardtype.
Subsystem Vendor ID and Subsystem ID
ThePCIConfigurationregisterreservedforthesubsystemvendorIDhasthe
valueof$1556,whichdesignatesPLDApplications.ThePCIConfiguration
registerreservedforthesubsystemIDhasthevalueof$0080,whichisthePLD
ApplicationsPCI‐Xcoreidentificationnumber.
Block Diagram
Figure 1 Block Diagram of PCIE-5565PIORC
133 MHz
Memory
32-bit Data
SERDES
106.25 MHz16-bit
2.125 GHz
Optics
Fiber-Optic Network
4-bit Parity
x4 PCIE
Rx Tx
FIFO
FIFO
Main FPGA
PCIe Core

10 PCIE-5565PIORC Reflective Memory Board
Figure 2 Typical Reflective Memory Network
PCI WorkStation
with
PCI-5565PIORC NODE 1
PCI-5565PIORC
VMEbus Chassis
with
PMC-5565PIORC
NODE 255
Up to 300m
between nodes
for multimode
VMEbus Chassis
with
VMIVME-5565
NODE 0
VMIVME
VMIVME
5565
5565
VMIVME
-5565
PMC-5565PIORC
Up to 10km
between nodes
for single mode

Overview 11
References
PCIExpress™CardElectromechanicalSpecificationRevision1.1
March28,2005
PCIExpressBaseSpecification,Revision1.1
March28,2005

12 PCIE-5565PIORC Reflective Memory Board
Organization
Thismanualiscomposedofthefollowingchapters:
OverviewprovidesageneraldescriptionofthePCIE‐5565PIORC,andGeneral
Safetytermsandsymbols.
Chapter1HandlingandInstallationdescribesunpackingandinstallationofthe
hardware.
Chapter2TheoryofOperationdescribestheproduct’sfeaturesandfunctionality.
Chapter3ProgrammingdescribesPCIConfigurationRegistersandother
registersforprogrammingandinstallation.
MaintenanceprovidesGE’scontactinformationrelativetothecareand
maintenanceoftheunit.
Complianceprovidestheapplicableinformationregardingregulatory
compliance.

Overview 13
Safety Summary
Thefollowinggeneralsafetyprecautionsmustbeobservedduringallphasesof
theoperation,serviceandrepairofthisproduct.Failuretocomplywiththese
precautionsorwithspecificwarningselsewhereinthismanualviolatessafety
standardsofthedesign,manufacture,andintendeduseofthisproduct.
GEassumesnoliabilityforthecustomerʹsfailuretocomplywiththese
requirements.
Ground the
System
Tominimizeshockhazard,thechassisandsystemcabinetmustbeconnectedto
anelectricalground.Athree‐conductorACpowercableshouldbeused.The
powercablemusteitherbepluggedintoanapprovedthree‐contactelectrical
outletorusedwithathree‐contacttotwo‐contactadapterwiththegrounding
wire(green)firmlyconnectedtoanelectricalground(safetyground)atthepower
outlet.
Do Not Operate in
an Explosive
Atmosphere
Donotoperatethesysteminthepresenceofflammablegasesorfumes.Operation
ofanyelectricalsysteminsuchanenvironmentconstitutesadefinitesafety
hazard.
Keep Away from
Live Circuits
Operatingpersonnelmustnotremoveproductcovers.Componentreplacement
andinternaladjustmentsmustbemadebyqualifiedmaintenancepersonnel.Do
notreplacecomponentswithpowercableconnected.Undercertainconditions,
dangerousvoltagesmayexistevenwiththepowercableremoved.Toavoid
injuries,alwaysdisconnectpoweranddischargecircuitsbeforetouchingthem.
Do Not Service or
Adjust Alone
Donotattemptinternalserviceoradjustmentunlessanotherpersoncapableof
renderingfirstaidandresuscitationispresent.
Do Not Substitute
Parts or Modify
System
Becauseofthedangerofintroducingadditionalhazards,donotinstallsubstitute
partsorperformanyunauthorizedmodificationtotheproduct.Returnthe
producttoGEforserviceandrepairtoensurethatsafetyfeaturesaremaintained.
Dangerous
Procedure
Warnings
Warnings,suchastheexamplebelow,precedeonlypotentiallydangerous
proceduresthroughoutthismanual.Instructionscontainedinthewarningsmust
befollowed.
WARNING
Dangerous voltages, capable of causing death, are present in this system.
Use extreme caution when handling, testing and adjusting.

14 PCIE-5565PIORC Reflective Memory Board
Warnings,
Cautions
and Notes
WARNING
WARNING denotes a hazard. It calls attention to a procedure, practice, or
condition, which, if not correctly performed or adhered to, could result in
injury or death to personnel.
CAUTION
CAUTION denotes a hazard. It calls attention to an operating procedure,
practice, or condition, which, if not correctly performed or adhered to, could
result in damage to or destruction of part or all of the system.
NOTE
NOTE denotes important information. It calls attention to a procedure, practice, or condition which
is essential to highlight.
TIP
Tip denotes a bit of expert information.
LINK
This is link text.

Handling and Installation 15
1 • Handling and Installation
Thischapterdescribestheinstallationandconfigurationoftheboard.Cable
configurationandboardlayoutareillustratedinthischapter.
1.1 Unpacking Procedures
Anyprecautionsfoundintheshippingcontainershouldbeobserved.Allitems
shouldbecarefullyunpackedandthoroughlyinspectedfordamagethatmight
haveoccurredduringshipment.Theboard(s)shouldbecheckedforbroken
components,damagedprintedcircuitboard(s),heatdamageandothervisible
contamination.Allclaimsarisingfromshippingdamageshouldbefiledwiththe
carrierandacompletereportsenttoGETechnicalSupport.
1.2 Handling Precaution
SomeofthecomponentsassembledonGE’sproductsmaybesensitiveto
electrostaticdischargeanddamagemayoccuronboardsthataresubjectedtoa
high‐energyelectrostaticfield.Whentheboardisplacedonabenchfor
configuring,etc.,itissuggestedthatconductivematerialshouldbeplacedunder
theboardtoprovideaconductiveshunt.Unusedboardsshouldbestoredinthe
sameprotectiveboxesinwhichtheywereshipped.

16 PCIE-5565PIORC Reflective Memory Board
1.3 Switch S1 and S2 Configuration
PriortoinstallingtheRFM‐5565inahostsystem,thedesirednodeIDmustbeset
usingswitchS2.EachnodeinthenetworkmusthaveauniquenodeID.See
Figure1‐1onpage18forthelocationofswitchS2.
SwitchS2correspondsto8nodeIDselectsignallines.The8nodeIDselectlines
permitanybinarynodeIDfrom0to$FF(255decimal).SwitchS2position1
correspondstotheleastsignificantnodeIDlineandswitchS2position8
correspondstothemostsignificantnodeIDline.PlacingswitchS2intheOFF
positionsetsthebinarynodeIDlinelow(0),whileplacingswitchS2intheON
positionsetsthebinarynodeIDlinehigh(1).Table1‐1onpage17provides
examplesofpossiblenodeIDs.
1.3.1 Before Installation Switch S1 and S2 Configuration
NOTE
ALL nodes on the ring MUST be configured for the SAME transfer mode, either redundant or non-
redundant transfer mode. A mismatch of this setting will result in certain packets being removed
from the ring, and that data will be lost.
NOTE
No more than one node on the ring should be configured with Rogue Master 0 enabled. Certain
packets will be removed from the ring when two or more nodes are configured with Rogue
Master 0 enabled, and that data will be lost.
NOTE
No more than one node on the ring should be configured with Rogue Master 1 enabled. Certain
packets will be removed from the ring when two or more nodes are configured with Rogue
Master 1 enabled, and that data will be lost.
PriortoinstallingtheRFM‐5565inthehostsystem,switchS1mustbeconfigured
fortheappropriatemodeofoperation.SwitchS1controlssixfunctionsonthe
board.SettingsonSwitchS1shouldonlybechangedwhilepowerisoff.
1.S1position1selectsthenon‐redundant(OFFposition)orredundantnet‐
worktransfermodes.
2.S1position2selectsbetweenthelownetworkusage(ONposition)ofthe
classic5565boardsorthehigherperformanceachievableonthisboard(OFF
position).
3.S1positions3and4selectthePCIwindowsizeforPIOmemoryaccesses.
Thedefault(whenbothswitchpositions3and4areOFF)istousethefull
installedmemorysize.Thereducedmemorywindowsizechoicesare
64MByte,16MByteor2MByte.
4.S1position5enables(ONposition)ordisablestheRogueMaster0function.
5.S1position6enables(ONposition)ordisablestheRogueMaster1function.
6.S1position8selectsbetweenthefactorydefaultcontrollogic(ONposition)
orthemostrecentcontrollogicflashedtotheboard(OFFposition).
S1position7iscurrentlyreservedandshouldnotbeused(leftintheOFF
position).

Handling and Installation 17
NOTE
S1 position 8 should be set in the ON position only when a flash update of the control logic has
failed. After a successful flash update of the control logic, S1 position 8 should be set in the OFF
position.
Table 1-1 Example Node ID Switch S2 RFM-5565
S2
Position 8
S2
Position 7
S2
Position 6
S2
Position 5
S2
Position 4
S2
Position 3
S2
Position 2
S2
Position 1
Node ID
Hex (Dec.)
ON ON ON ON ON ON ON ON $FF (255)
ON OFF OFF OFF OFF OFF OFF OFF $80 (128)
OFF ON OFF OFF OFF OFF OFF OFF $40 (64)
OFF OFF ON OFF OFF OFF OFF OFF $20 (32)
OFF OFF OFF ON OFF OFF OFF OFF $10 (16)
OFF OFF OFF OFF ON OFF OFF OFF $8 (8)
OFF OFF OFF OFF OFF ON OFF OFF $4 (4)
OFF OFF OFF OFF OFF OFF ON OFF $2 (2)
OFF OFF OFF OFF OFF OFF OFF ON $1 (1)
OFF OFF OFF OFF OFF OFF OFF OFF $0 (0)
Factory Default: S2 positions 1 through 8 OFF
Table 1-2 Switch S1 Configuration RFM-5565
Position 1 OFF (non-redundant mode)
Position 1 ON (redundant mode)
Position 2 OFF (higher performance achievable)
Position 2 ON (low network usage)
Position 5 OFF (disables Rogue Master 0)
Position 5 ON (enables Rogue Master 0)
Position 6 OFF (disables Rogue Master 1)
Position 6 ON (enables Rogue Master 1)
Position 8 OFF (most recent control logic)
Position 8 ON (original factory control logic)
Factory Defaults
Positions 1-8 OFF
PCI Window Size S1 Position 3 S1 Position 4
Default Off Off
64 MByte On Off
16 MByte Off On
2 MByte On On

18 PCIE-5565PIORC Reflective Memory Board
Figure 1-1 S1 and S2 Location PCIE-5565PIORC
S1S2

Handling and Installation 19
1.4 Physical Installation
CAUTION
Do not install or remove the board while power is applied.
HostPCIExpresscompatiblesitesvarywidelyinappearanceandboard
installationprocedures.GErecommendsexaminingthehostsysteminstallation
procedurespriortoinstallingthisboard.Thefollowingprocedureoutlinesthe
installationofthePCIE‐5565PIORContoasuitablemotherboardwithanavailable
PCIeconnector(x4,x8,orx16).
1.Openthesystemchassis.EnsurethatthenodeIDhasbeensetpriortoinstal‐
lation.Also,setuptheboardforthedesiredmodeofoperation.SeeSection
SwitchS1andS2Configurationonpage16.
2.InstallthePCIE‐5565PIORCfirmlyintothePCIeconnector(refertoFigure1‐
2onpage19forinstallationofthePCIE‐5565PIORC).Installthescrewto
securethePCIE‐5565PIORCtothechassis.
3.Closethesystemchassis,applypower.
Figure 1-2 Installing the PCIE-5565PIORC
ThisPCIE‐5565PIORCcomesintwophysicalformfactors:lowprofileand
standardheight.
NOTE
The PCIE-5565PIORC is designed to interface with any suitable PCIe compliant motherboard using
a direct PCIe x4 lane interface, or larger; compliant with Revision 1.1 of the PCI Express
Specification.
115
115
Side View
Isometric View
PCIE-5565PIORC
PCIE-5565PIORC

20 PCIE-5565PIORC Reflective Memory Board
1.5 Front Panel Description
ThePCIE‐5565PIORChasanopticaltransceiverandthreeLEDslocatedonthe
frontpanelillustratedinthefigurebelow.Table1‐3onpage21outlinesthefront
panel’sLEDs.Theportlabeled“RX”isthereceiverandtheportlabeled“TX”is
thetransmitter.ThePCIE‐5565PIORCuses“LC”typefiber‐opticcables.
Figure 1-3 Low Profile and Standard Front Panels of the PCIE-5565PIORC
CAUTION
When fiber-optic cables are not connected, the supplied dust caps need to be
installed to keep dust and dirt out of the optics. Do not power up the
PCIE-5565PIORC without the fiber-optic cables installed. This could cause eye
injuries.
STATUS
RX RECEIVER
CONNECTION
TX TRANSMITTER
CONNECTION
(RED)
SIGNAL DETECT
(YELLOW)
(GREEN)
OWN DATA
Low Profile Front Pane
l
Standard Front Panel