Geehy SEMICONDUCTOR APM32F030x4x6x8xC User manual

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User Manual
APM32F030x4x6x8xC
Arm® Cortex® -M0+ based 32-bit MCU
Version: V1.7

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Contents
1Introduction and Document Description Rules................................... 6
1.1 Introduction..................................................................................................................6
1.2 Document Description Rules ......................................................................................6
2System Architecture .............................................................................. 9
2.1 Full Name and Abbreviation Description of Terms......................................................9
2.2 System Architecture Block Diagram ...........................................................................9
2.3 Memory Mapping ......................................................................................................11
2.4 Startup Configuration ................................................................................................11
3FLASH Memory .................................................................................... 12
3.1 Full Name and Abbreviation Description of Terms....................................................12
3.2 Main Characteristics..................................................................................................12
3.3 Flash Memory Structure............................................................................................12
3.4 Functional Description ..............................................................................................13
3.5Register Address Mapping........................................................................................17
3.6 Register Functional Description................................................................................18
4System Configuration Controller (SYSCFG) ..................................... 22
4.1 Full Name and Abbreviation Description of Terms....................................................22
4.2 Register Address Mapping........................................................................................22
4.3 Register Functional Description................................................................................22
5Reset and Clock Management (RCM) ................................................ 28
5.1 Full Name and Abbreviation Description of Terms....................................................28
5.2 Reset Functional Description ....................................................................................28
5.3 Functional Description of Clock Management ..........................................................30
5.4 Register Address Mapping........................................................................................36
5.5 Register Functional Description................................................................................37
6Power Management Unit (PMU).......................................................... 53
6.1 Full Name and Abbreviation Description of Terms....................................................53
6.2 Introduction................................................................................................................53
6.3 Structure Block Diagram ...........................................................................................53
6.4 Functional Description ..............................................................................................54
6.5 Register Address Mapping........................................................................................57
6.6 Register Functional Description................................................................................57
7Nested Vector Interrupt Controller (NVIC) ......................................... 59
7.1 Full Name and Abbreviation Description of Terms....................................................59
7.2 Introduction................................................................................................................59

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7.3 Main Characteristics..................................................................................................59
7.4 Interrupt and Exception Vector Table........................................................................59
8External Interrupt and Event Controller (EINT) ................................. 61
8.1 Introduction................................................................................................................61
8.2 Functional Description ..............................................................................................61
8.3 Register Address Mapping........................................................................................63
8.4 Register Functional Description................................................................................63
9Direct Memory Access (DMA)............................................................. 66
9.1 Introduction................................................................................................................66
9.2 Main Characteristics..................................................................................................66
9.3 Functional Description ..............................................................................................66
9.4Register Address Mapping........................................................................................72
9.5 Register Functional Description................................................................................73
10 Debug MCU (DBGMCU)....................................................................... 77
10.1 Full Name and Abbreviation Description of Terms....................................................77
10.2 Introduction................................................................................................................77
10.3 Main Characteristics..................................................................................................77
10.4 Functional Description ..............................................................................................78
10.5 Register Address Mapping........................................................................................78
10.6 Register Functional Description................................................................................78
11 General-purpose/Alternate Function Input/Output Pin (GPIO/AFIO)82
11.1 Full Name and Abbreviation Description of Terms....................................................82
11.2 Main Characteristics..................................................................................................82
11.3 Structure Block Diagram ...........................................................................................83
11.4 Functional Description ..............................................................................................83
11.5 Register Address Mapping........................................................................................88
11.6 Register Functional Description................................................................................88
12 Timer Overview .................................................................................... 93
12.1 Full Name and Abbreviation Description of Terms....................................................93
12.2 Timer Category and Main Difference........................................................................93
13 Advanced Timer (TMR1)...................................................................... 96
13.1 Introduction................................................................................................................96
13.2 Main Characteristics..................................................................................................96
13.3 Structure Block Diagram ...........................................................................................97
13.4 Functional Description ..............................................................................................97
13.5 Register Address Mapping......................................................................................113
13.6 Register Functional Description..............................................................................114

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14 General-purpose Timer (TMR3) ........................................................ 131
14.1 Introduction..............................................................................................................131
14.2 Main Characteristics................................................................................................131
14.3 Structure Block Diagram .........................................................................................132
14.4 Functional Description ............................................................................................132
14.5 Register Address Mapping......................................................................................145
14.6 Register Functional Description..............................................................................146
15 General-purpose Timer (TMR14) ...................................................... 160
15.1 Introduction..............................................................................................................160
15.2 Main Characteristics................................................................................................160
15.3 Structure Block Diagram .........................................................................................160
15.4 Functional Description ............................................................................................161
15.5 Register Address Mapping......................................................................................168
15.6 Register Functional Description..............................................................................168
16 General-purpose Timer (TMR15/16/17) ............................................ 175
16.1 Introduction..............................................................................................................175
16.2 Main Characteristics................................................................................................175
16.3 Structure Block Diagram .........................................................................................176
16.4 Functional Description ............................................................................................177
16.5 TMR15 Register Address Mapping.........................................................................188
16.6 TMR15 Register Functional Description.................................................................188
16.7 TMR16 and TMR17 Register Address Mapping.....................................................201
16.8 TMR16 and TMR17 Register Functional Description.............................................201
17 Basic Timer (TMR6/TMR7)................................................................. 212
17.1 Introduction..............................................................................................................212
17.2 Main Characteristics................................................................................................212
17.3 Structure Block Diagram .........................................................................................212
17.4 Functional Description ............................................................................................212
17.5 Register Address Mapping......................................................................................214
17.6 Register Functional Description..............................................................................214
18 Infrared Timer (IRTMR) ...................................................................... 217
18.1 Introduction..............................................................................................................217
18.2 Functional Description ............................................................................................217
19 Watchdog Timer (WDT) ..................................................................... 218
19.1 Introduction..............................................................................................................218
19.2 Independent Watchdog...........................................................................................218
19.3 Window Watchdog ..................................................................................................220

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19.4 IWDT Register Address Mapping............................................................................221
19.5 IWDT Register Functional Description....................................................................222
19.6 WWDT Register Address Mapping .........................................................................224
19.7 WWDT Register Functional Description .................................................................224
20 Real-time clock (RTC)........................................................................ 226
20.1 Full Name and Abbreviation Description of Terms..................................................226
20.2 Introduction..............................................................................................................226
20.3 Main Characteristics................................................................................................226
20.4 Structure Block Diagram .........................................................................................227
20.5 Functional Description ............................................................................................228
20.6 Register Address Mapping......................................................................................233
20.7 Register Functional Description..............................................................................234
21 Universal Synchronous/Asynchronous Transceiver (USART) ...... 246
21.1 Full Name and Abbreviation Description of Terms..................................................246
21.2 Introduction..............................................................................................................246
21.3 Main Characteristics................................................................................................246
21.4 Functional Description ............................................................................................247
21.5 Register Address Mapping......................................................................................259
21.6 Register Functional Description..............................................................................260
22 Internal Integrated Circuit Interface (I2C) ........................................ 270
22.1 Full Name and Abbreviation Description of Terms..................................................270
22.2 Introduction..............................................................................................................270
22.3 Main Characteristics................................................................................................270
22.4 Structure Block Diagram .........................................................................................271
22.5 Functional Description ............................................................................................272
22.6 Register Address Mapping......................................................................................282
22.7 Register Functional Description..............................................................................282
23 Serial Peripheral Interface (SPI) ....................................................... 292
23.1 Full Name and Abbreviation Description of Terms..................................................292
23.2 Introduction..............................................................................................................292
23.3 Main Characteristics................................................................................................292
23.4 Functional Description ............................................................................................293
23.5 Register Address Mapping......................................................................................304
23.6 Register Functional Description..............................................................................304
24 Analog/Digital Converter (ADC).........................................................311
24.1 Introduction..............................................................................................................311
24.2 Main Characteristics................................................................................................311

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24.3 Functional Description ............................................................................................312
24.4 Register Address Mapping......................................................................................316
24.5 Register Functional Description..............................................................................317
25 Cyclic Redundancy Check Computing Unit (CRC) ......................... 323
25.1 Introduction..............................................................................................................323
25.2 Functional Description ............................................................................................323
25.3 Register Address Mapping......................................................................................323
25.4 Register Functional Description..............................................................................324
26 Chip Electronic Signature................................................................. 326
26.1 Functional Description ............................................................................................326
26.2 Register Functional Description..............................................................................326
27 Version History .................................................................................. 327

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1 Introduction and Document Description Rules
1.1 Introduction
This reference manual provides application developers with all the information
about how to use MCU (micro-controller) system architecture, memory and
peripherals.
For information about Arm® Cortex® -M0+ core, please refer to Arm® Cortex®
-M0+ Technical Reference Manual; please refer to the corresponding datasheet
for detailed data such as model information, dimension and electrical
characteristics of the device; for all MCU series models, please refer to the
corresponding data manual for memory mapping, peripheral existence and their
number.
1.2 Document Description Rules
"Register Functional Description" Rules
（1）Control (CTRL) registers are all "set to 1 and cleared by software",
unless otherwise specified.
（2）The control registers are usually followed by verb abbreviations to make
a distinction. The verbs can be: EN-Enable, CFG-Configure, D-Disable,
SET-Setup and SEL-Select
（3）The state register abbreviation is usually followed by FLG to make a
difference.
（4）The value and data registers usually include V, VALUE, D and DATA,
which are not followed by verbs, such as: xxPSC and CNT.
Full Name and Abbreviation Description of Terms
Table 1 R/W Abbreviation and Description
R/W
Description
Abbreviation
read/write
Software can read and write this bit.
R/W
read-only
Software can only read this bit.
R
write-only
Software can only write this bit, and after reading this bit, the reset
value will be returned.
W
read/clear
The software can read this bit and clear it by writing 1. Writing 0 has
no effect on this bit.
RC_W1
read/clear
The software can read this bit and clear it by writing 0. Writing 1 has
no effect on this bit.
RC_W0
read/clear by
read
The software can read this bit, reading this bit will automatically clear
it to 0, and writing this bit is invalid.
RC_R
read/set
The software can read and set this bit, and writing 0 has no effect on
this bit.
R/S
read-only write
trigger
The software can read this bit and writing 0 or 1 can trigger an event
but has no effect on the value of this bit.
RT_W
toggle
The software can flip this bit only by writing 1 and writing 0 has no
effect on this bit.
T
Table 2 Functional Description and Full Name and Abbreviation of Terms of Commonly
Used Registers
Full name in English
English abbreviation

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Full name in English
English abbreviation
Enable
EN
Disable
D
Clear
CLR
Select
SEL
Configure
CFG
Contrl
CTRL
Controller
C
Reset
RST
Stop
STOP
Set
SET
Load
LD
Calibration
CAL
Initialize
INIT
Error
ERR
Status
STS
Ready
RDY
Software
SW
Hardware
HW
Source
SRC
System
SYS
Peripheral
PER
Address
ADDR
Direction
DIR
Clock
CLK
Input
I
Output
O
Interrupt
INT
Data
DATA
Size
SIZE
Divider
DIV
Prescaler
PSC
Multiplier
MUL
Period
PRD

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Table 3 Full Name and Abbreviation of Modules
Full name in English
English abbreviation
Reset and Clock Management
RCM
Power Management Unit
PMU
Nested Vector Interrupt Controller
NVIC
External Interrupt /Event Controller
EINT
Direct Memory Access
DMA
Debug MCU
DBG MCU
General-Purpose Input Output Pin
GPIO
Alternate Function Input Output Pin
AFIO
Timer
TMR
Watchdog Timer
WDT
Independent Watchdog Timer
IWDT
Windows Watchdog Timer
WWDT
Real-Time Clock
RTC
Universal Synchronous
Asynchronous Receiver Transmitter
USART
Inter-integrated Circuit Interface
I2C
Serial Peripheral Interface
SPI
Inter-IC Sound Interface
I2S
Analog-to-Digital Converter
ADC
Cyclic Redundancy Check
Calculation Unit
CRC

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2 System Architecture
2.1 Full Name and Abbreviation Description of Terms
Table 4 Full Name and Abbreviation Description of Terms
Full name in English
English abbreviation
Advanced High-Performance Bus
AHB
Advanced Peripheral Bus
APB
2.2 System Architecture Block Diagram
The main system mainly consists of two master modules and four slave modules.
The main modules are Arm® Cortex® -M0+ core and general-purpose DMA. The
slave modules are internal SRAM, internal flash memory Flash, AHB2 bus
connecting all GPIO ports, and AHB1/APB bridges on AHB1 bus, among which,
AHB1/APB bridges connect all peripherals.
These are connected through a multi-level AHB bus architecture, as shown in
the figure below: