Geehy SEMICONDUCTOR APM32F030x4x6x8xC User manual

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User Manual
APM32F030x4x6x8xC
Arm® Cortex® -M0+ based 32-bit MCU
Version: V1.7

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Contents
1Introduction and Document Description Rules................................... 6
1.1 Introduction..................................................................................................................6
1.2 Document Description Rules ......................................................................................6
2System Architecture .............................................................................. 9
2.1 Full Name and Abbreviation Description of Terms......................................................9
2.2 System Architecture Block Diagram ...........................................................................9
2.3 Memory Mapping ......................................................................................................11
2.4 Startup Configuration ................................................................................................11
3FLASH Memory .................................................................................... 12
3.1 Full Name and Abbreviation Description of Terms....................................................12
3.2 Main Characteristics..................................................................................................12
3.3 Flash Memory Structure............................................................................................12
3.4 Functional Description ..............................................................................................13
3.5Register Address Mapping........................................................................................17
3.6 Register Functional Description................................................................................18
4System Configuration Controller (SYSCFG) ..................................... 22
4.1 Full Name and Abbreviation Description of Terms....................................................22
4.2 Register Address Mapping........................................................................................22
4.3 Register Functional Description................................................................................22
5Reset and Clock Management (RCM) ................................................ 28
5.1 Full Name and Abbreviation Description of Terms....................................................28
5.2 Reset Functional Description ....................................................................................28
5.3 Functional Description of Clock Management ..........................................................30
5.4 Register Address Mapping........................................................................................36
5.5 Register Functional Description................................................................................37
6Power Management Unit (PMU).......................................................... 53
6.1 Full Name and Abbreviation Description of Terms....................................................53
6.2 Introduction................................................................................................................53
6.3 Structure Block Diagram ...........................................................................................53
6.4 Functional Description ..............................................................................................54
6.5 Register Address Mapping........................................................................................57
6.6 Register Functional Description................................................................................57
7Nested Vector Interrupt Controller (NVIC) ......................................... 59
7.1 Full Name and Abbreviation Description of Terms....................................................59
7.2 Introduction................................................................................................................59

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7.3 Main Characteristics..................................................................................................59
7.4 Interrupt and Exception Vector Table........................................................................59
8External Interrupt and Event Controller (EINT) ................................. 61
8.1 Introduction................................................................................................................61
8.2 Functional Description ..............................................................................................61
8.3 Register Address Mapping........................................................................................63
8.4 Register Functional Description................................................................................63
9Direct Memory Access (DMA)............................................................. 66
9.1 Introduction................................................................................................................66
9.2 Main Characteristics..................................................................................................66
9.3 Functional Description ..............................................................................................66
9.4Register Address Mapping........................................................................................72
9.5 Register Functional Description................................................................................73
10 Debug MCU (DBGMCU)....................................................................... 77
10.1 Full Name and Abbreviation Description of Terms....................................................77
10.2 Introduction................................................................................................................77
10.3 Main Characteristics..................................................................................................77
10.4 Functional Description ..............................................................................................78
10.5 Register Address Mapping........................................................................................78
10.6 Register Functional Description................................................................................78
11 General-purpose/Alternate Function Input/Output Pin (GPIO/AFIO)82
11.1 Full Name and Abbreviation Description of Terms....................................................82
11.2 Main Characteristics..................................................................................................82
11.3 Structure Block Diagram ...........................................................................................83
11.4 Functional Description ..............................................................................................83
11.5 Register Address Mapping........................................................................................88
11.6 Register Functional Description................................................................................88
12 Timer Overview .................................................................................... 93
12.1 Full Name and Abbreviation Description of Terms....................................................93
12.2 Timer Category and Main Difference........................................................................93
13 Advanced Timer (TMR1)...................................................................... 96
13.1 Introduction................................................................................................................96
13.2 Main Characteristics..................................................................................................96
13.3 Structure Block Diagram ...........................................................................................97
13.4 Functional Description ..............................................................................................97
13.5 Register Address Mapping......................................................................................113
13.6 Register Functional Description..............................................................................114

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14 General-purpose Timer (TMR3) ........................................................ 131
14.1 Introduction..............................................................................................................131
14.2 Main Characteristics................................................................................................131
14.3 Structure Block Diagram .........................................................................................132
14.4 Functional Description ............................................................................................132
14.5 Register Address Mapping......................................................................................145
14.6 Register Functional Description..............................................................................146
15 General-purpose Timer (TMR14) ...................................................... 160
15.1 Introduction..............................................................................................................160
15.2 Main Characteristics................................................................................................160
15.3 Structure Block Diagram .........................................................................................160
15.4 Functional Description ............................................................................................161
15.5 Register Address Mapping......................................................................................168
15.6 Register Functional Description..............................................................................168
16 General-purpose Timer (TMR15/16/17) ............................................ 175
16.1 Introduction..............................................................................................................175
16.2 Main Characteristics................................................................................................175
16.3 Structure Block Diagram .........................................................................................176
16.4 Functional Description ............................................................................................177
16.5 TMR15 Register Address Mapping.........................................................................188
16.6 TMR15 Register Functional Description.................................................................188
16.7 TMR16 and TMR17 Register Address Mapping.....................................................201
16.8 TMR16 and TMR17 Register Functional Description.............................................201
17 Basic Timer (TMR6/TMR7)................................................................. 212
17.1 Introduction..............................................................................................................212
17.2 Main Characteristics................................................................................................212
17.3 Structure Block Diagram .........................................................................................212
17.4 Functional Description ............................................................................................212
17.5 Register Address Mapping......................................................................................214
17.6 Register Functional Description..............................................................................214
18 Infrared Timer (IRTMR) ...................................................................... 217
18.1 Introduction..............................................................................................................217
18.2 Functional Description ............................................................................................217
19 Watchdog Timer (WDT) ..................................................................... 218
19.1 Introduction..............................................................................................................218
19.2 Independent Watchdog...........................................................................................218
19.3 Window Watchdog ..................................................................................................220

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19.4 IWDT Register Address Mapping............................................................................221
19.5 IWDT Register Functional Description....................................................................222
19.6 WWDT Register Address Mapping .........................................................................224
19.7 WWDT Register Functional Description .................................................................224
20 Real-time clock (RTC)........................................................................ 226
20.1 Full Name and Abbreviation Description of Terms..................................................226
20.2 Introduction..............................................................................................................226
20.3 Main Characteristics................................................................................................226
20.4 Structure Block Diagram .........................................................................................227
20.5 Functional Description ............................................................................................228
20.6 Register Address Mapping......................................................................................233
20.7 Register Functional Description..............................................................................234
21 Universal Synchronous/Asynchronous Transceiver (USART) ...... 246
21.1 Full Name and Abbreviation Description of Terms..................................................246
21.2 Introduction..............................................................................................................246
21.3 Main Characteristics................................................................................................246
21.4 Functional Description ............................................................................................247
21.5 Register Address Mapping......................................................................................259
21.6 Register Functional Description..............................................................................260
22 Internal Integrated Circuit Interface (I2C) ........................................ 270
22.1 Full Name and Abbreviation Description of Terms..................................................270
22.2 Introduction..............................................................................................................270
22.3 Main Characteristics................................................................................................270
22.4 Structure Block Diagram .........................................................................................271
22.5 Functional Description ............................................................................................272
22.6 Register Address Mapping......................................................................................282
22.7 Register Functional Description..............................................................................282
23 Serial Peripheral Interface (SPI) ....................................................... 292
23.1 Full Name and Abbreviation Description of Terms..................................................292
23.2 Introduction..............................................................................................................292
23.3 Main Characteristics................................................................................................292
23.4 Functional Description ............................................................................................293
23.5 Register Address Mapping......................................................................................304
23.6 Register Functional Description..............................................................................304
24 Analog/Digital Converter (ADC).........................................................311
24.1 Introduction..............................................................................................................311
24.2 Main Characteristics................................................................................................311

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24.3 Functional Description ............................................................................................312
24.4 Register Address Mapping......................................................................................316
24.5 Register Functional Description..............................................................................317
25 Cyclic Redundancy Check Computing Unit (CRC) ......................... 323
25.1 Introduction..............................................................................................................323
25.2 Functional Description ............................................................................................323
25.3 Register Address Mapping......................................................................................323
25.4 Register Functional Description..............................................................................324
26 Chip Electronic Signature................................................................. 326
26.1 Functional Description ............................................................................................326
26.2 Register Functional Description..............................................................................326
27 Version History .................................................................................. 327

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1 Introduction and Document Description Rules
1.1 Introduction
This reference manual provides application developers with all the information
about how to use MCU (micro-controller) system architecture, memory and
peripherals.
For information about Arm® Cortex® -M0+ core, please refer to Arm® Cortex®
-M0+ Technical Reference Manual; please refer to the corresponding datasheet
for detailed data such as model information, dimension and electrical
characteristics of the device; for all MCU series models, please refer to the
corresponding data manual for memory mapping, peripheral existence and their
number.
1.2 Document Description Rules
"Register Functional Description" Rules
（1）Control (CTRL) registers are all "set to 1 and cleared by software",
unless otherwise specified.
（2）The control registers are usually followed by verb abbreviations to make
a distinction. The verbs can be: EN-Enable, CFG-Configure, D-Disable,
SET-Setup and SEL-Select
（3）The state register abbreviation is usually followed by FLG to make a
difference.
（4）The value and data registers usually include V, VALUE, D and DATA,
which are not followed by verbs, such as: xxPSC and CNT.
Full Name and Abbreviation Description of Terms
Table 1 R/W Abbreviation and Description
R/W
Description
Abbreviation
read/write
Software can read and write this bit.
R/W
read-only
Software can only read this bit.
R
write-only
Software can only write this bit, and after reading this bit, the reset
value will be returned.
W
read/clear
The software can read this bit and clear it by writing 1. Writing 0 has
no effect on this bit.
RC_W1
read/clear
The software can read this bit and clear it by writing 0. Writing 1 has
no effect on this bit.
RC_W0
read/clear by
read
The software can read this bit, reading this bit will automatically clear
it to 0, and writing this bit is invalid.
RC_R
read/set
The software can read and set this bit, and writing 0 has no effect on
this bit.
R/S
read-only write
trigger
The software can read this bit and writing 0 or 1 can trigger an event
but has no effect on the value of this bit.
RT_W
toggle
The software can flip this bit only by writing 1 and writing 0 has no
effect on this bit.
T
Table 2 Functional Description and Full Name and Abbreviation of Terms of Commonly
Used Registers
Full name in English
English abbreviation

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Full name in English
English abbreviation
Enable
EN
Disable
D
Clear
CLR
Select
SEL
Configure
CFG
Contrl
CTRL
Controller
C
Reset
RST
Stop
STOP
Set
SET
Load
LD
Calibration
CAL
Initialize
INIT
Error
ERR
Status
STS
Ready
RDY
Software
SW
Hardware
HW
Source
SRC
System
SYS
Peripheral
PER
Address
ADDR
Direction
DIR
Clock
CLK
Input
I
Output
O
Interrupt
INT
Data
DATA
Size
SIZE
Divider
DIV
Prescaler
PSC
Multiplier
MUL
Period
PRD

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Table 3 Full Name and Abbreviation of Modules
Full name in English
English abbreviation
Reset and Clock Management
RCM
Power Management Unit
PMU
Nested Vector Interrupt Controller
NVIC
External Interrupt /Event Controller
EINT
Direct Memory Access
DMA
Debug MCU
DBG MCU
General-Purpose Input Output Pin
GPIO
Alternate Function Input Output Pin
AFIO
Timer
TMR
Watchdog Timer
WDT
Independent Watchdog Timer
IWDT
Windows Watchdog Timer
WWDT
Real-Time Clock
RTC
Universal Synchronous
Asynchronous Receiver Transmitter
USART
Inter-integrated Circuit Interface
I2C
Serial Peripheral Interface
SPI
Inter-IC Sound Interface
I2S
Analog-to-Digital Converter
ADC
Cyclic Redundancy Check
Calculation Unit
CRC

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2 System Architecture
2.1 Full Name and Abbreviation Description of Terms
Table 4 Full Name and Abbreviation Description of Terms
Full name in English
English abbreviation
Advanced High-Performance Bus
AHB
Advanced Peripheral Bus
APB
2.2 System Architecture Block Diagram
The main system mainly consists of two master modules and four slave modules.
The main modules are Arm® Cortex® -M0+ core and general-purpose DMA. The
slave modules are internal SRAM, internal flash memory Flash, AHB2 bus
connecting all GPIO ports, and AHB1/APB bridges on AHB1 bus, among which,
AHB1/APB bridges connect all peripherals.
These are connected through a multi-level AHB bus architecture, as shown in
the figure below:

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Figure 1 APM32F030x4x6x8xC System Architecture Block Diagram
Bus matrix
Flash
SRAM
DMA
AHB2 bus
AHB1 bus
DMA bus
System bus
AHB1/APB
bridge
GPIOs
(A-D,F)
Flash
interface
APB bus
TMR1/3/6/7/1
4/15/16/17
RTC
WWDT
IWDT
SPI1/2
USART1-6
I2C1/2
PMU
SYSCFG
EINT
ADC
DBGMCU
Arm®Cortex®-M0+
(Fmax:48MHz)
SWD
CRC
RCM
NVIC SCB STK
Note: APM32F030x4x6x8 has no USART3-6 and no TMR7.
Table 5 Bus Name
Name
Instruction
System bus
Connect the system bus (peripheral bus) of Arm® Cortex® -M0 core and the bus matrix.
DMA bus
Connect AHB master control interface of DMA and the bus matrix.
Bus matrix
Coordinate the access of the core and DMA; consist of CPU AHB, system bus, DMA bus
and FMC, SRAM, AHB2 and AHB1/APB bridge. AHB peripheral is connected with the
system bus through the bus matrix and is allowed to access DMA.
AHB/APB
bridge
The bridge provides synchronous connection between AHB and APB buses.
The non-32-bit access to APB register will be converted into 32 bits automatically.

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2.3 Memory Mapping
The memory mapping address is totally 4GB address. The assigned addresses
include the core (including core peripherals), on-chip Flash (including main
memory area, system memory area and option bytes), on-chip SRAM, and bus
peripherals (including AHB and APB peripherals). Please refer to the data
manual of the corresponding model for specific information of various addresses.
Embedded SRAM
Built-in static SRAM. It can access by byte, half word (16 bits) or full word (32
bits). The start address of SRAM is 0x2000 0000.
2.4 Startup Configuration
APM32F MCU series realizes a special mechanism. By configuring the BOOT
pin parameter and the nBOOT1 bit in FMC_OBCS, there are three different
startup modes, namely, the system can not only start from Flash memory or
system memory, but also start from the built-in SRAM. The memory selected as
the start zone is determined by the selected startup mode.
Table 6 Startup Mode Configuration and Access Mode
Startup mode
selection pin
Startup
mode
Access mode
BOOT1
BOOT0
X
0
Main flash
memory
（Flash）
The main flash memory is mapped to the boot space, but it can
still be accessed at its original address, that is, the contents of
the flash memory can be accessed in two address areas.
0
1
System
memory
The system memory is mapped to the boot space (0x0000
0000), but it can still be accessed at its original address.
1
1
Built-in
SRAM
SRAM can be accessed only at the starting address.
Note:
（1）The boot space address is 0x0000 0000
（2）The original address of Flash is 0x0800 0000
（3）The original address of the system memory is 0x1FFF EC00
（4）The starting address of SRAM is 0x2000 0000
（5）The value of BOOT1 is negation of nBOOT1 option bit
The user can select the startup mode after reset by setting the states of BOOT1 (configuration nBOOT1)
and BOOT0 pins.
BOOT pin should keep the user's required startup configuration in standby mode. When exiting from the
standby mode, the value of boot pin will be latched.
If you choose to start from built-in SRAM, you must use NVIC's exception table and offset register to
remap the vector table to SRAM when writing the application code.
Embedded startup program
The embedded startup program is written on the production line by APEX and
stored in the system memory area.

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3 FLASH Memory
This chapter mainly introduces the storage structure, read, erase, write,
read/write protection, unlock/lock characteristics of Flash, and the involved
register functional description.
3.1 Full Name and Abbreviation Description of Terms
Table 7 Full Name and Abbreviation Description of Terms
Full name in English
English abbreviation
Flash Memory Controller
FMC
3.2 Main Characteristics
（1）Flash memory structure
Contain main memory area and information block
The capacity of main memory area is up to 256KB
The information block is divided into system memory area and option
byte
BootLoader program, 96-bit unique UID and capacity information of
main memory area are stored in system memory area, with a capacity
of:
-3KB for APM32F030x4x6x8
-8KB for APM32F030xC
The capacity of the option byte area is 16Bytes
（2）Functional Description
Read Flash
Page/Mass erase Flash
Write Flash
Read/Write protection Flash
Configure option bytes
3.3 Flash Memory Structure
Table 8 Flash Memory Structure of APM32F030x4x6x8 Series Products
Block
Name
Address area
Size (byte)
Sector
Main memory area
Page 0
0x0800 0000–0x0800 03FF
1K
Sector 0
Main memory area
Page 1
0x0800 0400–0x0800 07FF
1K
Main memory area
Page 2
0x0800 0800–0x0800 0BFF
1K
Main memory area
Page 3
0x0800 0C00–0x0800 0FFF
1K
Main memory area
…
…
…
…
Main memory area
Page 28
0x0800 7000–0x0800 73FF
1K
Fan 7
Main memory area
Page 29
0x0800 7400–0x0800 77FF
1K
Main memory area
Page 30
0x0800 7800–0x0800 7BFF
1K

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Block
Name
Address area
Size (byte)
Sector
Main memory area
Page 31
0x0800 7C00–0x0800 7FFF
1K
Main memory area
…
…
…
…
Main memory area
Page 60
0x0800 F000–0x0800 F3FF
1K
Fan 15
Main memory area
Page 61
0x0800 4000–0x0800 F7FF
1K
Main memory area
Page 62
0x0800 8000–0x0800 FBFF
1K
Main memory area
Page 63
0x0800 C000–0x0800 FFFF
1K
Information block
System memory area
0x1FFF EC00–0x1FFF F7FF
3K
-
Information block
Option byte
0x1FFF F800–0x1FFF F80F
16
-
Note: The number of pages in the main memory block of APM32F030x4x6x8 series products is related to
the Flash capacity of specific product.
Table 9 Flash Memory Structure of APM32F030xC Series Products
Block
Name
Address area
Size (byte)
Sector
Main memory area
Page 0
0x0800 0000–0x0800 07FF
2K
Sector 0
Main memory area
Page 1
0x0800 0800–0x0800 0FFF
2K
Main memory area
…
…
…
…
Main memory area
Page 62
0x0801 F000–0x0801 F7FF
2K
Fan 31
Main memory area
Page 63
0x0801 F800–0x0801 FFFF
2K
Main memory area
…
…
…
…
Main memory area
Page 126
0x0800 8000–0x0800 FBFF
2K
Fan 64
Main memory area
Page 127
0x0800 C000–0x0800 FFFF
2K
Information block
System memory area
0x1FFF D800–0x1FFF F7FF
8K
-
Information block
Option byte
0x1FFF F800–0x1FFF F80F
16
-
3.4 Functional Description
Describe the operation of main memory and information block (including system
memory area and option byte), including read, write, erase and read/write
protection.
Reading Flash includes main memory block and information block, while the
erase, write, read/write are introduced separately; the system memory area has
been written before the product leaves the factory and cannot be modified by the
user. The erase, write, and read/write protection of the module will not be
introduced.
Read Flash
Flash memory can be directly addressed, and reading Flash is affected by the
following configuration:
Wait cycle

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Different wait cycles should be configured for different system clocks:
0 wait cycle: 0<system clock≤24MHz
1 wait cycle: 24MHz<system clock≤48MHz
Prefetch buffer
It can improve the reading speed and every time it is reset, the prefetch buffer
will be automatically opened; the read interface with prefetch buffer. It can be
configured only when the system clock is consistent with AHB clock and is less
than 24MHz, and can be used only when the system clock is consistent with
AHB clock.
Half-cycle access
When the power consumption needs to be optimized, half-cycle access can be
used; at this time, the system clock and AHB clock are consistent, and the
system clock is 8MHz or less than 8MHz, then half-cycle access to Flash can be
used, otherwise, it must be turned on.
Main Memory Block
3.4.2.1 Erase main memory block
FMC supports page erase and mass erase (full erase) to initialize the contents of
the main memory area to high level (the data is represented as 0xFFFF). Before
writing to Flash, users are advised to erase the write address page. If the data of
write address is not 0xFFFF, a programming error will be triggered.
Main memory page erase
Page erase is an independent erase according to the main memory area page
selected by the program, which will not have any impact on the page not
selected for erasure.
After the correct page erase (or flash write operation) is completed, OCF of
FMC_STS register will be set. If OCIE interrupt is enabled, an operation
completion interrupt will be triggered. Users need to note that the page to be
erased must be a valid page (the valid address of the main memory area and the
address not protected by write).
Main memory mass erase
The mass erase operation will erase all the contents in the main storage area of
Flash, and the mass erase operation will erase all the data in the main memory
area, so the users need to pay special attention when using it to avoid the loss of
important data caused by misoperation.
3.4.2.2 Write main memory block
FMC supports the writing of 16-bit (half word) data in the main memory area. You
can select Debug, BootLoader, program running in SRAM, and directly reading
the erased page to judge whether the erasing is successful.
In order to ensure correct writing, it is necessary to check whether the
destination address has been erased before writing; if it is not erased, the written
data will be invalid and PEF bit of FMC_STS register will be set to "1". If the
destination address has write protection, the written data is invalid and a write
protection error will be triggered (WPEF bit of FMC_STS is set to "1").
3.4.2.3 Main memory block of read/write protection
Read/Write protection of the flash is used to prevent illegal reading/modification
of the main memory area code or data, and it is controlled by the read/write
protection configuration byte of option byte. For APM32F030x4x6x8xC series

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products, the basic unit of write protection is 4 pages (i.e. KB).
Read protection
The read protection has three levels, namely, Level 0, Level 1 and Level 2, which
are specifically described as follows:
Table 10 Difference among Read Protection Levels
Category
READPROT
Description
Level 0
0xAA
The main memory area and option byte are erasable, writable and
readable.
Level 1
Other values
except 0xAA and
0xCC
User mode: Allowed to erase, write and read the main memory area
and option byte.
Debug, SRAM running, system memory area running: Access to the
main memory area is disabled; the option byte is erasable, writable and
readable, but when the level is modified to 0, the main memory area
erase will be performed first.
Level 2
0xCC
Debug is not allowed, the main memory area and option byte cannot
be erased, written and read, and the level cannot be modified.
Write protection
Write protection control can be conducted for the corresponding page of the
main memory block by configuring the value of write protection option byte
WRP0/1/2/3. After the write protection is turned on, the content on the
corresponding page of the main memory area cannot be modified in any way.
3.4.2.4 Main memory block of unlock/lock
FMC_CTRL1 of the reset FMC will be locked by hardware, and then
FMC_CTRL1 can't be directly written, and the corresponding value must be
written to FMC_KEY according to the correct sequence to unlock FMC. The KEY
value is as follows:
KEY1=0x45670123
KEY2=0xCDEF89AB
The wrong writing sequence or wrong value will cause the program to enter the
hardware wrongly. At this time, FMC will be locked, and all FMC operations will
be invalid until it is reset next time. The users can also lock FMC through
software by writing "1" to LOCK bit of the control register 2 (FMC_CTRL2).
In each Flash programming operation, the users must follow the steps of "Flash
unlock - program by user - Flash lock", so as to avoid the risk that user code/data
is accidentally modified due to the Flash unlocking after the Flash programming
operation.
Option Byte
3.4.3.1 Erase option byte
Support erase function. After the correct option byte erase (or option byte write
operation) is completed, OCF of FMC_STS register will be set. If OCIE interrupt
is enabled, an operation completion interrupt will be triggered.
3.4.3.2 Write option byte
Eight configurable bytes of option bytes all support writing function.
3.4.3.3 Option byte of write protection
By default, the option byte is always readable and write protected. To perform
write operation (program/erase) for the option byte block, first write the correct
key sequence (the same as that of locking) in FMC_OBKEY, and then allow the
write operation of option byte block; the OBWEN bit of FLASH_CTRL2 register
indicates write enabled; clear this bit and write operation will be disabled.

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3.4.3.4 Unlock/Lock option byte
After the system reset, the option byte is locked by default. Only when the option
byte is unlocked correctly, can it be modified. The difference between option byte
unlocking and flash unlocking is that FMC_OBKEY register rather than
FMC_KEY register writes the KEY value. The option byte does not support
"software lock". The user should pay special attention to that every time after the
value of the option byte is modified, the system must be reset to make it
effective.
Functional Description of Option Byte
The option byte provides some optional functions for users, and it mainly
consists of 8 configurable bytes and corresponding complementary codes. Every
time the system is reset, the option byte area will be reloaded to the FMC_
OBCS and FMC_WRTPROT register (the option byte will only take effect each
time they are reloaded to FMC). In the process of reloading, if a certain
configurable byte does not match its reverse code, an option byte error (OBE bit
of FMC_ register is set to "1") will be triggered, and this byte will be set to "0xFF".
The information of 16 bytes in the option byte area is shown in the table below.
Table 11 Option Bytes
Address
Option byte
Initial
value
R/W
Functional description
0x1FFF F800
READPROT
0xA5
R/W
Read protection configuration
Bit [7:0]: READPROT
0xAA: Level 0
0xCC: Level 2
Others: Level 1
0x1FFF F801
nREADPROT
0x5A
R
READPROT complementary code
0x1FFF F802
UOB
0xFF
R/W
User option byte
Bit 0: WDTSEL
0: Hardware watchdog
1: Software watchdog
Bit 1: nRSTSTOP
0: Reset occurs when entering the Stop mode
1: Reset does not occur when entering the Stop
mode
Bit 2: nRSTSTB
0: Reset occurs when entering the Standby
mode
1: Reset does not occur when entering the
Standby mode
Bit 3: Reserved
Bit 4: nBOOT1
Select BOOT mode
Bit 5: VDDAMONI
0: VDDA power supply detector is disabled
1: VDDA power supply detector is enabled
Bit 6: SRAMPARITY
0: RAM parity check is disabled
1: RAM parity check is enabled
Bit 7: Reserved
0x1FFF F803
nUOB
0x00
R
UOB complementary code
0x1FFF F804
Data0
0xFF
R/W
User data byte 0
0x1FFF F805
nData0
0x00
R
Data0 complementary code

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Address
Option byte
Initial
value
R/W
Functional description
0x1FFF F806
Data1
0xFF
R/W
User data byte 1
0x1FFF F807
nData1
0x00
R
Data complementary code
0x1FFF F808
WRP0
0xFF
R/W
Write protection configuration 0
0x1FFF F809
nWRP0
0x00
R
WRP0 complementary code
0x1FFF F80A
WRP1
0xFF
R/W
Write protection configuration 1
0x1FFF F80B
nWRP1
0x00
R
WRP1 complementary code
0x1FFF F80C
WRP2
0xFF
R/W
Write protection configuration 2
0x1FFF F80D
nWRP2
0x00
R
WRP2 complementary code
0x1FFF F80E
WRP3
0xFF
R/W
Write protection configuration 3
0x1FFF F80F
nWRP3
0x00
R
WRP3 complementary code
Note: When the configurable byte and its reverse code value are "0xFF", the match will not be verified in
the reloading process
Table 12 Write Protection WRPx Function Description of Main Memory Area
Product capacity
Functional description
APM32F030x4x6
series products
Each bit in WRPx controls the write protection of 4KB (4 pages) address of the
main memory area
0: Write protection is turned on
1: Write protection is not turned on
WRP0: Page 0-31
APM32F030x8
series products
Each bit in WRPx controls the write protection of 4KB (4 pages) address of the
main memory area
0: Write protection is turned on
1: Write protection is not turned on
WRP0: Page 0-31
WRP1: Page 32-63
APM32F030xC
series products
Among Bits 0~30 in WRPx, each bit controls the write protection of 4KB (2 pages)
address of the main memory area, and Bit 31 controls the write protection of
132KB address of the main memory area
0: Write protection is turned on
1: Write protection is not turned on
WRP0: Page 0-31
WRP1: Page 32-63
Note: Flash read/write protection configuration is independent of each other. Removing the write
protection will not force the loss of the contents of the main memory area, but keep them as they are.
3.5 Register Address Mapping
Base address: 0x40022000
Table 13 FMC Register Address Mapping
Register name
Description
Offset address
FMC_CTRL1
Control register 1
0x00
FMC_KEY
Key register
0x04
FMC_OBKEY
Option byte key register
0x08
FMC_STS
State register
0x0C

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Register name
Description
Offset address
FMC_CTRL2
Control register 2
0x10
FMC_ADDR
Address register
0x14
FMC_OBCS
Option byte control/state register
0x1C
FMC_WRTPROT
Write protection register
0x20
3.6 Register Functional Description
Control register 1 (FMC_CTRL1)
Offset address: 0x00
Reset value: 0x0000 0000
Field
Name
R/W
Description
2:0
WS
R/W
Wait State Configure
000: 0 wait cycle, 0<system clock≤24MHz
001: 1 wait cycle: 24MHz<system clock≤48MHz
Others: Reserved
3
Reserved
4
PBEN
R/W
Prefetch Buffer Enable
0: Disable
1: Enable
5
PBSF
R
Prefetch Buffer Status Flag
0: In disabled state
1: In enabled state
31:6
Reserved
Key register (FMC_KEY)
Offset address: 0x04
Reset value: xxxx xxxx
Field
Name
R/W
Description
31:0
KEY
W
FMC Key
Writing the keys represented by these bits can unlock FMC. These bits can only
perform write operation, and 0 is returned when read operation is performed.
Option byte key register (FMC_OBKEY)
Offset address: 0x08
Reset value: xxxx xxxx
Field
Name
R/W
Description
31:0
OBKEY
W
Option Byte Key
Writing the keys represented by these bits can unlock the option byte write
operation. These bits can only perform write operation and 0 is returned when
read operation is performed.

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State register (FMC_STS)
Offset address: 0x0C
Reset value: 0x0000 0000
Field
Name
R/W
Description
0
BUSYF
R
Busy Flag
This bit indicates that a flash operation is in progress. These bits can only
perform write operation, and 0 is returned when read operation is performed.
1
Reserved
2
PEF
R/W
Programming Error Flag
This bit will be set by software when the value before the address is edited is
not "0xFFFF".
3
Reserved
4
WPEF
R/W
Write Protection Error Flag
This bit will be set by hardware when programming the write protection
address in FLASH.
5
OCF
R/W
Operation Complete Flag
This bit will be set by hardware when read/write operation in FLASH is
completed.
31:6
Reserved
Control register 2 (FMC_CTRL2)
Offset address: 0x10
Reset value: 0x0000 0080
Field
Name
R/W
Description
0
PG
R/W
Program
Set this bit to 1 to program Flash
1
PAGEERA
R/W
Page Erase
Set this bit to 1 to erase the page
2
MASSERA
R/W
Mass Erase
Set this bit to 1 to erase the mass.
3
Reserved
4
OBP
R/W
Option Byte Program
Set this bit to 1 to program the option byte.
5
OBE
R/W
Option Byte Erase
Set this bit to 1 to erase the option byte.
6
STA
R/W
Start Erase
This bit can be only set to 1 by software, and can be reset by clearing
STS_BUSYF bit.
7
LOCK
R/W
Lock
This bit can be written to 1 only, and when this bit is set to 1, it means that
FMC and CTRL2 registers are locked.
8
Reserved
9
OBWEN
R/W
Option Byte Write Enable
When this bit is set to 1, the option byte can be programmed.
10
ERRIE
R/W
Error interrupt Enable
0: Interrupt is disabled
1: Interrupt is enabled