Geehy SEMICONDUCTOR GW3323 User manual
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User Manual
GW3323
RISC-V based 32-bit MCU with Bluetooth
Version: V0.2
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Contents
1 Block Diagram ................................................................................................................... 5
2 System Management ........................................................................................................ 6
2.1 System Clock ...............................................................................................................................................6
2.2 Clock Register ............................................................................................................................................. 7
3 Memory Access ...............................................................................................................19
4 Low Power Mode .............................................................................................................20
4.1 1. sleep mode,500uA ................................................................................................................................ 20
4.1.1 Configuration of sleep mode ............................................................................................................................20
4.2 Power-off mode (power off, 4uA) ..............................................................................................................20
4.2.1 Configuration of power-down mode .................................................................................................................20
5 Interrupts ......................................................................................................................... 22
5.1 Feature ...................................................................................................................................................... 22
5.2 interrupt vector table ................................................................................................................................. 22
5.3 Interrupts Special Registers ......................................................................................................................24
6 WatchDog ........................................................................................................................ 27
6.1 User Guide ................................................................................................................................................ 27
6.2 WDT Special Function Registers ..............................................................................................................27
7 GPIO Management .......................................................................................................... 29
7.1 Features .................................................................................................................................................... 29
7.2 GPIO internal block diagram .....................................................................................................................29
7.3 GPIO general control register ................................................................................................................... 29
7.4 GPIO function mapping .............................................................................................................................32
7.5 External Port interrupt wake up ................................................................................................................ 34
8 DMA ..................................................................................................................................37
8.1 Feature ...................................................................................................................................................... 37
8.2 Functional configuration ............................................................................................................................37
9 Timer ................................................................................................................................ 38
9.1 Features .................................................................................................................................................... 38
9.2 Timer clock select ......................................................................................................................................39
9.3 Timer0/1/2 Special Function Registers .....................................................................................................39
9.4 Timer3/4/5 Special Function Registers .....................................................................................................40
10 RTC ...................................................................................................................................43
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10.1 Features .................................................................................................................................................... 43
10.2 Special Function Registers ....................................................................................................................... 43
10.3 Independent Power RTC Registers ..........................................................................................................44
11 UART ................................................................................................................................ 50
11.1 Features .................................................................................................................................................... 50
11.2 User Guide ................................................................................................................................................ 50
11.2.1 UART Special Function Registers ................................................................................................................... 50
12 HSUART ........................................................................................................................... 53
12.1 Features .................................................................................................................................................... 53
12.2 User Guide ................................................................................................................................................ 53
12.2.1 SYNC configure ............................................................................................................................................... 53
12.2.2 TX 1 byte with buffer ........................................................................................................................................ 53
12.2.3 TX n byte with DMA ......................................................................................................................................... 54
12.2.4 RX 1 byte with buffer ....................................................................................................................................... 54
12.2.5 RX n byte with DMA &loop buffer disable ........................................................................................................54
12.2.6 DMA RX TIMER MODE: .................................................................................................................................. 55
12.2.7 Application Note ...............................................................................................................................................55
12.3 HSUART Special Function Registers ....................................................................................................... 58
13 SPI .................................................................................................................................... 62
13.1 Features .................................................................................................................................................... 62
13.2 User Guide ................................................................................................................................................ 62
13.3 SPI Special Function Registers ................................................................................................................ 64
14 IIC ..................................................................................................................................... 66
14.1 Features .................................................................................................................................................... 66
14.2 User Guide ................................................................................................................................................ 66
14.3 IIC Special Function Registers ..................................................................................................................67
15 ADC .................................................................................................................................. 69
15.1 Features .................................................................................................................................................... 69
15.2 Channel select ...........................................................................................................................................69
15.3 User Guide ................................................................................................................................................ 69
15.4 ADC_CTL Special Function Registers ......................................................................................................70
16 DAC .................................................................................................................................. 75
16.1 Feature ...................................................................................................................................................... 75
16.2 Control use ................................................................................................................................................ 75
17 USB .................................................................................................................................. 76
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17.1 Feature ...................................................................................................................................................... 76
17.2 Control use ................................................................................................................................................ 76
18 Power Management ........................................................................................................ 77
18.1 Charging process ...................................................................................................................................... 77
18.2 Charging settings ...................................................................................................................................... 77
18.3 Charging control function .......................................................................................................................... 77
19 Bluetooth ......................................................................................................................... 78
19.1 Feature ...................................................................................................................................................... 78
19.2 SPP protocol ..............................................................................................................................................78
19.2.1 SPP protocol is based on credit flow control mechanism ................................................................................78
19.2.2 SPP use and development in SDK ..................................................................................................................79
19.3 BLE protocol ..............................................................................................................................................80
19.3.1 Flow control mechanism of BLE protocol ........................................................................................................ 81
19.3.2 Use and Development of BLE in SDK ............................................................................................................. 81
19.4 FOTA upgrade ........................................................................................................................................... 82
19.4.1 Use and development of FOTA in feature SDK ...............................................................................................82
20 Revision history .............................................................................................................. 83
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1 Block Diagram
Figure 1 GW3323 System Block Diagram
Note: Chx indicates the channel number x
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2 System Management
2.1 System Clock
Figure 2 System Clock Tree
For details, see GW3323_clock.pdf.
The maximum frequency of this chip is 160MHz, which can be set by set_sys_clk().
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Table 1 PLL clock error
PLL
clock(Hz)
Value set by PLLCON0
Theoretical
output clock
Actual output
clock
Error%
2M
configure set_sys_clk()
2M
2M
0
24M
configure set_sys_clk()
24M
24M
0
48M
DI_LDO_SEL(0x2);
DI_LDO2_SEL(0x3);
DI_EN_XRES(0x0);
DI_EN_NOTCH(0x0);
DI_EN_TRIM(0x1);
DI_EN_TEST_BUF(0x0);
DI_CP_SEL(0x2);
DI_CP_OFFSET(0x0);
DI_LPF_SEL(0x3);
DI_VCO_GAIN(0x4);
DI_TRIM_VOL(0x4);
DI_EN_DIV2(0x0);
DI_EN_LDO(0x1);
DI_EN_LDO2(0x1);
48
47.99
1%
60M
60
59.99
1%
120M
120
119.99
1%
147M
147
147
0
160M
160
160
0
The clock of all peripheral devices of the chip is divided by the system clock frequency, and the sampling
rate can be known according to the clock tree and the baud rate register of each module.
2.2 Clock Register
Figure 3 Clock Register
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Bit
Name
Mode
Default
Description
31
Sdadc_bqclkx2_sel
WR
0x0
sdadc clk select
0：addc_clk
1: addc_clkdiv2
30
XSOC_x2en_a
WR
0x0
XSOC double enable
0：disable
1：enable
29:28
Sarclk_sel
WR
0x0
Saradc clk select
0x0：rc2m
0x1：XSOC_div4
27:26
—
—
—
—
25
Tmrck_async_sel
WR
0x0
Timer increase clk asynchronization select
0：选择系统时钟同步的 timer increase clk
1：选择 timer increase clk
24:23
Tmrck_sel
WR
0x0
Timer increase clk select
0x0: osc32k
0x1: clkout
0x2: XSOC_div
0x3: rc2m_d0
22
Pllts_oe
WRW
0x0
Pllts clk output enable
0：output disable
1：output enable
21:19
Pllts_sel
WR
0x0
Pllts clk select
0x0: pll0_tsck
0x1: pll1_tsck
0x2: bt_sx_tsck
0x3: 0x0
18:17
Hutclk_sel
WR
0x0
Hsuart clk select
Hutclk_sel[0]:0 select pll0_out/xosc ,1 select
pll1_out/xosc52m
Hutclk_sel[1]：0 select system clock (xosc/xosc_double)，1
select pll_div clk
16:13
Clkout_sel
WR
0x0
clock output select
0x1：xosc
0x2：XSOC_32k
0x3：osc32k
0x4：pll0div2_clk
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Bit
Name
Mode
Default
Description
0x5：xosc52m
0x6：pll1out
0x7：rc2m
0x8：rtc_rc2m
0x9：sys_clk
0xa：bt26m
0xb：bt_sx_tsck
0xc：dac_clk
12
Bt13m_sel
WR
0x0
Bt13m clk select
0：bt13m clk
1：PF0 input
11:10
Bt52m_sel
WR
0x0
Bt52m clk select：
0:xosc52m
1: invalid
9:8
-
-
-
-
7
Bt26m_sel
WR
0x0
Bt26m clock select：
0: select bt26m clk
1: invalid
6:4
Syspll_sel_a
WR
0x0
Sys pll select
Syspll_sel[0]:0 select pll_clk,1 select xosc52m
Syspll_sel[1]:0 select pll_clk/xosc52m
Syspll_sel[2]:0 select pll_clk/xosc52m,1 select xosc26m
3:2
Sysck_sel
WR
0x0
Sys clk clock select
00：rc2m clk
01：osc32k clk
10：pll_div clk
11：XSOC_div clk
0
Rcosc_en_sw
WR
0x1
RCOSC clock software enable
0：RCOSC enable invalid
1：RCOSC enable valid
Bit
Name
Mode
Default
Description
31
CVSD
WR
0x1
cvsd clk enable bit
0: disable
1: enable
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Bit
Name
Mode
Default
Description
30
AEC
WR
0x1
aec clk enable bit
0: disable
1: enable
29
SPF
WR
0x1
spf clk enable bit
0: disable
1: enable
28
SDADCM
WR
0x1
sdadcm clk enable bit
0: disable
1: enable
27
RECSRC
WR
0x1
recsrc clk enable bit
0: disable
1: enable
26
RTCC
WR
0x1
rtc clk enable bit
0: disable
1: enable
25
TMR2
WR
0x1
Timer2 clk enable bit
0: disable
1: enable
24
TMR1
WR
0x1
Timer1 clk enable bit
0: disable
1: enable
23
SDADCR
WR
0x1
saadcr clk enable bit
0: disable
1: enable
22
SDADCL
WR
0x1
Sdadcl clk enable bit
0: disable
1: enable
21
UART1
WR
0x1
Uart1 clk enable bit
0: disable
1: enable
20
BT
WR
0x1
bt clk enable bit
0: disable
1: enable
19
SPI0
WR
0x1
Spi0 clk enable bit
0: disable
1: enable
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Bit
Name
Mode
Default
Description
18
MBIST
WR
0x1
mbist clk enable bit
0: disable
1: enable
17
PORT
WR
0x1
port clk enable bit
0: disable
1: enable
16
AUDEC
WR
0x1
audec clk enable bit
0: disable
1: enable
15
SDADC
WR
0x1
sdadc clk enable bit
0: disable
1: enable
14
USB
WR
0x1
usb clk enable bit
0: disable
1: enable
13
SARADC
WR
0x1
saradc clk enable bit
0: disable
1: enable
12
DAC
WR
0x1
dac clk enable bit
0: disable
1: enable
11
HSUT0
WR
0x1
hsuart0 clk enable bit
0: disable
1: enable
10
UART0
WR
0x1
uart0 clk enable bit
0: disable
1: enable
9
SD0
WR
0x1
sd0 clk enable bit
0: disable
1: enable
8
TMR0
WR
0x1
timer0 clk enable bit
0: disable
1: enable
7
—
WR
0x1
6
RAM4
WR
0x1
Ram4 clk enable bit
0: disable
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Bit
Name
Mode
Default
Description
1: enable
5
RAM3
WR
0x1
Ram3 clk enable bit
0: disable
1: enable
4
RAM2
WR
0x1
Ram2 clk enable bit
0: disable
1: enable
3
RAM1
WR
0x1
Ram1 clk enable bit
0: disable
1: enable
2
RAM0
WR
0x1
Ram0 clk enable bit
0: disable
1: enable
1
ROM1
WR
0x1
Rom1 clk enable bit
0: disable
1: enable
0
ROM0
WR
0x1
Rom0 clk enable bit
0: disable
1: enable
Bit
Name
Mode
Default
Description
31
Dvp_pclk_inv_en
WR
0x0
Dvp clk Flip enable：
0x0:disable
0x1：enable
30:29
Dvp_delay_sel
WR
0x0
Dvp clk delay:
0:disable
1:enable
28:27
Dvp_outclk_sel
WR
0x0
Dvp clk select
0x0:syspll_div
0x1:XSOC
0x2:sys_clk
26:25
Splldiv_sel
WR
0x0
Sys pll div select：
Sysplldiv_sel[0]：0 select syspll_div/bt26m,1 select
XSOC_clk/bt26m negation
Sysplldiv_sel[1]:0 select syspll_div/XSOC，1 select
bt26m/bt26m negation
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Bit
Name
Mode
Default
Description
24
Ft_clkpin_sel
WR
0x0
FT clk select
0x0:PF5
0x1:PA7
23
Iicclk_sel
WR
0x0
Iic clk select
0x0: rc2m
0x1: XSOC_div8
22
Pll0sdmsel_a
WR
0x0
-
21
XSOC_lpm_gen
WR
0x0
XSOC_lpm enable bit
0x0: disable
0x1: enable
20
—
—
—
—
19
Aecram_div1_sel
WR
0x0
Aecram div1 select
0x0:disable
0x1:enable
18
Usb6p5_sel
WR
0x0
-
17
K32_tscsel
WR
0x0
Osc32k select
0x0:osc32k
0x1:cp_pin
16
XSOC_dlysel_a
WR
0x0
XSOC clk delay select
0：disable
1：enable
15
X52m_insel_a
WR
0x0
Xo52m pre select
0：xo52m_pre0
1：xo52m_pre1
14
Uartck_sel
WR
0x0
Uart inc clk select
0：XSOC_div
1：XSOC_div4
13:12
Ttck_sel
WR
0x0
Tick inc clk select
0x0: XSOC_div
0x1: pll0div16
0x2: pll0div32
0x3: pll0div64
11:10
Usbpll_sel
WR
0x0
-
9:8
Iisclk_sel
WR
0x0
Iis clk select
0x0：dac_clk
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Bit
Name
Mode
Default
Description
0x1:xosc52m
0x2:dac_clk/xosc52m(depend on iisclk_sel[0])
0x3:iis_div_clk
7:6
—
—
—
—
5:4
Irrxclksel
WR
0x0
Ir rx clk select
0x0:XSOC_32k
0x1:XSOC_div
0x2:osc32k
0x3:rc32k
3:2
—
—
—
—
1:0
Adda_clksel
WR
0x0
DAC clk select
0x3:adda_clk
0x2:XSOC
0x1:adpll_div_clk
0x0:0
Bit
Name
Mode
Default
Description
31
EFUSE
WR
0x1
efuse clk enable bit
0: disable
1: enable
30
M2MDMA
WR
0x1
M2m clk enable bit
0: disable
1: enable
29
XSOC
WR
0x0
XSOC clk enable bit
0: disable
1: enable
28
DBG
WR
0x1
dbg clk enable bit
0: disable
1: enable
27
PBF
WR
0x1
pbf clk enable bit
0: disable
1: enable
26
FRQEDET
WR
0x1
freqdet clk enable bit
0: disable
1: enable
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Bit
Name
Mode
Default
Description
25
ROM3
WR
0x1
Rom3 clk enable bit
0: disable
1: enable
24
ROM2
WR
0x1
Rom2 clk enable bit
0: disable
1: enable
23
AECRAM
WR
0x1
aecram clk enable bit
0: disable
1: enable
22:17
—
—
0x1
—
16
TICK0
WR
0x1
Tick0 clk enable bit
0: disable
1: enable
15
PIANO
WR
0x1
piano clk enable bit
0: disable
1: enable
14:13
—
—
0x1
—
12
SPI1
WR
0x1
Spi1 clk enable bit
0: disable
1: enable
11
UART2
WR
0x1
Uart2 clk enable bit
0: disable
1: enable
10
TMR5
WR
0x1
Timer5 clk enable bit
0: disable
1: enable
9
TMR4
WR
0x1
Timer4 clk enable bit
0: disable
1: enable
8
TMR3
WR
0x1
Timer3 clk enable bit
0: disable
1: enable
7
PLC
WR
0x1
plc clk enable bit
0: disable
1: enable
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Bit
Name
Mode
Default
Description
6
—
—
0x1
—
5
SBCEC
WR
0x1
sbcec clk enable bit
0: disable
1: enable
4
IIS
WR
0x1
iis clk enable bit
0: disable
1: enable
3
IRRX
WR
0x1
Irrx clk enable bit
0: disable
1: enable
2
SRC
WR
0x1
src clk enable bit
0: disable
1: enable
1:0
—
—
0x1
—
Bit
Name
Mode
Default
Description
31:24
XSOC_div
WR
0x0
External crystal oscillator clock for divide
23:22
Hut_div
WR
0x0
HSUART divide
21:17
Clkout_div
WR
0x0
CLKOUT divide
16:13
Audec_div
WR
0x0
AUDECPLL divide
12:8
Syspll_div
WR
0x0
SYSPLL divide
7:4
Adpll_div
WR
0x0
ADPLL divide
3:0
Btpll_div
WR
0x0
BTPLL divide
Bit
Name
Mode
Default
Description
31:22
—
—
0x1
—
21
HWMATH
WR
0x1
hwmath clk enable bit
0: disable
1: enable
20
RDFT
WR
0x1
rdft clk enable bit
0: disable
1: enable
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Bit
Name
Mode
Default
Description
19
RNN
WR
0x1
rnn clk enable bit
0: disable
1: enable
18
DRC_PCLK
WR
0x1
drc pclk enable bit
0: disable
1: enable
17
DACDIV2SEL
WR
0x0
Dacdiv2 clk enable bit
0: disable
1: enable
16
DAC_25
WR
0x0
Dac25 clk enable bit
0: disable
1: enable
15
DAC
WR
0x0
dac clk enable bit
0: disable
1: enable
14
ADDIV
WR
0x1
adddiv clk enable bit
0: disable
1: enable
13
SYSPLLDIV
WR
0x1
sysplldiv clk enable bit
0: disable
1: enable
12
PLLCLKDIV4
WR
0x1
Plldiv4 clk enable bit
0: disable
1: enable
11
PLLCLKDIV2
WR
0x1
Plldiv2 clk enable bit
0: disable
1: enable
10
BDP
WR
0x1
bsp clk enable bit
0: disable
1: enable
9:3
—
WR
0x1
Unused
2
DVP
WR
0x1
dvp clk enable bit
0: disable
1: enable
1
—
WR
0x1
Unused
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Bit
Name
Mode
Default
Description
0
IIC
WR
0x1
iic clk enable bit
0: disable
1: enable
Bit
Name
Mode
Default
Description
26:23
piano_div
WR
0x0
PIANO divide
26:23
cvsd_div
WR
0x0
CVSD divide
22:19
plc_div
WR
0x0
PLC divide
18:16
usb_div
WR
0x0
USB divide
15:12
sbcec_div
WR
0x0
SBCEC divide
11:8
iis_div
WR
0x0
IIS divide
7:4
src_div
WR
0x0
SRC divide
3:0
aec_div
WR
0x0
AEC divide
Bit
Name
Mode
Default
Description
26:23
Dvp_out_div
WR
0x0
DVP_OUT divide
22:20
hwmath_div
WR
0x0
HWMATH divide
19:16
dvp_div
WR
0x0
DVP divide
11:8
rnn_div
WR
0x0
RNN divide
6:0
Btlp_div
WR
0x0
BTLP divide
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3 Memory Access
Table 2 Memory Access
Number
Channel
SRAM0~2
SRAM3~4
Cache
RAM
AEC
RAM
AUDEC
RAM
SBCENC
RAM
RDFT
RAM
RNN
RAM
0
USB
BT_RFTS
RW
-
-
RW
-
-
-
-
1
BT
RW
RW
-
-
-
-
-
-
2
AUBUF
AUBUF1
ANCDAC
DACDMAO
RW
RW
RW
RW
RW
RW
-
-
3
SDADC
W
W
W
W
W
W
-
-
4
SD
SPI0
SPI1
IIS
RW
RW
RW
RW
RW
RW
RW
-
5
CVSD
EQ
PSRC
PLC
RW
RW
-
RW
RW
RW
-
-
6
RDFT
RW
RW
-
-
-
-
-
-
7
AUDEC
SBCENC
RW
RW
-
-
RW
-
-
-
8
GPDMA
BSP
RW
RW
-
RW
RW
RW
-
-
9
HSUT
DVP
SPF
RW
RW
-
-
-
-
-
-
10
-
-
-
-
-
-
-
-
-
11
-
-
-
-
-
-
-
-
-
12
-
-
-
-
-
-
-
-
-
13
-
-
-
-
-
-
-
-
-
14
-
-
-
-
-
-
-
-
-
15
-
-
-
-
-
-
-
-
-
DMA supported peripherals:HSUART, SPI, SD, USB and IIS,SDADC,SDDAC.
Note:
（1）RDFT refers to Fourier transform.
（2）GPDMA refers to general-purpose DMA, used to transmit data between peripherals and/or memory through a
linked list;
（3）BSP is Bit stream pickup;
（4）DVP, DVP interface, is one of standard protocols for cameras;
（5）SPF (abbreviation of SPDIF) is optical audio output;
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4 Low Power Mode
GW3323 supports two low-power modes：
4.1 1. sleep mode,500uA
Sleep mode will auto gate system clock, close memory access, close RC2M, but some asyn
clock should be disable by software.
Sleep mode wake up source as follow. After wakeup, software run continue or enter interruptif
enable.
BT wakeup
port external interrupt wakeup(PA7,PB1,PB2,PB3,PB4,PB5,INT_FALL,INT_RISE)
RTC 1s or alarm wakeup
4.1.1 Configuration of sleep mode
(1) Set sleep conditions
(2) Wait for sleep conditions to be met
(3) Save the status of the peripheral before entering sleep mode
(4) After the statuses of all IO ports are remembered, set all IO ports to input mode, adjust
the system clock to 24MHz, and disable PLL
(5) Configure wake-up conditions
(6) Enter sleep mode
(7) Wait to be awakened
(8) Recover the IO port status and restore the system clock
(9) Disable wake-up conditions
4.2 Power-off mode (power off, 4uA)
The wake-up source of power-off mode is shown below. The chip is reset after wake-up.
Wake-up through external interrupt level of ports (VUSB, PB0, PB1, PB2, PB5)
RTC 1s or alarm wake-up
Note:
（1）To enter low-power mode when SARADC mode is turned on, it needs to be manually turned off.
（2）There is no power supply in the chip in power-off mode, so resetting the circuit connected to the Reset pin is
invalid at this time.
（3）When the chip crashes in power-off mode, it needs to be powered off and restarted, or be designed as "Reset
can control and Vbat decreases" in hardware circuit, achieving the same effect as power-off restart.
4.2.1 Configuration of power-down mode
(1) Set the conditions for power-off mode
(2) Wait for the power-down mode conditions to be met
(3) Set the buck circuit module
(4) Turn off all IO port configurations
(5) Turn off the clock
(6) Configure wake-up conditions
(7) Enter the sleep mode
(8) Wait to be awakened
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