Geehy SEMICONDUCTOR GW3323 User manual

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User Manual
GW3323
RISC-V based 32-bit MCU with Bluetooth
Version: V0.2

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Contents
1 Block Diagram ................................................................................................................... 5
2 System Management ........................................................................................................ 6
2.1 System Clock ...............................................................................................................................................6
2.2 Clock Register ............................................................................................................................................. 7
3 Memory Access ...............................................................................................................19
4 Low Power Mode .............................................................................................................20
4.1 1. sleep mode,500uA ................................................................................................................................ 20
4.1.1 Configuration of sleep mode ............................................................................................................................20
4.2 Power-off mode (power off, 4uA) ..............................................................................................................20
4.2.1 Configuration of power-down mode .................................................................................................................20
5 Interrupts ......................................................................................................................... 22
5.1 Feature ...................................................................................................................................................... 22
5.2 interrupt vector table ................................................................................................................................. 22
5.3 Interrupts Special Registers ......................................................................................................................24
6 WatchDog ........................................................................................................................ 27
6.1 User Guide ................................................................................................................................................ 27
6.2 WDT Special Function Registers ..............................................................................................................27
7 GPIO Management .......................................................................................................... 29
7.1 Features .................................................................................................................................................... 29
7.2 GPIO internal block diagram .....................................................................................................................29
7.3 GPIO general control register ................................................................................................................... 29
7.4 GPIO function mapping .............................................................................................................................32
7.5 External Port interrupt wake up ................................................................................................................ 34
8 DMA ..................................................................................................................................37
8.1 Feature ...................................................................................................................................................... 37
8.2 Functional configuration ............................................................................................................................37
9 Timer ................................................................................................................................ 38
9.1 Features .................................................................................................................................................... 38
9.2 Timer clock select ......................................................................................................................................39
9.3 Timer0/1/2 Special Function Registers .....................................................................................................39
9.4 Timer3/4/5 Special Function Registers .....................................................................................................40
10 RTC ...................................................................................................................................43

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10.1 Features .................................................................................................................................................... 43
10.2 Special Function Registers ....................................................................................................................... 43
10.3 Independent Power RTC Registers ..........................................................................................................44
11 UART ................................................................................................................................ 50
11.1 Features .................................................................................................................................................... 50
11.2 User Guide ................................................................................................................................................ 50
11.2.1 UART Special Function Registers ................................................................................................................... 50
12 HSUART ........................................................................................................................... 53
12.1 Features .................................................................................................................................................... 53
12.2 User Guide ................................................................................................................................................ 53
12.2.1 SYNC configure ............................................................................................................................................... 53
12.2.2 TX 1 byte with buffer ........................................................................................................................................ 53
12.2.3 TX n byte with DMA ......................................................................................................................................... 54
12.2.4 RX 1 byte with buffer ....................................................................................................................................... 54
12.2.5 RX n byte with DMA &loop buffer disable ........................................................................................................54
12.2.6 DMA RX TIMER MODE: .................................................................................................................................. 55
12.2.7 Application Note ...............................................................................................................................................55
12.3 HSUART Special Function Registers ....................................................................................................... 58
13 SPI .................................................................................................................................... 62
13.1 Features .................................................................................................................................................... 62
13.2 User Guide ................................................................................................................................................ 62
13.3 SPI Special Function Registers ................................................................................................................ 64
14 IIC ..................................................................................................................................... 66
14.1 Features .................................................................................................................................................... 66
14.2 User Guide ................................................................................................................................................ 66
14.3 IIC Special Function Registers ..................................................................................................................67
15 ADC .................................................................................................................................. 69
15.1 Features .................................................................................................................................................... 69
15.2 Channel select ...........................................................................................................................................69
15.3 User Guide ................................................................................................................................................ 69
15.4 ADC_CTL Special Function Registers ......................................................................................................70
16 DAC .................................................................................................................................. 75
16.1 Feature ...................................................................................................................................................... 75
16.2 Control use ................................................................................................................................................ 75
17 USB .................................................................................................................................. 76

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17.1 Feature ...................................................................................................................................................... 76
17.2 Control use ................................................................................................................................................ 76
18 Power Management ........................................................................................................ 77
18.1 Charging process ...................................................................................................................................... 77
18.2 Charging settings ...................................................................................................................................... 77
18.3 Charging control function .......................................................................................................................... 77
19 Bluetooth ......................................................................................................................... 78
19.1 Feature ...................................................................................................................................................... 78
19.2 SPP protocol ..............................................................................................................................................78
19.2.1 SPP protocol is based on credit flow control mechanism ................................................................................78
19.2.2 SPP use and development in SDK ..................................................................................................................79
19.3 BLE protocol ..............................................................................................................................................80
19.3.1 Flow control mechanism of BLE protocol ........................................................................................................ 81
19.3.2 Use and Development of BLE in SDK ............................................................................................................. 81
19.4 FOTA upgrade ........................................................................................................................................... 82
19.4.1 Use and development of FOTA in feature SDK ...............................................................................................82
20 Revision history .............................................................................................................. 83

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1 Block Diagram
Figure 1 GW3323 System Block Diagram
Note: Chx indicates the channel number x

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2 System Management
2.1 System Clock
Figure 2 System Clock Tree
For details, see GW3323_clock.pdf.
The maximum frequency of this chip is 160MHz, which can be set by set_sys_clk().

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Table 1 PLL clock error
PLL
clock(Hz)
Value set by PLLCON0
Theoretical
output clock
Actual output
clock
Error%
2M
configure set_sys_clk()
2M
2M
0
24M
configure set_sys_clk()
24M
24M
0
48M
DI_LDO_SEL(0x2);
DI_LDO2_SEL(0x3);
DI_EN_XRES(0x0);
DI_EN_NOTCH(0x0);
DI_EN_TRIM(0x1);
DI_EN_TEST_BUF(0x0);
DI_CP_SEL(0x2);
DI_CP_OFFSET(0x0);
DI_LPF_SEL(0x3);
DI_VCO_GAIN(0x4);
DI_TRIM_VOL(0x4);
DI_EN_DIV2(0x0);
DI_EN_LDO(0x1);
DI_EN_LDO2(0x1);
48
47.99
1%
60M
60
59.99
1%
120M
120
119.99
1%
147M
147
147
0
160M
160
160
0
The clock of all peripheral devices of the chip is divided by the system clock frequency, and the sampling
rate can be known according to the clock tree and the baud rate register of each module.
2.2 Clock Register
Figure 3 Clock Register

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Bit
Name
Mode
Default
Description
31
Sdadc_bqclkx2_sel
WR
0x0
sdadc clk select
0：addc_clk
1: addc_clkdiv2
30
XSOC_x2en_a
WR
0x0
XSOC double enable
0：disable
1：enable
29:28
Sarclk_sel
WR
0x0
Saradc clk select
0x0：rc2m
0x1：XSOC_div4
27:26
—
—
—
—
25
Tmrck_async_sel
WR
0x0
Timer increase clk asynchronization select
0：选择系统时钟同步的 timer increase clk
1：选择 timer increase clk
24:23
Tmrck_sel
WR
0x0
Timer increase clk select
0x0: osc32k
0x1: clkout
0x2: XSOC_div
0x3: rc2m_d0
22
Pllts_oe
WRW
0x0
Pllts clk output enable
0：output disable
1：output enable
21:19
Pllts_sel
WR
0x0
Pllts clk select
0x0: pll0_tsck
0x1: pll1_tsck
0x2: bt_sx_tsck
0x3: 0x0
18:17
Hutclk_sel
WR
0x0
Hsuart clk select
Hutclk_sel[0]:0 select pll0_out/xosc ,1 select
pll1_out/xosc52m
Hutclk_sel[1]：0 select system clock (xosc/xosc_double)，1
select pll_div clk
16:13
Clkout_sel
WR
0x0
clock output select
0x1：xosc
0x2：XSOC_32k
0x3：osc32k
0x4：pll0div2_clk

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Bit
Name
Mode
Default
Description
0x5：xosc52m
0x6：pll1out
0x7：rc2m
0x8：rtc_rc2m
0x9：sys_clk
0xa：bt26m
0xb：bt_sx_tsck
0xc：dac_clk
12
Bt13m_sel
WR
0x0
Bt13m clk select
0：bt13m clk
1：PF0 input
11:10
Bt52m_sel
WR
0x0
Bt52m clk select：
0:xosc52m
1: invalid
9:8
-
-
-
-
7
Bt26m_sel
WR
0x0
Bt26m clock select：
0: select bt26m clk
1: invalid
6:4
Syspll_sel_a
WR
0x0
Sys pll select
Syspll_sel[0]:0 select pll_clk,1 select xosc52m
Syspll_sel[1]:0 select pll_clk/xosc52m
Syspll_sel[2]:0 select pll_clk/xosc52m,1 select xosc26m
3:2
Sysck_sel
WR
0x0
Sys clk clock select
00：rc2m clk
01：osc32k clk
10：pll_div clk
11：XSOC_div clk
0
Rcosc_en_sw
WR
0x1
RCOSC clock software enable
0：RCOSC enable invalid
1：RCOSC enable valid
Bit
Name
Mode
Default
Description
31
CVSD
WR
0x1
cvsd clk enable bit
0: disable
1: enable

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Bit
Name
Mode
Default
Description
30
AEC
WR
0x1
aec clk enable bit
0: disable
1: enable
29
SPF
WR
0x1
spf clk enable bit
0: disable
1: enable
28
SDADCM
WR
0x1
sdadcm clk enable bit
0: disable
1: enable
27
RECSRC
WR
0x1
recsrc clk enable bit
0: disable
1: enable
26
RTCC
WR
0x1
rtc clk enable bit
0: disable
1: enable
25
TMR2
WR
0x1
Timer2 clk enable bit
0: disable
1: enable
24
TMR1
WR
0x1
Timer1 clk enable bit
0: disable
1: enable
23
SDADCR
WR
0x1
saadcr clk enable bit
0: disable
1: enable
22
SDADCL
WR
0x1
Sdadcl clk enable bit
0: disable
1: enable
21
UART1
WR
0x1
Uart1 clk enable bit
0: disable
1: enable
20
BT
WR
0x1
bt clk enable bit
0: disable
1: enable
19
SPI0
WR
0x1
Spi0 clk enable bit
0: disable
1: enable