Atmel 8051 User manual

Atmel 8051 Microcontrollers
Hardware Manual

Atmel 8051 Microcontrollers Hardware Manual 1
4316B–8051–02/04
Table of Contents
Section 1
The 8051 Instruction Set.......................................................................1-2
1.1 Program Status Word................................................................................1-2
1.2 Addressing Modes ....................................................................................1-3
1.3 Arithmetic Instructions...............................................................................1-5
1.4 Logical Instructions ...................................................................................1-6
1.5 Data Transfers .........................................................................................1-7
1.6 External RAM.........................................................................................1-10
1.7 Lookup Tables .......................................................................................1-10
1.8 Boolean Instructions ...............................................................................1-11
1.9 Jump Instructions....................................................................................1-13
1.10 Read-Modify-Write Instruction Features .................................................1-15
1.11 Instruction Set Summary.........................................................................1-16
1.12 Instructions That Affect Flag Settings .....................................................1-20
1.13 Instruction Table .....................................................................................1-21
1.14 Instruction Definitions..............................................................................1-24
Section 2
Common Features Description...........................................................2-64
2.1 Introduction ............................................................................................2-64
2.2 Special Function Registers .....................................................................2-65
2.3 Oscillator and Clock Circuit.....................................................................2-68
2.4 CPU Timing.............................................................................................2-69
2.5 Port Structures and Operation ................................................................2-71
2.6 Accessing External Memory....................................................................2-75
2.7 PSEN ......................................................................................................2-76
2.8 ALE .........................................................................................................2-76
2.9 Timer/Counters .......................................................................................2-78
2.10 Timer 0....................................................................................................2-78
2.11 Timer 1....................................................................................................2-81
2.12 Timer 2....................................................................................................2-86
2.13 Serial Interface........................................................................................2-91
2.14 Framing Error Detection........................................................................2-101
2.15 Automatic Address Recognition............................................................2-102
2.16 Interrupts...............................................................................................2-109

Atmel 8051 Microcontrollers Hardware Manual 1-2
Rev. 4316B–8051–02/04
Section 1
The 8051 Instruction Set
The 8051 instruction set is optimized for 8-bit control applications. It provides a variety of
fast addressing modes for accessing the internal RAM to facilitate byte operations on
small data structures. The instruction set provides extensive support for one-bit vari-
ables as a separate data type, allowing direct bit manipulation in control and logic
systems that require Boolean processing.
An overview of the 8051 instruction set is presented below, with a brief description of
how certain instructions might be used.
1.1 Program Status
Word The Program Status Word (PSW) contains several status bits that reflect the current
state of the CPU. The PSW, shown in Table 1-1 on page 3, resides in SFR space. It
contains the Carry bit, the Auxiliary Carry (for BCD operations), the two register bank
select bits, the Overflow flag, a parity bit, and two user-definable status flags.
The Carry bit, other than serving the functions of a Carry bit in arithmetic operations,
also serves as the “Accumulator” for a number of Boolean operations.
The bits RS0 and RS1 are used to select one of the four register banks shown below.
A number of instructions refer to these RAM locations as R0 through R7. The selection
of which of the four banks is being referred to is made on the basis of the bits RS0 and
RS1 at execution time.
The parity bit reflects the number of 1’s in the Accumulator: P = 1 if the Accumulator
contains an odd number of 1’s, and P = 0 if the Accumulator contains an even number of
1’s. Thus the number of 1’s in the Accumulator plus P is always even.
Two bits in the PSW are uncommitted and may be used as general purpose status flags.
The PSW register contains program status information as detailed in Table 1-1.

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Table 1-1. PSW: Program Status Word Register
1.2 Addressing
Modes The addressing modes in the 8051 instruction set are as follows:
1.2.1 Direct Addressing
In direct addressing the operand is specified by an 8-bit address field in the instruction.
Only 128 Lowest bytes of internal Data RAM and SFRs can be directly addressed.
1.2.2 Indirect Addressing
In indirect addressing the instruction specifies a register which contains the address of
the operand. Both internal and external RAM can be indirectly addressed.
The address register for 8-bit addresses can be R0 or R1 of the selected register bank,
or the Stack Pointer. The address register for 16-bit addresses can only be the 16-bit
“data pointer” register, DPTR.
1.2.3 Register Instructions
(MSB) (LSB)
CY AC F0 RS1 RS0 OV - P
Symbol Position Name and Significance
CY PSW.7 Carry flag
AC PSW.6 Auxiliary Carry flag.
(For BCD operations.)
F0 PSW.5 Flag 0
(Available to the user for general purposes.)
RS1 PSW.4
Register bank Select control bits 1 & 0. Set/cleared
by software to determine working register bank (see
Note).
RS0 PSW.3
OV PSW.2 Overflow flag.
- PSW.1 (reserved)
PPSW.0
Parity flag.
Set/cleared by hardware each instruction cycle to
indicate and odd/even number of “one” bits in the
accumulator, i.e., even parity.
Note:
The contents of (RS1, RS0) enable the working register banks as follows:
(0.0)-Bank 0(00H-07H)
(0.1)-Bank 1(08H-0FH)
(1.0)-Bank 2(10H-17H)
(1.1)-Bank 3(18H-1FH)

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The register banks, containing registers R0 through R7, can be accessed by certain
instructions which carry a 3-bit register specification within the opcode of the instruction.
Instructions that access the registers this way are code efficient, since this mode elimi-
nates an address byte. When the instruction is executed, one of the eight registers in the
selected bank is accessed. One of four banks is selected at execution time by the two
bank select bits in the PSW.
1.2.4 Register-specific Instructions
Some instructions are specific to a certain register. For example, some instructions
always operate on the Accumulator, or Data Pointer, etc., so no address byte is needed
to point to it. The opcode does this itself. Instructions that refer to the Accumulator as ‘A’
assemble as accumulator-specific opcodes.
1.2.5 Immediate Constants
The value of a constant can follow the opcode in Program Memory. For example;
MOV A, # 100
loads the Accumulator with the decimal number 100. The same number could be speci-
fied in hex digits as 64H.
1.2.6 Indexed Addressing
Only Program Memory can be accessed with indexed addressing, and it can only be
read. This addressing mode is intended for reading look-up tables in Program Memory.
A 16-bit base register (either DPTR or the Program Counter) points to the base of the
table, and the Accumulator is set up with the table entry number. The address of the
table entry in Program Memory is formed by adding the Accumulator data to the base
pointer.
Another type of indexed addressing is used in the “case jump” instruction. In this case
the destination address of a jump instruction is computed as the sum of the base pointer
and the Accumulator data.

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1.3 Arithmetic
Instructions The menu of arithmetic instructions is listed in Table 1-2. The table indicates the
addressing modes that can be used with each instruction to access the <byte> operand.
For example, the ADD A, <byte> instruction can be written as:
ADD A,7FH (direct addressing)
ADD A,@ R0(indirect addressing)
ADD A,R7 (register addressing)
ADD A,# 127(immediate constant)
The execution times listed in Table 1-2 assume a 12 MHz clock frequency and X1
mode. All of the arithmetic instructions execute in 1 µs except the INC DPTR instruction,
which takes 2 µs, and the Multiply and Divide instructions, which take 4 µs.
Note that any byte in the internal Data Memory space can be incremented or decre-
mented without going through the Accumulator.
One of the INC instructions operates on the 16-bit Data Pointer. The Data Pointer is
used to generate 16-bit addresses for external memory, so being able to increment it in
one 16-bit operation is a useful feature.
The MUL AB instruction multiplies the Accumulator by the data in the B register and puts
the 16-bit product into the concatenated B and Accumulator registers.
The DIV AB instruction divides the Accumulator by the data in the B register and leaves
the 8-bit quotient in the Accumulator, and the 8-bit remainder in the B register.
Oddly enough, DIV AB finds less use in arithmetic “divide” routines than in radix conver-
sions and programmable shift operations. An example of the use of DIV AB in a radix
conversion will be given later. In shift operations, dividing a number by 2nshifts its n bits
to the right. Using DIV AB to perform the division completes the shift in 4 µs leaves the B
register holding the bits that were shifted out.
Table 1-2. A list of the Atmel 8051 Arithmetic Instructions.
Mnemonic Operation Addressing Modes
Execution Time in X1
Mode
@12 MHz (µs)
Dir Ind Reg Im m
ADD A, <byt>e A = A + <byte> X X X X
ADDC A,
<byte> A = A + <byte> + C X X X X 1
SUBB A,
<byte> A = A – <byte> – C X X X X 1
INC A A = A + 1 Accumulator only 1
INC <byte> <byte> = <byte> + 1 X X X 1
INC DPTR DPTR = DPTR + 1 Data Pointer only 2
DEC A A = A – 1 Accumulator only 1
DEC <byte> <byte> = <byte> – 1 X X X 1
MUL AB B:A = B ×A ACC and B only 4
DIV AB A = Int [A/B]
B = Mod [A/B] ACC and B only 4
DA A Decimal Adjust Accumulator only 1

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The DA A instruction is for BCD arithmetic operations. In BCD arithmetic ADD and
ADDC instructions should always be followed by a DA A operation, to ensure that the
result is also in BCD. Note that DAA will not convert a binary number to BCD. The DA A
operation produces a meaningful result only as the second step in the addition of two
BCD bytes.
1.4 Logical
Instructions Table 1-3 shows the list of logical instructions. The instructions that perform Boolean
operations (AND, OR, Exclusive OR, NOT) on bytes perform the operation on a bit-by-
bit basis. That is, if the Accumulator contains 00110101B and <byte> contains
01010011B, then
ANL A,<byte>
will leave the Accumulator holding 00010001B.
The addressing modes that can be used to access the <byte> operand are listed in
Table 1-3. Thus, the ANL A, <byte> instruction may take any of the following forms.
ANL A, 7FH(direct addressing)
ANL A, @ R1(indirect addressing)
ANL A, R6(register addressing)
ANL A, # 53H(immediate constant)
All of the logical instructions that are Accumulator specific execute in 1 µs (using a
12 MHz clock and X1 mode). The others take 2 µs.
Table 1-3. A list of the Atmel 8051 Logical Instructions
Mnemonic Operation Addressing Modes Execution Time @ 12MHz (µs)
Dir Ind Reg Imm
ANL A, <byte> A = A AND <byte> X X X X 1
ANL <byte>, A <byte> = <byte> AND A X 1
ANL <byte>, #
data <byte> = <byte> AND # data X 2
ORL A, <byte> A = A OR <byte> X X X X 1
ORL <byte>, A <byte> = <byte> OR A X 1
ORL <byte>, #
data <byte> = <byte> OR # data X 2
XRL A, <byte> A = A XOR <byte> X X X X 1
XRL <byte>, A <byte> = <byte> XOR A X 1
XRL <byte>, #
data <byte> = <byte> XOR # data X 2
CLR A A = 00H Accumulator only 1
CLP A A = NOT A Accumulator only 1
RL A Rotate ACC Left 1 bit Accumulator only 1
RLC A Rotate Left through Carry Accumulator only 1
RR A Rotate ACC Right 1 bit Accumulator only 1
RRC A Rotate Right through Carry Accumulator only 1
SWAP A Swap Nibbles in A Accumulator only 1

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Note that Boolean operations can be performed on any byte in the internal Data Memory
space without going through the Accumulator. The XRL <byte>, # data instruction, for
example, offers a quick and easy way to invert port bits, as in
XRL P1, #OFFH
If the operation is in response to an interrupt, not using the Accumulator saves the time
and effort to stack it in the service routine.
The Rotate instructions (RL A, RLC A, etc.) shift the Accumulator 1 bit to the left or right.
For a left rotation, the MSB rolls into the LSB position. For a right rotation, the LSB rolls
into the MSB position.
The SWAP A instruction interchanges the high and low nibbles within the Accumulator.
this is a useful operation in BCD manipulations. For example, if the Accumulator con-
tains a binary number which is known to be less than 100, it can be quickly converted to
BCD by the following code:
MOV B, #10
DIV AB
SWAP A
ADD A,B
Dividing the number by 10 leaves the tens digit in the low nibble of the Accumulator, and
the ones digit in the B register. The SWAP and ADD instructions move the tens digit to
the high nibble of the Accumulator, and the ones digit to the low nibble.
1.5 Data Transfers
1.5.1 Internal RAM
Table 1-4 shows the menu of instructions that are available for moving data around
within the internal memory spaces, and the addressing modes that can be used with
each one. With a 12 MHz clock and X1 mode, all of these instructions execute in either
1 or 2 µs.
The MOV <dest>, <src> instruction allows data to be transferred between any two inter-
nal RAM or SFR locations without going through the Accumulator. Remember the Upper
128 bytes of data RAM can be accessed only by indirect, and SFR space only by direct
addressing.
Note that in all 8051 devices, the stack resides in on-chip RAM, and grows upwards.
The PUSH instruction first increments the Stack Pointer (SP), then copies the byte into
the stack. PUSH and POP use only direct addressing to identify the byte being saved or
restored, but the stack itself is accessed by indirect addressing using the SP register.

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This means the stack can go into the Upper 128, if they are implemented, but not into
SFR space.
The Upper 128 are not implemented in the 8 standard 8051, nor in their ROMless. With
these devices, if the SP points to the Upper 128 PUSHed bytes are lost, and POPped
bytes are indeterminate.
The Data Transfer instructions include a 16-bit MOV that can be used to initialize the
Data Pointer (DPTR) for look-up tables in Program Memory, or for 16-bit external Data
Memory accesses.
The XCH A, <byte> instruction causes the Accumulator and addressed byte to
exchange data.
The XCHD A, @ Ri instruction is similar, but only the low nibbles are involved in the
exchange.
The see how XCH and XCHD can be used to facilitate data manipulations, consider first
the problem of shifting an 8-digit BCD number two digits to the right. Table 1-5 shows
how this can be done using direct MOVs, and for comparison how it can be done using
XCH instructions. To aid in understanding how the code works, the contents of the reg-
isters that are holding the BCD number and the content of the Accumulator are shown
alongside each instruction to indicate their status after the instruction has been
executed.
After the routine has been executed, the Accumulator contains the two digits that were
shifted out on the right. Performing the routine with direct MOVs uses 14 code bytes and
9 µs of execution time (assuming a 12 MHz clock and X1 mode). The same operation
with XCHs uses less code and executes almost twice as fast.
Table 1-4. Atmel 8051 Data Transfer Instructions that Access Internal Data Memory
Space
Mnemonic Operation Addressing Modes Execution Time
@ 12MHz (µs)
Dir Ind Reg Imm
MOV A, <src> A = <src> X X X X 1
MOV <dest>, A <dest> = A X X X 1
MOV <dest>,
<src> <dest> = <src> X X X X 2
MOV DPTR, #
data 16 DPTR = 16-bit immediate constant X2
PUSH <src> INC SP: MOV “@SP”, <scr> X 2
POP <dest> MOV <dest>, “@SP”: DEC SP X 2
XCH A, <byte> ACC and <byte> Exchange Data X X X 1
XCHD A, @Ri ACC and @ Ri exchange low
nibbles X1

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To right-shift by an odd number of digits, a one-digit shift must be executed. Table 1-6
shows a sample of code that will right-shift a BCD number one digit, using the XCHD
instruction. Again, the contents of the registers holding the number and of the Accumu-
lator are shown alongside each instruction.
First, pointers R1 and R0 are set up to point to the two bytes containing the last four
BCD digits. Then a loop is executed which leaves the last byte, location 2EH, holding
the last two digits of the shifted number. The pointers are decremented, and the loop is
Table 1-5. Shifting a BCD Number Two Digits to the Right
2A 2B 2C 2D 2E ACC
MOV A,2EH
MOV 2EH, 2DH
MOV 2DH, 2CH
MOV 2CH, 2BH
MOV 2BH, # 0
00
00
00
00
00
12
12
12
12
00
34
34
34
12
12
56
56
34
34
34
78
56
56
56
56
78
78
78
78
78
Note: Using direct MOVs: 14 bytes, 9 µs
2A 2B 2C 2E 2E ACC
CLR A
XCH A,2BH
XCH A,2CH
XCH A,2DH
XCH A,2EH
00
00
00
00
00
12
00
00
00
00
34
34
12
12
12
56
56
56
34
34
78
78
78
78
56
00
12
34
56
78
Note: Using XCHs: 9 bytes, 5 µs
Table 1-6. Shifting a BCD Number One Digit to the Right
2A 2B 2C 2D 2E ACC
MOVR1,#2EH 0012345678XX
MOVR0,#2DH 0012345678XX
loop for R1 = 2EH:
LOOP:MOVA,@R1 001234567878
XCHD A, @R0 00 12 34 58 78 76
SWAPA 001234587867
MOV@R1,A 001234586767
DEC R1 00 12 34 58 67 67
DEC R0 00 12 34 58 67 67
CJNE R1, #2AH, LOOP
loop for R1 = 2DH: 00 12 38 45 67 45
loop for R1 = 2CH: 00 18 23 45 67 23
loop for R1 = 2BH: 08 01 23 45 67 01
CLRA 080123456700
XCHA,2AH 000123456708