Geehy SEMICONDUCTOR APM32F405/415 G Series User manual

www.geehy.com Page 0
User Manual
APM32F405/415xG
APM32F407/417xExG
Arm® Cortex®-M4 based 32-bit MCU
Version: V1.4

www.geehy.com Page 1
Contents
Introduction and document description rules....................................8
Introduction................................................................................................................8
Document description rules ......................................................................................8
System architecture ...........................................................................12
Full name and abbreviation description of terms....................................................12
System architecture block diagram.........................................................................12
Memory mapping ....................................................................................................15
Startup configuration...............................................................................................15
FLASH memory...................................................................................17
Full name and abbreviation description of terms....................................................17
Introduction..............................................................................................................17
Main characteristics ................................................................................................17
Flash memory structure ..........................................................................................18
Flash memroy functional description ......................................................................18
Register address mapping......................................................................................25
Register functional description................................................................................25
External Memory Controller (EMMC) ................................................30
Full name and abbreviation description of terms....................................................30
EMMC Overview .....................................................................................................30
SMC Introduction ....................................................................................................30
SMC Structure Block Diagram................................................................................31
SMC Functional Description ...................................................................................31
SMC register address mapping ..............................................................................37
SMC register functional description........................................................................38
DMC introduction ....................................................................................................47
Main characteristics of DMC...................................................................................47
DMC structure block diagram .................................................................................48
DMC functional description .....................................................................................48
DMC register address mapping..............................................................................50
DMC register functional description........................................................................50
System configuration controller (SYSCFG)......................................55
Main characteristics ................................................................................................55
I/O compensation cell..............................................................................................55
Register address mapping......................................................................................55
Register functional description................................................................................55

www.geehy.com Page 2
Reset and clock (RCM).......................................................................60
Full name and abbreviation description of terms....................................................60
Reset management unit (RMU) ..............................................................................60
Clock management unit (CMU)...............................................................................63
Register address mapping......................................................................................70
Register functional description................................................................................71
Power management unit (PMU) .......................................................101
Full name and abbreviation description of terms..................................................101
Introduction............................................................................................................101
Structure block diagram........................................................................................102
Functional description ...........................................................................................102
Register address mapping....................................................................................109
Register functional description..............................................................................109
Nested vector interrupt controller (NVIC).......................................112
Full name and abbreviation description of terms..................................................112
Introduction............................................................................................................112
Main characteristics ..............................................................................................112
Interrupt and exception vector table .....................................................................112
External Interrupt/Event Controller (EINT) .....................................120
Introduction............................................................................................................120
Main Characteristics..............................................................................................120
Functional description ...........................................................................................120
Register address mapping....................................................................................123
Register functional description..............................................................................123
Direct memory access (DMA) ..........................................................126
Introduction............................................................................................................126
Main characteristics ..............................................................................................126
Functional description ...........................................................................................126
DMA register address mapping.............................................................................133
Register functional description..............................................................................133
Debug MCU (DBGMCU)....................................................................142
Full name and abbreviation description of terms..................................................142
Introduction............................................................................................................142
Main characteristics ..............................................................................................142
Functional description ...........................................................................................143
Register address mapping....................................................................................144
Register functional description..............................................................................144

www.geehy.com Page 3
General-Purpose Input/Output Pin (GPIO) .....................................149
Full name and abbreviation description of terms..................................................149
Main characteristics ..............................................................................................149
Structure block diagram........................................................................................150
Functional description ...........................................................................................150
Register address mapping....................................................................................154
Register functional description..............................................................................154
Timer overview..................................................................................159
Full name and abbreviation description of terms..................................................159
Timer category and main difference .....................................................................159
Advanced Timers (TMR1/8)..............................................................162
Introduction............................................................................................................162
Main characteristics ..............................................................................................162
Structure block diagram........................................................................................163
Functional description ...........................................................................................163
Register address mapping....................................................................................180
Register functional description..............................................................................181
General-purpose timer (TMR2/3/4/5) ...............................................200
Introduction............................................................................................................200
Main characteristics ..............................................................................................200
Structure block diagram........................................................................................201
Functional description ...........................................................................................201
Register address mapping....................................................................................214
Register functional description..............................................................................214
General-purpose timer (TMR9/10/11/12/13/14)................................231
Introduction............................................................................................................231
Main characteristics of TMR9/12 ..........................................................................231
Main characteristics of TMR10/11/13/14 ..............................................................231
TMR9/12 structure block diagram.........................................................................232
TMR10/11/13/14 structure block diagram.............................................................233
Functional description ...........................................................................................233
TMR9/12 register address mapping .....................................................................240
TMR9/12 register functional description ...............................................................241
TMR10/11/13/14 register address mapping..........................................................250
TMR10/11/13/14 register functional description ...................................................251
Basic timer (TMR6/7) ........................................................................258
Introduction............................................................................................................258

www.geehy.com Page 4
Main characteristics ..............................................................................................258
Structure block diagram........................................................................................258
Functional description ...........................................................................................258
Register address mapping....................................................................................260
Register functional description..............................................................................261
Watchdog timer (WDT) .....................................................................265
Introduction............................................................................................................265
Independent watchdog timer (IWDT)....................................................................265
Window watchdog timer (WWDT).........................................................................267
IWDT register address mappin .............................................................................268
IWDT register functional description.....................................................................269
WWDT register address mappin...........................................................................270
WWDT register functional description ..................................................................270
Real-time clock (RTC).......................................................................272
Full name and abbreviation description of terms..................................................272
Introduction............................................................................................................272
Main characteristics ..............................................................................................272
Structure block diagram........................................................................................272
Functional description ...........................................................................................273
Register address mapping....................................................................................279
Register functional description..............................................................................280
HASH processor (HASH)..................................................................296
Introduction............................................................................................................296
Main characteristics ..............................................................................................296
Functional description ...........................................................................................296
Register address mapping....................................................................................297
Register functional description..............................................................................297
Digital camera interface (DCI)..........................................................302
Full name and abbreviation description of terms..................................................302
Introduction............................................................................................................302
Main characteristics ..............................................................................................302
Structure block diagram........................................................................................303
Functional description ...........................................................................................303
Register address mapping....................................................................................307
Register functional description..............................................................................308
Universal synchronous/asynchronous transceiver (USART) .......314
Full name and abbreviation description of terms..................................................314

www.geehy.com Page 5
Introduction............................................................................................................314
Main characteristics ..............................................................................................314
Functional description ...........................................................................................316
Register address mapping....................................................................................330
Register functional description..............................................................................330
Internal integrated circuit interface (I2C)........................................338
Full name and abbreviation description of terms..................................................338
Introduction............................................................................................................338
Main characteristics ..............................................................................................338
Structure block diagram........................................................................................340
Functional description ...........................................................................................340
Register address mapping....................................................................................347
Register functional description..............................................................................347
Serial peripheral interface/On-chip audio interface (SPI/I2S) .......357
Full name and abbreviation description of terms..................................................357
Introduction............................................................................................................357
Main characteristics ..............................................................................................358
SPI functional description .....................................................................................359
I2S functional description......................................................................................370
Register address mapping....................................................................................382
Register functional description..............................................................................383
Controller area network (CAN) ........................................................390
Full name and abbreviation description of terms..................................................390
Introduction............................................................................................................390
Main characteristics ..............................................................................................390
Functional description ...........................................................................................390
Register address mapping....................................................................................399
Register functional description..............................................................................400
Secure digital input/output interface (SDIO) ..................................418
Full name and abbreviation description of terms..................................................418
Introduction............................................................................................................418
Main characteristics ..............................................................................................418
Functional description ...........................................................................................418
Register address mapping....................................................................................441
Register functional description..............................................................................441
USB_OTG ..........................................................................................453
Introduction............................................................................................................453

www.geehy.com Page 6
OTG_FS global register address mapping...........................................................453
OTG_FS global register functional description.....................................................454
OTG_FS host mode register address mapping....................................................468
OTG_FS host mode register functional description..............................................469
OTG_FS device mode register address mapping ................................................475
OTG_FS device mode register functional description..........................................476
Full-speed OTG power and clock gating control register (OTG_FS_PCGCTRL) 491
OTG_HS1 global register address mapping.........................................................492
OTG_HS1 global register functional description ..................................................493
OTG_HS1 host mode register address mapping .................................................510
OTG_HS1 host mode register functional description ...........................................510
OTG_HS1 device mode register address mapping..............................................518
OTG_HS1 device mode register functional description .......................................519
High-speed OTG power and clock gating control register
(OTG_HS1_PCGCTRL) ..................................................................................................537
OTG_HS2 register address mapping ...................................................................538
OTG_HS2 global register functional description ..................................................538
Ethernet .............................................................................................540
Introduction............................................................................................................540
Main characteristics of Ethernet............................................................................540
Functional description ...........................................................................................543
MAC register address mapping ............................................................................572
MAC register functional description......................................................................573
MMC register address mapping............................................................................589
MMC register functional description .....................................................................589
PTP register address mapping .............................................................................593
PTP register functional description.......................................................................593
DMA register address mapping.............................................................................598
DMA register functional description ......................................................................598
Analog-to-digital converter (ADC)...................................................610
Full name and abbreviation description of terms..................................................610
Introduction............................................................................................................611
Main characteristics ..............................................................................................611
Functional description ...........................................................................................612
Register address mapping....................................................................................623
Register functional description..............................................................................624
Digital-to-analog converter (DAC) ...................................................635
Full name and abbreviation description of terms..................................................635

www.geehy.com Page 7
Introduction............................................................................................................635
Structure block diagram........................................................................................635
Functional description ...........................................................................................635
Register address mapping....................................................................................639
Register functional description..............................................................................639
Random number generator (RNG) ..................................................645
Introduction............................................................................................................645
Main characteristics ..............................................................................................645
Functional description ...........................................................................................645
Register address mapping....................................................................................646
Register functional description..............................................................................646
CRYP..................................................................................................649
Introduction............................................................................................................649
Main characteristics ..............................................................................................649
Interrupt.................................................................................................................649
DMA ......................................................................................................................650
Register address mapping....................................................................................650
Register functional description..............................................................................650
Cyclic redundancy check computing unit (CRC)...........................655
Introduction............................................................................................................655
Functional description ...........................................................................................655
Register address mapping....................................................................................655
Register functional description..............................................................................655
Chip electronic signature.................................................................657
Introduction............................................................................................................657
Register functional description..............................................................................657
Version History .................................................................................658

www.geehy.com Page 8
Introduction and document description rules
Introduction
This user manual provides application developers with all the information about
how to use MCU (micro-controller) system architecture, memory and
peripherals.
For information about Arm® Cortex®-M4 core, please refer to Arm® Cortex® -M4
Technical Reference Manual; please refer to the corresponding datasheet for
detailed data such as model information, dimension and electrical
characteristics of the device; for all MCU series models, please refer to the
corresponding datasheet for memory mapping, peripheral existence and their
number.
Document description rules
"Register functional description" rules
Control (CTRL) registers are all "set to 1 and cleared to 0 by software",
unless otherwise specified.
The control registers are usually followed by verb abbreviations to make
a distinction. The verbs can be: EN-Enable, CFG-Configure, D-Disable,
SET-Setup and SEL-Select
The state register abbreviation is usually followed by FLG to make a
difference.
The value and data registers usually include V, VALUE, D and DATA,
which are not followed by verbs, such as: xxPSC and CNT.
Full name and abbreviation description of terms
Table 1 Abbreviation and Description of R/W Modes
R/W mode
Description
Abbreviation
read/write
Software can read and write this bit.
R/W
read-only
Software can only read this bit.
R
write-only
Software can only write this bit, and after reading this bit, the
reset value will be returned.
W
read/clear
The software can read this bit and clear it by writing 1. Writing
0 has no effect on this bit.
RC_W1
read/clear
The software can read this bit and clear it by writing 0. Writing
1 has no effect on this bit.
RC_W0
read/clear by read
The software can read this bit and reading this bit will
automatically clear it to 0, and writing this bit is invalid.
RC_R

www.geehy.com Page 9
R/W mode
Description
Abbreviation
read/set
The software can read and set this bit, and writing 0 has no
effect on this bit.
R/S
read-only write trigger
The software can read this bit and writing 0 or 1 can trigger an
event but has no effect on the value of this bit.
RT_W
toggle
The software can flip this bit only by writing 1 and writing 0 has
no effect on this bit.
T
Table 2 Functional Description and Full Name and Abbreviation of Terms of Commonly
Used Registers
Full name in English
English abbreviation
Enable
EN
Disable
D
Clear
CLR
Select
SEL
Configure
CFG
Contrl
CTRL
Controller
C
Reset
RST
Stop
STOP
Set
SET
Load
LD
Calibration
CAL
Initialize
INIT
Error
ERR
Status
STS
Ready
RDY
Software
SW
Hardware
HW
Source
SRC
System
SYS
Peripheral
PER
Address
ADDR
Direction
DIR
Clock
CLK
Input
I

www.geehy.com Page 10
Full name in English
English abbreviation
Output
O
Interrupt
INT
Data
DATA
Size
SIZE
Divider
DIV
Prescaler
PSC
Multiplier
MUL
Period
PRD
Table 3 Full Name and Abbreviation of Modules
Full name in English
English abbreviation
External Memory Controller
EMMC
Static Memory Controller
SMC
Dynamic memory Controller
DMC
Reset and Clock Management Unit
RCM
Power Management Unit
PMU
Backup Register
BAKPR
Nested Vector Interrupt Controller
NVIC
External Interrupt /Event Controller
EINT
Direct Memory Access
DMA
Debug MCU
DBG MCU
General-Purpose Input Output Pin
GPIO
Alternate Function Input Output Pin
AFIO
Timer
TMR
Watchdog Timer
WDT
Independent Watchdog Timer
IWDT
Windows Watchdog Timer
WWDT
Real-Time Clock
RTC
Universal Synchronous Asynchronous Receiver Transmitter
USART
Inter-Integrated Circuit Interface
I2C
Serial Peripheral Interface
SPI
Inter-IC Sound Interface
I2S
Quad Serial Peripheral Interface
QSPI

www.geehy.com Page 11
Full name in English
English abbreviation
Controller Area Network
CAN
Secure Digital Input and Output
SDIO
Universal Serial Bus Full-Speed Device
USBD
Analog-to-Digital Converter
ADC
Digital-to-Analog Converter
DAC
Cyclic Redundancy Check Calculation Unit
CRC
Float Point Unit
FPU

www.geehy.com Page 12
System architecture
Full name and abbreviation description of terms
Table 4 Full name and abbreviation description of terms
Full name in English
English abbreviation
Advanced High-Performance Bus
AHB
Advanced Peripheral Bus
APB
Core Couple Memory
CCM
System architecture block diagram
Arm® Cortex®-M4 core in the product has FPU, while the FPU of other series of
products (unless otherwise specified) is beyond the core.
The system mainly consists of eight master modules and seven slave modules.
The master modules are I-bus, D-bus and S-bus of Arm® Cortex®-M4 core with
FPU, general-purpose DMA1, general-purpose DMA2, and DMA2 peripheral
bus, Ethernet DMA bus and USB OTG HS DMA bus.
The slave modules are internal Flash I-bus, D-bus, main internal memory
SRAM1, auxiliary internal memory SRAM2, AHB1 bus and AHB1/APB bridge
connected peripherals, peripherals on AHB2 bus and EMMC.
The bus matrix provides a platform to support the master module to access the
slave module. The matrix can realize concurrent access, and the CPU still has
efficient processing capacity when multiple peripherals are running at high
speed.
It also has a 64-bit core couple memory, and it can access only through CPU.
The name and description of the bus are shown in the following table.
Table 5 Bus Name
Name
Description
I-bus
Connect the instruction bus of Arm® Cortex® -M4 core and the bus matrix.
Used for obtaining instructions.
D-bus
Connect the data bus of Arm® Cortex® -M4 core and the bus matrix.
Used for text loading and debugging access.
S-bus
Connect the system bus of Arm® Cortex® -M4 core and the bus matrix.
Used for accessing the data in peripherals and SRAM.
DMA memory bus
Connect the main interface of DMA memory and the bus matrix.
Realize transmission related to the memory through DMA.

www.geehy.com Page 13
Name
Description
DMA peripheral bus
Connect the main interface of DMA peripherals and the bus matrix.
It can not only realize access of DMA to the peripherals on AHB, but also
realize transmission among memories.
Ethernet DMA bus
Connect the main interface of Ethernet DMA and the bus matrix.
The data are loaded/stored in the memory through Ethernet DMA.
USB OTG HS DMA
bus
Connect the main interface of USB OTG HS DMA and the bus matrix.
The data are loaded/stored in the memory through USB OTG DMA.
Bus matrix
Coordinate the access among modules, and roll polling algorithm is used
during arbitration.
AHB/APB bridge
The bridge provides synchronous connection between AHB and APB buses.
The non-32-bit access to APB register will be converted into 32 bits
automatically.

www.geehy.com Page 14
Figure 1 APM32F405/415xG、APM32F407/417xExG System Architecture Block
Diagram
M4 with FPU
NVIC
JTAG/SWD
S-bus
I-bus
CCM Data RAM
AHB bus matrix
ART
FMC
Flash
Main SRAM1
Annex SRAM2
DMA1
DMA2
Ethernet MAC
Fast USB OTG
EMMC SRAM/External
memory
AHB/APB1 AHB/APB2
TMR2/3/4/5/6/7/12/13
/14
RTC
WWDT
IWDT
SPI2/I2S2
SPI3/I2S3
USART2/3
UART4/5
I2C1/2/3
TMR1/8/9/10/11
USART1/6
ADC1/2/3
SDIO
SPI1
SYSCFG
EINT
T-Sensor
CAN1/2
DAC1/2
AHB1
I Code
D Code
GPIO A-I
CRC
RCM
Fast USB OTG
Camera interface
RNG
D-bus
AHB2
CRYP
Note:
(1) APM32F415xG/APM32F417xExG has HASH processor and CRYP, while
APM32F405xG/APM32F407xExG does not have; APM32F407/417xExG has Ethernet and
DCI, while APM32F405/415xG does not have.
(2) Actually, APM32F405/415xG、APM32F407/417xExG series has two USB OTG_HS, and they
share the clock, reset, bus address, CPU interrupt, power supply, pins and other related

www.geehy.com Page 15
resources. Only one of two USB OTG_HS can be used at the same time. Their difference is:
one has on-chip UTMI USB PHY (there is internal PLL with 60MHz output), while the other
does not have.
Memory mapping
The assigned addresses of memory mapping include the core (including core
peripherals), on-chip Flash (including main memory area, system memory area
and option bytes), on-chip SRAM, and bus peripherals (including AHB and APB
peripherals). Please refer to the data manual of the corresponding model for
specific information of various addresses.
Embedded SRAM
The product has backup SRAM (4KB) and system SRAM (192KB). The system
SRAM is divided into three parts: SRAM1 (112KB), SRAM2 (16KB) and CCM
(64KB).
SRAM1 and SRAM2
The main SRAM1 and auxiliary SRAM2 can be accessed by byte, half word (16
bits) or full word (32 bits). The mapping address of SRAM1 and SRAM2 is
0x2000 0000, and the main module can be accessoed by all AHB.
Core couple memory (CCM)
The mapping address of CCM (64KB) is 0x1000 0000, and it can only be
accessed by CPU through D-bus.
Bit band
Arm® Cortex®-M4 memory is mapped with two bit-band areas, and it maps each
word in the alias memory area to one bit in the bit-band memory. Write a word to
the alias memory and there will be the same effect as the read-change-write
operation on the target of the bit-band area. Both peripheral register and SRAM
are mapped into a bit band area, and it is allowed to perform single bit-band
write and read operations.
The following gives a mapping formula:
bit_word_addr=bit_band_base+（byte_offset×32）+（bit_number×4）
Startup configuration
APM32F4xx series MCU realizes a special mechanism. By configuring the
BOOT[1:0] pin, there are three different startup modes, and the system can not
only start from Flash memory or system memory, but also start from the built-in
SRAM. The memory selected as the start zone is determined by the selected

www.geehy.com Page 16
startup mode.
Table 6 Startup Mode Configuration and Access Mode
Startup mode
configuration
Startup mode
Access mode
BOOT1 pin
BOOT0 pin
X
0
Main flash
memory
（Flash）
The main flash memory is mapped to the boot
space, but it can still be accessed at its original
address, that is, the contents of the flash memory
can be accessed in two address areas.
0
1
System
memory
The system memory is mapped to the boot space
(0x0000 0000), but it can still be accessed at its
original address.
1
1
Built-in SRAM
SRAM can be accessed only at the starting
address.
Note:
(1) The boot space address is 0x0000 0000
(2) The original address of Flash is 0x0800 0000
(3) The original address of the system memory is 0x1FFF 0000
(4) The starting address of SRAM is 0x2000 0000
(5) The user can select the startup mode after reset by setting the state of BOOT[1:0] pin.
(6) BOOT pin should keep the user's required startup configuration in standby mode. When
exiting from the standby mode, the value of boot pin will be latched.
(7) If you choose to start from built-in SRAM, you must use NVIC's exception table and offset
register to remap the vector table to SRAM when writing the application code.
Physical remapping
After BOOT pin is selected, MMSEL bit of SYSCFG_MMSEL register can be
modified through software program to configure some register to allow access
from I-Code bus. See SYSCFG register for specific configuration.
Embedded BootLoader
The embedded BootLoader mode will be selected to reprogram Flash through
which of the following serial port:
USART1
USART3
CAN2
USB OTG_FS slave mode

www.geehy.com Page 17
FLASH memory
Full name and abbreviation description of terms
Table 7 Full name and abbreviation description of terms
Full name in English
English abbreviation
Flash Memory Controller
FMC
One-time Programmable
OTP
Adaptive Real-time
ART
Introduction
This chapter mainly introduces the storage structure, read, erase, write,
read/write protection, unlock/lock characteristics of Flash, and the involved
register functional description.
Main characteristics
Flash memory structure
Contain main memory area and information block
The capacity of main memory area is up to 1MB
The information block is divided into system memory, OTP area and
option byte three areas
The capacity of the system memory area is 30KB, for storing
BootLoader program, 96-bit unique UID, and main memory area
capacity information
The OTP area is 528Bytes, 512 OTP bytes are used for storing user
data, and the remaining 16 bytes are used for locking the
corresponding OTP data block
The capacity of the option byte area is 16Bytes
Functional Description
Operate the Flash:
-Read
-Sector/Mass Erase
-Write
-Read/Write protection
Operate the option byte:
-Read
-Erase
-Write
-Read/Write protection

www.geehy.com Page 18
Flash memory structure
Table 8 Flash Memory Structure
Block
Name
Address range
Size (byte)
Sector
Main memory block
0x0800 0000–0x0800 3FFF
16K
Sector 0
0x0800 4000–0x0800 7FFF
16K
Sector 1
0x0800 8000–0x0800 BFFF
16K
Sector 2
0x0800 C000–0x0800 FFFF
16K
Sector 3
0x0801 0000 – 0x0801 FFFF
64K
Sector 4
0x0802 0000 – 0x0803 FFFF
128K
Sector 5
…
…
…
0x080E 0000–0x080F FFFF
128K
Sector 11
Information
block
System
memory
0x1FFF 0000–0x1FFF 77FF
30K
-
OTP area
0x1FFF 7800–0x1FFF 7A0F
528
-
Option byte
0x1FFF C000–0x1FFF C00F
16
-
Note: The number of sectors included by the main memory block of APM32F405/415xG、
APM32F407/417xExG series products is related to the capacity of specific Flash; see the Data Manual
for the capacity of Flash of different models.
Flash memroy functional description
Read Flash
Flash has a prefetch buffer area, and it can be turned on only when the power
supply voltage is not lower than 2.1V.
The reading speed of Flash is affected by the number of wait cycles, and the
number of wait cycles is affected by HCLK and power supply voltage. Assuming
the wait cycle is n, and the rising base of HCLK range is X
When (n+1) X is less than the maximum value:
nX＜HCLK≤（n+1）X
When (n-1) X is greater than the maximum value:
nX＜HCLK≤ maximum value
Table 9 X Affected by Voltage Range and Maximum Value of HCLK
Voltage range
1.8V-2.1V
2.1V-2.4V
2.4V-2.7V
2.7V-3.6V
X
20MHz
22MHz
24MHz
30MHz
Maximum value
160MHz
168MHz
168MHz
168MHz
Note:

www.geehy.com Page 19
When PMU_CTRL register VOSSEL=0, the maximum value of HCLK is 144MHz; when VOSSEL=1, the
maximum value of HCLK is 168MHz.
CPU frequency can be adjusted by selecting different wait cycles, so as to
adjust the reading speed of Flash.
Adaptive real-time memory accelerator (ART)
ART accelerator can improve the execution speed of Flash, so that the Flash
can execute programs with fewer wait cycles at high CPU frequency.
Prefetch buffer area
When needing to insert wait cycle to access Flash, the next instruction line of
Flash can be pre-read through I-Code bus, to improve the access rate.
I-cache
I-cache is an instruction buffer memory. The instructions in I-cache can be
obtained without delay. The system can store 64 lines of 128-bit instructions in I-
cache and the I-cache function can be enabled through ICACHEEN bit of
FMC_ACCTRL register.
D-cache
D-cache is a data buffer memory. The system accesses the data buffer area of
Flash through D-Bus to reduce the waiting time. Access of D-bus is prior to I-
bus. The system can store 8 lines of 128-bit instructions in D-cache and the D-
cache function can be enabled through DCACHEEN bit of FMC_ACCTRL
register.
Main memory block
When erasing/writing to the main memory, Flash can no longer be read.
Number of parallel bits
The number of parallel bits is the number of bytes to be processed when
erasing/writing to the Flash, and it is determined by the power supply voltage
and the use of external power supply. The number of parallel bits is configured
by programming the PGSIZE bit of FMC_CTRL register. The determinant
factors and the number of parallel bits are shown in the table below:
Table 10 Relationship between Determinant Factors and Number of Parallel Bits
Voltage range (V)
1.8-2.1
2.1-2.4
2.4-2.7
2.7-3.6
2.7-3.6 (external VPP is used)
Number of parallel
bits
8-bit
16-bit
32-bit
64-bit