Geehy SEMICONDUCTOR APM32F405/415 G Series User manual

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User Manual
APM32F405/415xG
APM32F407/417xExG
Arm® Cortex®-M4 based 32-bit MCU
Version: V1.4

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Contents
Introduction and document description rules....................................8
Introduction................................................................................................................8
Document description rules ......................................................................................8
System architecture ...........................................................................12
Full name and abbreviation description of terms....................................................12
System architecture block diagram.........................................................................12
Memory mapping ....................................................................................................15
Startup configuration...............................................................................................15
FLASH memory...................................................................................17
Full name and abbreviation description of terms....................................................17
Introduction..............................................................................................................17
Main characteristics ................................................................................................17
Flash memory structure ..........................................................................................18
Flash memroy functional description ......................................................................18
Register address mapping......................................................................................25
Register functional description................................................................................25
External Memory Controller (EMMC) ................................................30
Full name and abbreviation description of terms....................................................30
EMMC Overview .....................................................................................................30
SMC Introduction ....................................................................................................30
SMC Structure Block Diagram................................................................................31
SMC Functional Description ...................................................................................31
SMC register address mapping ..............................................................................37
SMC register functional description........................................................................38
DMC introduction ....................................................................................................47
Main characteristics of DMC...................................................................................47
DMC structure block diagram .................................................................................48
DMC functional description .....................................................................................48
DMC register address mapping..............................................................................50
DMC register functional description........................................................................50
System configuration controller (SYSCFG)......................................55
Main characteristics ................................................................................................55
I/O compensation cell..............................................................................................55
Register address mapping......................................................................................55
Register functional description................................................................................55

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Reset and clock (RCM).......................................................................60
Full name and abbreviation description of terms....................................................60
Reset management unit (RMU) ..............................................................................60
Clock management unit (CMU)...............................................................................63
Register address mapping......................................................................................70
Register functional description................................................................................71
Power management unit (PMU) .......................................................101
Full name and abbreviation description of terms..................................................101
Introduction............................................................................................................101
Structure block diagram........................................................................................102
Functional description ...........................................................................................102
Register address mapping....................................................................................109
Register functional description..............................................................................109
Nested vector interrupt controller (NVIC).......................................112
Full name and abbreviation description of terms..................................................112
Introduction............................................................................................................112
Main characteristics ..............................................................................................112
Interrupt and exception vector table .....................................................................112
External Interrupt/Event Controller (EINT) .....................................120
Introduction............................................................................................................120
Main Characteristics..............................................................................................120
Functional description ...........................................................................................120
Register address mapping....................................................................................123
Register functional description..............................................................................123
Direct memory access (DMA) ..........................................................126
Introduction............................................................................................................126
Main characteristics ..............................................................................................126
Functional description ...........................................................................................126
DMA register address mapping.............................................................................133
Register functional description..............................................................................133
Debug MCU (DBGMCU)....................................................................142
Full name and abbreviation description of terms..................................................142
Introduction............................................................................................................142
Main characteristics ..............................................................................................142
Functional description ...........................................................................................143
Register address mapping....................................................................................144
Register functional description..............................................................................144

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General-Purpose Input/Output Pin (GPIO) .....................................149
Full name and abbreviation description of terms..................................................149
Main characteristics ..............................................................................................149
Structure block diagram........................................................................................150
Functional description ...........................................................................................150
Register address mapping....................................................................................154
Register functional description..............................................................................154
Timer overview..................................................................................159
Full name and abbreviation description of terms..................................................159
Timer category and main difference .....................................................................159
Advanced Timers (TMR1/8)..............................................................162
Introduction............................................................................................................162
Main characteristics ..............................................................................................162
Structure block diagram........................................................................................163
Functional description ...........................................................................................163
Register address mapping....................................................................................180
Register functional description..............................................................................181
General-purpose timer (TMR2/3/4/5) ...............................................200
Introduction............................................................................................................200
Main characteristics ..............................................................................................200
Structure block diagram........................................................................................201
Functional description ...........................................................................................201
Register address mapping....................................................................................214
Register functional description..............................................................................214
General-purpose timer (TMR9/10/11/12/13/14)................................231
Introduction............................................................................................................231
Main characteristics of TMR9/12 ..........................................................................231
Main characteristics of TMR10/11/13/14 ..............................................................231
TMR9/12 structure block diagram.........................................................................232
TMR10/11/13/14 structure block diagram.............................................................233
Functional description ...........................................................................................233
TMR9/12 register address mapping .....................................................................240
TMR9/12 register functional description ...............................................................241
TMR10/11/13/14 register address mapping..........................................................250
TMR10/11/13/14 register functional description ...................................................251
Basic timer (TMR6/7) ........................................................................258
Introduction............................................................................................................258

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Main characteristics ..............................................................................................258
Structure block diagram........................................................................................258
Functional description ...........................................................................................258
Register address mapping....................................................................................260
Register functional description..............................................................................261
Watchdog timer (WDT) .....................................................................265
Introduction............................................................................................................265
Independent watchdog timer (IWDT)....................................................................265
Window watchdog timer (WWDT).........................................................................267
IWDT register address mappin .............................................................................268
IWDT register functional description.....................................................................269
WWDT register address mappin...........................................................................270
WWDT register functional description ..................................................................270
Real-time clock (RTC).......................................................................272
Full name and abbreviation description of terms..................................................272
Introduction............................................................................................................272
Main characteristics ..............................................................................................272
Structure block diagram........................................................................................272
Functional description ...........................................................................................273
Register address mapping....................................................................................279
Register functional description..............................................................................280
HASH processor (HASH)..................................................................296
Introduction............................................................................................................296
Main characteristics ..............................................................................................296
Functional description ...........................................................................................296
Register address mapping....................................................................................297
Register functional description..............................................................................297
Digital camera interface (DCI)..........................................................302
Full name and abbreviation description of terms..................................................302
Introduction............................................................................................................302
Main characteristics ..............................................................................................302
Structure block diagram........................................................................................303
Functional description ...........................................................................................303
Register address mapping....................................................................................307
Register functional description..............................................................................308
Universal synchronous/asynchronous transceiver (USART) .......314
Full name and abbreviation description of terms..................................................314

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Introduction............................................................................................................314
Main characteristics ..............................................................................................314
Functional description ...........................................................................................316
Register address mapping....................................................................................330
Register functional description..............................................................................330
Internal integrated circuit interface (I2C)........................................338
Full name and abbreviation description of terms..................................................338
Introduction............................................................................................................338
Main characteristics ..............................................................................................338
Structure block diagram........................................................................................340
Functional description ...........................................................................................340
Register address mapping....................................................................................347
Register functional description..............................................................................347
Serial peripheral interface/On-chip audio interface (SPI/I2S) .......357
Full name and abbreviation description of terms..................................................357
Introduction............................................................................................................357
Main characteristics ..............................................................................................358
SPI functional description .....................................................................................359
I2S functional description......................................................................................370
Register address mapping....................................................................................382
Register functional description..............................................................................383
Controller area network (CAN) ........................................................390
Full name and abbreviation description of terms..................................................390
Introduction............................................................................................................390
Main characteristics ..............................................................................................390
Functional description ...........................................................................................390
Register address mapping....................................................................................399
Register functional description..............................................................................400
Secure digital input/output interface (SDIO) ..................................418
Full name and abbreviation description of terms..................................................418
Introduction............................................................................................................418
Main characteristics ..............................................................................................418
Functional description ...........................................................................................418
Register address mapping....................................................................................441
Register functional description..............................................................................441
USB_OTG ..........................................................................................453
Introduction............................................................................................................453

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OTG_FS global register address mapping...........................................................453
OTG_FS global register functional description.....................................................454
OTG_FS host mode register address mapping....................................................468
OTG_FS host mode register functional description..............................................469
OTG_FS device mode register address mapping ................................................475
OTG_FS device mode register functional description..........................................476
Full-speed OTG power and clock gating control register (OTG_FS_PCGCTRL) 491
OTG_HS1 global register address mapping.........................................................492
OTG_HS1 global register functional description ..................................................493
OTG_HS1 host mode register address mapping .................................................510
OTG_HS1 host mode register functional description ...........................................510
OTG_HS1 device mode register address mapping..............................................518
OTG_HS1 device mode register functional description .......................................519
High-speed OTG power and clock gating control register
(OTG_HS1_PCGCTRL) ..................................................................................................537
OTG_HS2 register address mapping ...................................................................538
OTG_HS2 global register functional description ..................................................538
Ethernet .............................................................................................540
Introduction............................................................................................................540
Main characteristics of Ethernet............................................................................540
Functional description ...........................................................................................543
MAC register address mapping ............................................................................572
MAC register functional description......................................................................573
MMC register address mapping............................................................................589
MMC register functional description .....................................................................589
PTP register address mapping .............................................................................593
PTP register functional description.......................................................................593
DMA register address mapping.............................................................................598
DMA register functional description ......................................................................598
Analog-to-digital converter (ADC)...................................................610
Full name and abbreviation description of terms..................................................610
Introduction............................................................................................................611
Main characteristics ..............................................................................................611
Functional description ...........................................................................................612
Register address mapping....................................................................................623
Register functional description..............................................................................624
Digital-to-analog converter (DAC) ...................................................635
Full name and abbreviation description of terms..................................................635

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Introduction............................................................................................................635
Structure block diagram........................................................................................635
Functional description ...........................................................................................635
Register address mapping....................................................................................639
Register functional description..............................................................................639
Random number generator (RNG) ..................................................645
Introduction............................................................................................................645
Main characteristics ..............................................................................................645
Functional description ...........................................................................................645
Register address mapping....................................................................................646
Register functional description..............................................................................646
CRYP..................................................................................................649
Introduction............................................................................................................649
Main characteristics ..............................................................................................649
Interrupt.................................................................................................................649
DMA ......................................................................................................................650
Register address mapping....................................................................................650
Register functional description..............................................................................650
Cyclic redundancy check computing unit (CRC)...........................655
Introduction............................................................................................................655
Functional description ...........................................................................................655
Register address mapping....................................................................................655
Register functional description..............................................................................655
Chip electronic signature.................................................................657
Introduction............................................................................................................657
Register functional description..............................................................................657
Version History .................................................................................658

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Introduction and document description rules
Introduction
This user manual provides application developers with all the information about
how to use MCU (micro-controller) system architecture, memory and
peripherals.
For information about Arm® Cortex®-M4 core, please refer to Arm® Cortex® -M4
Technical Reference Manual; please refer to the corresponding datasheet for
detailed data such as model information, dimension and electrical
characteristics of the device; for all MCU series models, please refer to the
corresponding datasheet for memory mapping, peripheral existence and their
number.
Document description rules
"Register functional description" rules
Control (CTRL) registers are all "set to 1 and cleared to 0 by software",
unless otherwise specified.
The control registers are usually followed by verb abbreviations to make
a distinction. The verbs can be: EN-Enable, CFG-Configure, D-Disable,
SET-Setup and SEL-Select
The state register abbreviation is usually followed by FLG to make a
difference.
The value and data registers usually include V, VALUE, D and DATA,
which are not followed by verbs, such as: xxPSC and CNT.
Full name and abbreviation description of terms
Table 1 Abbreviation and Description of R/W Modes
R/W mode
Description
Abbreviation
read/write
Software can read and write this bit.
R/W
read-only
Software can only read this bit.
R
write-only
Software can only write this bit, and after reading this bit, the
reset value will be returned.
W
read/clear
The software can read this bit and clear it by writing 1. Writing
0 has no effect on this bit.
RC_W1
read/clear
The software can read this bit and clear it by writing 0. Writing
1 has no effect on this bit.
RC_W0
read/clear by read
The software can read this bit and reading this bit will
automatically clear it to 0, and writing this bit is invalid.
RC_R

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R/W mode
Description
Abbreviation
read/set
The software can read and set this bit, and writing 0 has no
effect on this bit.
R/S
read-only write trigger
The software can read this bit and writing 0 or 1 can trigger an
event but has no effect on the value of this bit.
RT_W
toggle
The software can flip this bit only by writing 1 and writing 0 has
no effect on this bit.
T
Table 2 Functional Description and Full Name and Abbreviation of Terms of Commonly
Used Registers
Full name in English
English abbreviation
Enable
EN
Disable
D
Clear
CLR
Select
SEL
Configure
CFG
Contrl
CTRL
Controller
C
Reset
RST
Stop
STOP
Set
SET
Load
LD
Calibration
CAL
Initialize
INIT
Error
ERR
Status
STS
Ready
RDY
Software
SW
Hardware
HW
Source
SRC
System
SYS
Peripheral
PER
Address
ADDR
Direction
DIR
Clock
CLK
Input
I