NXP Semiconductors MC9S08PA4 User manual

MC9S08PA4 Reference Manual
Supports: MC9S08PA4
Document Number: MC9S08PA4RM
Rev. 5, 08/2017

MC9S08PA4 Reference Manual, Rev. 5, 08/2017
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Contents
Section number Title Page
Chapter 1
Device Overview
1.1 Introduction.....................................................................................................................................................................23
1.2 MCU block diagram....................................................................................................................................................... 24
1.3 System clock distribution................................................................................................................................................25
Chapter 2
Pins and connections
2.1 Device pin assignment.................................................................................................................................................... 29
2.2 Pin functions................................................................................................................................................................... 30
2.2.1 Power (VDD, VSS)..........................................................................................................................................30
2.2.2 Oscillator (XTAL, EXTAL)............................................................................................................................ 31
2.2.3 External reset pin (RESET) and interrupt pin (IRQ)....................................................................................... 32
2.2.4 Background/mode select (BKGD/MS)............................................................................................................ 33
2.2.5 Port A input/output (I/O) pins (PTA5–PTA0)................................................................................................. 34
2.2.6 Port B input/output (I/O) pins (PTB7–PTB0)..................................................................................................34
2.2.7 Port C input/output (I/O) pins (PTC3–PTC0)..................................................................................................34
2.2.8 True open drain pins (PTB0)........................................................................................................................... 34
2.2.9 High current drive pins (PTB4, PTB5)............................................................................................................ 34
2.3 Peripheral pinouts........................................................................................................................................................... 35
Chapter 3
Power management
3.1 Introduction.....................................................................................................................................................................37
3.2 Features...........................................................................................................................................................................37
3.2.1 Run mode......................................................................................................................................................... 37
3.2.2 Wait mode........................................................................................................................................................38
3.2.3 Stop3 mode...................................................................................................................................................... 38
3.2.4 Active BDM enabled in stop3 mode................................................................................................................38
3.2.5 LVD enabled in stop mode.............................................................................................................................. 39
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3.2.6 Power modes behaviors................................................................................................................................... 39
3.3 Low voltage detect (LVD) system..................................................................................................................................40
3.3.1 Power-on reset (POR) operation......................................................................................................................41
3.3.2 LVD reset operation.........................................................................................................................................41
3.3.3 Low-voltage warning (LVW).......................................................................................................................... 41
3.4 Bandgap reference.......................................................................................................................................................... 42
3.5 Power management control bits and registers................................................................................................................ 42
3.5.1 System Power Management Status and Control 1 Register (PMC_SPMSC1)................................................42
3.5.2 System Power Management Status and Control 2 Register (PMC_SPMSC2)................................................44
Chapter 4
Memory map
4.1 Memory map...................................................................................................................................................................45
4.2 Reset and interrupt vector assignments...........................................................................................................................46
4.3 Register addresses and bit assignments.......................................................................................................................... 47
4.4 Random-access memory (RAM).................................................................................................................................... 55
4.5 Flash and EEPROM........................................................................................................................................................56
4.5.1 Overview..........................................................................................................................................................56
4.5.2 Function descriptions....................................................................................................................................... 58
4.5.2.1 Modes of operation.......................................................................................................................... 58
4.5.2.2 Flash and EEPROM memory map...................................................................................................58
4.5.2.3 Flash and EEPROM initialization after system reset.......................................................................58
4.5.2.4 Flash and EEPROM command operations.......................................................................................59
4.5.2.5 Flash and EEPROM interrupts.........................................................................................................64
4.5.2.6 Protection......................................................................................................................................... 65
4.5.2.7 Security............................................................................................................................................ 68
4.5.2.8 Flash and EEPROM commands.......................................................................................................70
4.5.2.9 Flash and EEPROM command summary........................................................................................ 72
4.6 Flash and EEPROM registers descriptions.....................................................................................................................86
4.6.1 Flash Clock Divider Register (NVM_FCLKDIV)...........................................................................................86
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4.6.2 Flash Security Register (NVM_FSEC)............................................................................................................87
4.6.3 Flash CCOB Index Register (NVM_FCCOBIX)............................................................................................ 88
4.6.4 Flash Configuration Register (NVM_FCNFG)............................................................................................... 88
4.6.5 Flash Error Configuration Register (NVM_FERCNFG).................................................................................89
4.6.6 Flash Status Register (NVM_FSTAT).............................................................................................................90
4.6.7 Flash Error Status Register (NVM_FERSTAT).............................................................................................. 91
4.6.8 Flash Protection Register (NVM_FPROT)......................................................................................................92
4.6.9 EEPROM Protection Register (NVM_EEPROT)............................................................................................93
4.6.10 Flash Common Command Object Register:High (NVM_FCCOBHI)............................................................94
4.6.11 Flash Common Command Object Register: Low (NVM_FCCOBLO)...........................................................95
4.6.12 Flash Option Register (NVM_FOPT)..............................................................................................................95
Chapter 5
Interrupt
5.1 Interrupts.........................................................................................................................................................................97
5.1.1 Interrupt stack frame........................................................................................................................................ 98
5.1.2 Interrupt vectors, sources, and local masks......................................................................................................99
5.1.3 Hardware nested interrupt................................................................................................................................101
5.1.3.1 Interrupt priority level register.........................................................................................................103
5.1.3.2 Interrupt priority level comparator set............................................................................................. 104
5.1.3.3 Interrupt priority mask update and restore mechanism....................................................................104
5.1.3.4 Integration and application of the IPC............................................................................................. 105
5.2 IRQ..................................................................................................................................................................................105
5.2.1 Features............................................................................................................................................................ 106
5.2.1.1 Pin configuration options.................................................................................................................106
5.2.1.2 Edge and level sensitivity................................................................................................................ 107
5.3 Interrupt pin request register...........................................................................................................................................107
5.3.1 Interrupt Pin Request Status and Control Register (IRQ_SC).........................................................................108
5.4 Interrupt priority control register.................................................................................................................................... 109
5.4.1 IPC Status and Control Register (IPC_SC)......................................................................................................110
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5.4.2 Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)........................................................................ 111
5.4.3 Interrupt Level Setting Registers n (IPC_ILRSn)............................................................................................111
Chapter 6
System control
6.1 System device identification (SDID)..............................................................................................................................113
6.2 Universally unique identification (UUID)......................................................................................................................113
6.3 Reset and system initialization........................................................................................................................................113
6.4 System options................................................................................................................................................................114
6.4.1 BKGD pin enable.............................................................................................................................................114
6.4.2 RESET pin enable............................................................................................................................................114
6.4.3 SCI0 pin reassignment..................................................................................................................................... 114
6.4.4 FTM0 channels pin reassignment.................................................................................................................... 115
6.4.5 FTM1 pin reassignment................................................................................................................................... 115
6.5 System interconnection...................................................................................................................................................115
6.5.1 ACMP output selection....................................................................................................................................115
6.5.2 SCI0 TxD modulation......................................................................................................................................116
6.5.3 SCI0 RxD capture............................................................................................................................................ 116
6.5.4 SCI0 RxD filter................................................................................................................................................ 117
6.5.5 RTC capture..................................................................................................................................................... 117
6.5.6 ADC hardware trigger......................................................................................................................................117
6.6 System Control Registers................................................................................................................................................118
6.6.1 System Reset Status Register (SYS_SRS).......................................................................................................119
6.6.2 System Background Debug Force Reset Register (SYS_SBDFR)..................................................................121
6.6.3 System Device Identification Register: High (SYS_SDIDH)......................................................................... 121
6.6.4 System Device Identification Register: Low (SYS_SDIDL).......................................................................... 122
6.6.5 System Options Register 1 (SYS_SOPT1)...................................................................................................... 122
6.6.6 System Options Register 2 (SYS_SOPT2)...................................................................................................... 124
6.6.7 System Options Register 3 (SYS_SOPT3)...................................................................................................... 125
6.6.8 Illegal Address Register: High (SYS_ILLAH)................................................................................................126
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6.6.9 Illegal Address Register: Low (SYS_ILLAL).................................................................................................126
6.6.10 Universally Unique Identifier Register 1 (SYS_UUID1)................................................................................127
6.6.11 Universally Unique Identifier Register 2 (SYS_UUID2)................................................................................127
6.6.12 Universally Unique Identifier Register 3 (SYS_UUID3)................................................................................128
6.6.13 Universally Unique Identifier Register 4 (SYS_UUID4)................................................................................128
6.6.14 Universally Unique Identifier Register 5 (SYS_UUID5)................................................................................129
6.6.15 Universally Unique Identifier Register 6 (SYS_UUID6)................................................................................129
6.6.16 Universally Unique Identifier Register 7 (SYS_UUID7)................................................................................130
6.6.17 Universally Unique Identifier Register 8 (SYS_UUID8)................................................................................130
Chapter 7
Parallel input/output
7.1 Introduction.....................................................................................................................................................................131
7.2 Port data and data direction.............................................................................................................................................133
7.3 Internal pullup enable..................................................................................................................................................... 133
7.4 Input glitch filter setting..................................................................................................................................................134
7.5 High current drive...........................................................................................................................................................134
7.6 Pin behavior in stop mode...............................................................................................................................................134
7.7 Port data registers............................................................................................................................................................134
7.7.1 Port A Data Register (PORT_PTAD)..............................................................................................................135
7.7.2 Port B Data Register (PORT_PTBD).............................................................................................................. 136
7.7.3 Port C Data Register (PORT_PTCD).............................................................................................................. 136
7.7.4 Port High Drive Enable Register (PORT_HDRVE)........................................................................................137
7.7.5 Port A Output Enable Register (PORT_PTAOE)............................................................................................137
7.7.6 Port B Output Enable Register (PORT_PTBOE)............................................................................................ 138
7.7.7 Port C Output Enable Register (PORT_PTCOE)............................................................................................ 139
7.7.8 Port A Input Enable Register (PORT_PTAIE)................................................................................................140
7.7.9 Port B Input Enable Register (PORT_PTBIE)................................................................................................ 141
7.7.10 Port C Input Enable Register (PORT_PTCIE)................................................................................................ 142
7.7.11 Port Filter Register 0 (PORT_IOFLT0)...........................................................................................................143
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7.7.12 Port Filter Register 2 (PORT_IOFLT2)...........................................................................................................144
7.7.13 Port Clock Division Register (PORT_FCLKDIV).......................................................................................... 145
7.7.14 Port A Pullup Enable Register (PORT_PTAPE)............................................................................................. 146
7.7.15 Port B Pullup Enable Register (PORT_PTBPE)..............................................................................................147
7.7.16 Port C Pullup Enable Register (PORT_PTCPE)..............................................................................................148
Chapter 8
Clock management
8.1 Clock module..................................................................................................................................................................151
8.2 Internal clock source (ICS)............................................................................................................................................. 152
8.2.1 Function description.........................................................................................................................................153
8.2.1.1 Bus frequency divider...................................................................................................................... 154
8.2.1.2 Low power bit usage........................................................................................................................154
8.2.1.3 Internal reference clock (ICSIRCLK)..............................................................................................154
8.2.1.4 Fixed frequency clock (ICSFFCLK)................................................................................................155
8.2.1.5 BDC clock........................................................................................................................................156
8.2.2 Modes of operation.......................................................................................................................................... 156
8.2.2.1 FLL engaged internal (FEI)............................................................................................................. 157
8.2.2.2 FLL engaged external (FEE)............................................................................................................158
8.2.2.3 FLL bypassed internal (FBI)............................................................................................................158
8.2.2.4 FLL bypassed internal low power (FBILP)..................................................................................... 158
8.2.2.5 FLL bypassed external (FBE)..........................................................................................................159
8.2.2.6 FLL bypassed external low power (FBELP)................................................................................... 159
8.2.2.7 Stop (STOP).....................................................................................................................................160
8.2.3 FLL lock and clock monitor.............................................................................................................................161
8.2.3.1 FLL clock lock.................................................................................................................................161
8.2.3.2 External reference clock monitor.....................................................................................................161
8.3 Initialization / application information........................................................................................................................... 161
8.3.1 Initializing FEI mode....................................................................................................................................... 162
8.3.2 Initializing FBI mode.......................................................................................................................................162
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8.3.3 Initializing FEE mode...................................................................................................................................... 162
8.3.4 Initializing FBE mode......................................................................................................................................163
8.3.5 External oscillator (OSC).................................................................................................................................163
8.3.5.1 Bypass mode.................................................................................................................................... 164
8.3.5.2 Low-power configuration................................................................................................................ 164
8.3.5.3 High-gain configuration...................................................................................................................165
8.3.5.4 Initializing external oscillator for peripherals..................................................................................165
8.4 1 kHz low-power oscillator (LPO)................................................................................................................................. 166
8.5 Peripheral clock gating................................................................................................................................................... 166
8.6 ICS control registers....................................................................................................................................................... 166
8.6.1 ICS Control Register 1 (ICS_C1).................................................................................................................... 167
8.6.2 ICS Control Register 2 (ICS_C2).................................................................................................................... 168
8.6.3 ICS Control Register 3 (ICS_C3).................................................................................................................... 169
8.6.4 ICS Control Register 4 (ICS_C4).................................................................................................................... 169
8.6.5 ICS Status Register (ICS_S)............................................................................................................................ 170
8.6.6 OSC Status and Control Register (ICS_OSCSC)............................................................................................ 171
8.7 System clock gating control registers............................................................................................................................. 172
8.7.1 System Clock Gating Control 1 Register (SCG_C1).......................................................................................173
8.7.2 System Clock Gating Control 2 Register (SCG_C2).......................................................................................174
8.7.3 System Clock Gating Control 3 Register (SCG_C3).......................................................................................175
8.7.4 System Clock Gating Control 4 Register (SCG_C4).......................................................................................175
Chapter 9
Chip configurations
9.1 Introduction.....................................................................................................................................................................177
9.2 Core modules.................................................................................................................................................................. 177
9.2.1 Central processor unit (CPU)...........................................................................................................................177
9.2.2 Debug module (DBG)......................................................................................................................................177
9.3 System modules.............................................................................................................................................................. 178
9.3.1 Watchdog (WDOG)......................................................................................................................................... 178
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9.4 Clock module..................................................................................................................................................................178
9.5 Memory...........................................................................................................................................................................180
9.5.1 Random-access-memory (RAM)..................................................................................................................... 180
9.5.2 Non-volatile memory (NVM).......................................................................................................................... 180
9.6 Power modules................................................................................................................................................................180
9.7 Timers............................................................................................................................................................................. 181
9.7.1 FlexTimer module (FTM)................................................................................................................................181
9.7.1.1 FTM0 interconnection......................................................................................................................182
9.7.1.2 FTM1 interconnection......................................................................................................................183
9.7.2 Real-time counter (RTC)................................................................................................................................. 183
9.8 Communication interfaces.............................................................................................................................................. 185
9.8.1 Serial communications interface (SCI)............................................................................................................185
9.8.1.1 SCI0 infrared functions....................................................................................................................186
9.9 Analog.............................................................................................................................................................................187
9.9.1 Analog-to-digital converter (ADC)..................................................................................................................187
9.9.1.1 ADC channel assignments............................................................................................................... 188
9.9.1.2 Alternate clock................................................................................................................................. 189
9.9.1.3 Hardware trigger.............................................................................................................................. 190
9.9.1.4 Temperature sensor..........................................................................................................................190
9.9.2 Analog comparator (ACMP)............................................................................................................................191
9.9.2.1 ACMP configuration information....................................................................................................192
9.9.2.2 ACMP in stop3 mode.......................................................................................................................193
9.9.2.3 ACMP to FTM configuration information.......................................................................................193
9.9.2.4 ACMP for SCI0 RXD filter............................................................................................................. 193
9.10 Human-machine interfaces HMI.....................................................................................................................................194
9.10.1 Keyboard interrupts (KBI)...............................................................................................................................194
Chapter 10
Central processor unit
10.1 Introduction.....................................................................................................................................................................197
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