General Standards Corporation PC104P-SIO4BX Instructions for use

PC104P-SIO4BX
PCI104-SIO4BX
Hardware User’s Manual
QUAD CHANNELMULTI-PROTOCOL
SERIAL CONTROLLER
WITH DEEPTRANSMITAND RECEIVE FIFOS
AND MULTIPROTOCOL TRANSCEIVERS
RS-485
RS-422 / V.11
RS-423 / V.10
RS-232 / V.28
General Standards Corporation
8302A Whitesburg Drive
Huntsville,AL35802
Phone: [phone]
Fax: [phone]
URL: www.generalstandards.com
E-mail: techsup[email protected] Rev 0

PREFACE
Revision History
1. Rev 0 –May 2014 –Original rev from PMC-SIO4BX manual.
Additional copies of this manual or other General Standards Corporation literature may be obtained
from:
General Standards Corporation
8302A Whitesburg Drive
Huntsville, Alabama 35802
Telephone: [phone]
Fax: [phone]
URL: www.generalstandards.com
The information in this document is subject to change without notice.
General Standards Corporation makes no warranty of any kind with regard to this material, including,
but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Although
extensive editing and reviews are performed before release to ECO control, General Standards
Corporation assumes no responsibility for any errors that may exist in this document. No commitment is
made to update or keep current the information contained in this document.
General Standards Corporation does not assume any liability arising out of the application or use of any
product or circuit described herein, nor is any license conveyed under any patent right of any rights of
others.
General Standards Corporation assumes no responsibility resulting from omissions or errors in this
manual, or from the use of information contained herein.
General Standards Corporation reserves the right to make any changes, without notice, to this product
to improve reliability, performance, function, or design.
All rights reserved
No parts of this document may be copied or reproduced in any form or by any means without prior written
consent of General Standards Corporation.
Copyright © 2014 General Standards Corporation

RELATED PUBLICATIONS
ZILOG Z16C30 USC® User’s Manual
ZILOG Z16C30 USC® Product Specifications Databook
ZILOG, Inc.
210 East Hacienda Ave.
Campbell, CA 95008-6600
[phone]
http://www.zilog.com/
PLX PCI 9080 Data Book
PLX Technology Inc.
390 Potrero Avenue
Sunnyvale, CA 4085
[phone]
http://www.plxtech.com/
EIA-422-A –Electrical Characteristics of Balanced Voltage Digital Interface Circuits
(EIA order number EIA-RS-422A)
EIA-485 –Standard for Electrical Characteristics of Generators and Receivers for Use in Balanced Digital
Multipoint Systems
(EIA order number EIA-RS-485)
EIA Standards and Publications can be purchased from:
GLOBAL ENGINEERING DOCUMENTS
15 Inverness Way East
Englewood, CO 80112
Phone: [phone]
http://global.ihs.com/
PCI Local Bus Specification Revision 2.1 June 1, 1995.
Copies of PCI specifications available from:
PCI Special Interest Group
NE 2575 Kathryn Street, #17
Hillsboro, OR 97124
http://www.pcisig.com/

TABLE OF CONTENTS
CHAPTER 1: INTRODUCTION..............................................................................................................................1
1.0 GENERAL DESCRIPTION..................................................................................................................................1
1.1 PMC/PCI INTERFACE.....................................................................................................................................2
1.2 LOCAL CONTROL LOGIC.................................................................................................................................2
1.3 TRANSMIT/RECEIVE FIFOS............................................................................................................................2
1.4 UNIVERSAL SERIAL CONTROLLERS ................................................................................................................2
1.5 MULTIPROTOCOL TRANSCEIVERS...................................................................................................................2
1.6 GENERAL PURPOSE IO ...................................................................................................................................2
1.7 CONNECTOR INTERFACE ................................................................................................................................2
CHAPTER 2: LOCAL SPACE REGISTERS..........................................................................................................3
2.0 REGISTER MAP...............................................................................................................................................3
2.1 GSC FIRMWARE REGISTERS...........................................................................................................................4
2.1.1 FIRMWARE REVISION:LOCAL OFFSET 0X0000..............................................................................................5
2.1.2 BOARD CONTROL:LOCAL OFFSET 0X0004....................................................................................................5
2.1.3 BOARD STATUS:LOCAL OFFSET 0X0008........................................................................................................6
2.1.5 CHANNEL TX ALMOST FLAGS:LOCAL OFFSET 0X0010 /0X0020 /0X0030 /0X0040.....................................6
2.1.6 CHANNEL RX ALMOST FLAGS:LOCAL OFFSET 0X0014 /0X0024 /0X0034 /0X0044.....................................6
2.1.7 CHANNEL FIFO: LOCAL OFFSET 0X0018 /0X0028 /0X0038 /0X0048 ..........................................................6
2.1.8 CHANNEL CONTROL/STATUS:LOCAL OFFSET 0X001C /0X002C /0X003C /0X004C....................................7
2.1.9 CHANNEL SYNC DETECT BYTE:LOCAL OFFSET 0X0050 /0X0054 /0X0058 /0X005C..................................7
2.1.10 INTERRUPT REGISTERS...................................................................................................................................8
2.1.10.1 INTERRUPT CONTROL:LOCAL OFFSET 0X0060 ......................................................................................9
2.1.10.2 INTERRUPT STATUS/CLEAR:LOCAL OFFSET 0X0064..............................................................................9
2.1.10.3 INTERRUPT EDGE/LEVEL &INTERRUPT HI/LO:LOCAL OFFSET 0X0068 /0X006C.................................9
2.1.11 CHANNEL PIN SOURCE:LOCAL OFFSET 0X0080 /0X0084 /0X0088 /0X008C............................................10
2.1.12 CHANNEL PIN STATUS:LOCAL OFFSET 0X0090 /0X0094 /0X0098 /0X009C.............................................13
2.1.13 PROGRAMMABLE CLOCK REGISTERS:LOCAL OFFSET 0X00A0 /0X00A4 /0X00A8....................................14
2.1.14 FIFO COUNT REGISTER:LOCAL OFFSET 0X00D0 /0X00D4 /0X00D8 /0X00DC .......................................14
2.1.15 FIFO SIZE REGISTER:LOCAL OFFSET 0X00E0 /0X00E4 /0X00E8 /0X00EC .............................................14
2.1.16 FEATURES REGISTER:LOCAL OFFSET 0X00FC............................................................................................14
2.2 UNIVERSAL SERIAL CONTROLLER REGISTERS ..............................................................................................15
2.2.1 USC RESET ..................................................................................................................................................15
2.2.2 8-BIT USC REGISTER ACCESS......................................................................................................................15
2.2.3 USC DATA TRANSFER..................................................................................................................................15
2.2.4 USC REGISTER MEMORY MAP.....................................................................................................................16
CHAPTER 3: PROGRAMMING...........................................................................................................................17
3.0 INTRODUCTION.............................................................................................................................................17
3.1 RESETS.........................................................................................................................................................17
3.2 FIFO ALMOST FLAGS...................................................................................................................................17
3.3 PCI DMA.....................................................................................................................................................18
3.4 INTERRUPTS .................................................................................................................................................18
3.5 CLOCK SETUP...............................................................................................................................................19
3.6 PROGRAMMABLE OSCILLATOR /PROGRAMMABLE CLOCKS .........................................................................20
3.7 MULTIPROTOCOL TRANSCEIVER CONTROL ..................................................................................................21
3.8 DCE/DTE MODE .........................................................................................................................................21
3.9 GENERAL PURPOSE IO .................................................................................................................................21
CHAPTER 4: PCI INTERFACE ............................................................................................................................22
4.0 PCI INTERFACE REGISTERS ..........................................................................................................................22
4.1 PCI REGISTERS.............................................................................................................................................22

4.1.1 PCI CONFIGURATION REGISTERS..................................................................................................................22
4.1.2 LOCAL CONFIGURATION REGISTERS.............................................................................................................23
4.1.3 RUNTIME REGISTERS....................................................................................................................................23
4.1.4 DMA REGISTERS..........................................................................................................................................23
4.1.4.1 DMA CHANNEL MODE REGISTER:(PCI 0X80 /0X94) .................................................................................23
CHAPTER 5: HARDWARE CONFIGURATION................................................................................................24
5.0 BOARD LAYOUT...........................................................................................................................................24
5.1 BOARD ID JUMPER <JP1>............................................................................................................................25
5.2 PC104P /PCI104 SLOT SELECT SWITCH <U4>............................................................................................25
CHAPTER 6: ORDERING OPTIONS...................................................................................................................27
6.0 ORDERING INFORMATION.............................................................................................................................27
6.1 INTERFACE CABLE........................................................................................................................................27
6.2 DEVICE DRIVERS..........................................................................................................................................27
6.3 CUSTOM APPLICATIONS................................................................................................................................27
APPENDIX A: PROGRAMMABLE OSCILLATOR PROGRAMMING .........................................................28
APPENDIX B: FIRMWARE REVISIONS / FEATURES REGISTER ..............................................................31

PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: [phone]
CHAPTER 1: INTRODUCTION
1.0 General Description
The PC104P-SI04BX/PCI104-SIO4BX board is a four channel serial interface card which provides high speed, full-
duplex, multi-protocol serial capability for PC104P applications. The SIO4BX combines two multi-protocol Dual
Universal Serial Controllers (USC®), 8 external FIFOs, and multiprotocol transceivers to provide four fully
independent synchronous/asynchronous serial channels. These features, along with a high performance PCI interface
engine, give the PC104P-SIO4BX unsurpassed performance in a serial interface card.
P
C
1
0
4
P
/
P
C
I
1
0
4
PCI
Bridge
Control
Logic
Tx
FIFO
Universal
Serial
Controller
Rx
FIFO
Prog
Osc
DTE
DCE
Multiprotocol
Transceiver
68 Pin
User
(Cable
IF)
x4 Channels
Receiver
Transmitter
Figure 1-1 Block Diagram of PC104P-SIO4BX / PCI104-SIO4BX
Four Independent Multi-Protocol Serial Channels
Synchronous Serial Data Rates up to 10 Mbps
Asynchronous Serial Data Rates up to 1.25 Mbps
Independent Transmit and Receive FIFOs for each Serial Channel –Up to 32k Deep Each
Serial Mode Protocols include Asynchronous, MonoSync, BiSync, SDLC, and HDLC
Multiprotocol Transceivers support RS422 (V.11)/RS485, RS423 (V.10), RS232 (V.28), and V.35 Modes
Parity and CRC detection capability
On-Board Programmable Oscillators provide increased flexibility for exact Baud Rate Clock generation
SCSI II type 68 pin front edge I/O Connector with optional cable adapter to four DB25 connectors.
Six signals per channel, configurable as either DTE or DCE configuration: 2 Serial Clocks, 2 Serial Data
signals, Clear-To-Send (CTS), and Ready-To-Send (RTS).
Unused signals may be reconfigured as general purpose IO.
Fast RS422/RS485 Differential Cable Transceivers Provide Data Rate up to 10Mbps
RS423 and RS232 Cable Transceivers Provide Data Rate up to 230kbps
Industry Standard Zilog Z16C30 Multi-Protocol Universal Serial Controllers (USC®)
Dual PCI DMA Engine to speed transfers and minimize host I/O overhead
A variety of device drivers are available, including VxWorks, WinNT, Win2k, WinXP, Linux, and Labview
PCI104 form factor available

PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: [phone]
1.1 PMC/PCI Interface
The control interface to the SIO4BX is through the PMC/PCI interface. An industry standard PCI9080 bridge chip
from PLX Technology is used to implement PCI Specification 2.1. The PCI9080 provides the 32bit, 33MHz
(132Mbps) interface between the PCI bus and the Local 32 bit bus.
1.2 Local Control Logic
The control functions and glue logic for the board are implemented in an on-board FPGA. This custom logic defines
local space registers to provide software control over the board functions. The on-board logic adds many custom
features to compliment the Serial Controller chips. These functions include programmable oscillator setup, GPIO
functionality, transfer of data between the serial controller chips and the large external FIFOs, and functions to
simplify data transfer to/from the FIFOs.
1.3 Transmit/Receive FIFOs
Eight independent Transmit and Receive FIFOs provide up to 32kbytes of data buffering per channel for the serial
data. Each channel has a unique transmit and receive FIFO to allow the channels to operate independently. The
large FIFOs allow data transfer to continue independent of PCI interface transfers and software overhead. The
required FIFO size may depend on several factors including data transfer size, required throughput rate, and the
software overhead (which will also vary based on OS). Deep FIFOs ensure no data is lost for critical systems.
1.4 Universal Serial Controllers
Two Zilog Z16C30 Universal Serial Controllers provide the four serial data channels. The Z16C30 USCs serve as
serial/parallel converters which can be software configured to provide a variety of serial protocols. The USCs are
highly configurable to allow for a wide range of serial solutions.
1.5 Multiprotocol Transceivers
Data is transferred over the user interface using high-speed multiprotocol transceivers. These multiprotocol
transceivers can be configured as RS422/RS485, RS423, RS232, RS530, V.35, or RS422/RS423 mixed mode on a
per channel basis. Each channel may also be configured as DTE or DCE configuration.
1.6 General Purpose IO
Since some signals may not be used in all applications, the SIO4B provides the flexibility to remap unused signals to
be used as general purpose IO. For example, this would allow support for an application requiring DTR/DSR signals
to be implemented on an unused DCD or AuxC signals. This also allows signals from unused channels to be
available as general purpose IO.
1.7 Connector Interface
The SIO4BX provides a user IO interface through a front-side card edge connector. All four serial channels
interface through this high-density, 68 pin SCSI II type connector. Signals are grouped at the connector to simplify
separating the cable into four distinct serial connectors.
Standard cables are available from General Standards in various lengths to adapt the single 68 pin SCSII connector
into four DB25 connectors (one per channel). A standard cable is also available with a single 68 pin SCSII
connector on one end and open on the other. This allows the user to add a custom connector (or connect to a
terminal block). General Standards will also work with customers to fabricate custom cables. Consult factory for
details on custom cables.

PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: [phone]
CHAPTER 2: LOCAL SPACE REGISTERS
2.0 Register Map
The SIO4BX is accessed through three sets of registers –PCI Registers, USC Registers, and GSC Firmware
Registers. The GSC Firmware Registers and USC Registers are referred to as Local Space Registers and are
described below. The PCI registers are discussed in Chapter 3.
The Local Space Registers are divided into two distinct functional register blocks –the GSC Firmware Registers and
the USC Registers. The GSC Firmware Registers perform the custom board control functions, while the USC
Registers map the Zilog Z16C30 registers into local address space. The register block for each USC channel is
accessed at a unique address range. The table below shows the address mapping for the local space registers.
Local Address Range
Base Address Offset
Register Block Description
0x0000 –0x00FF
0x0000
GSC Firmware Registers
0x0100 –0x013F
0x0100
Channel 1 USC Registers
0x0140 –0x01FF
Reserved
0x0200 –0x023F
0x0200
Channel 2 USC Registers
0x0240 –0x02FF
Reserved
0x0300 –0x033F
0x0300
Channel 3 USC Registers
0x0340 –0x03FF
Reserved
0x0400 –0x043F
0x0400
Channel 4 USC Registers
The GSC Firmware Registers are detailed in Section 2.1. The USC Registers are briefly touched on in Section 2.2 of
this manual, but are described in much greater detail in the Zilog Z16C30 Users Manuals.

PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: [phone]
2.1 GSC Firmware Registers
The GSC Firmware Registers provide the primary control/status for the SIO4B board.
Offset Address
Size
Access*
Register Name
Default Value (Hex)
0x0000
D32
Read/Write
Firmware Revision
C41101XX
0x0004
D32
Read/Write
Board Control
00000000
0x0008
D32
Read Only
Board Status
000000XX
0x000C
D32
Read/Write
Clock Control
00000000
0x0010
D32
Read/Write
Ch 1 Tx Almost Full/Empty
00070007
0x0014
D32
Read/Write
Ch 1 Rx Almost Full/Empty
00070007
0x0018
D32
Read/Write
Ch l 1 Data FIFO
000000XX
0x001C
D32
Read/Write
Ch 1 Control/Status
0000CC00
0x0020
D32
Read/Write
Ch 2 Tx Almost Full/Empty
00070007
0x0024
D32
Read/Write
Ch 2 Rx Almost Full/Empty
00070007
0x0028
D32
Read/Write
Ch 2 Data FIFO
000000XX
0x002C
D32
Read/Write
Ch 2 Control/Status
0000CC00
0x0030
D32
Read/Write
Ch 3 Tx Almost Full/Empty
00070007
0x0034
D32
Read/Write
Ch 3 Rx Almost Full/Empty
00070007
0x0038
D32
Read/Write
Ch 3 Data FIFO
000000XX
0x003C
D32
Read/Write
Ch 3 Control/Status
0000CC00
0x0040
D32
Read/Write
Ch 4 Tx Almost Full/Empty
00070007
0x0044
D32
Read/Write
Ch 4 Rx Almost Full/Empty
00070007
0x0048
D32
Read/Write
Ch 4 Data FIFO
000000XX
0x004C
D32
Read/Write
Ch 4 Control/Status
0000CC00
0x0050
D32
Read/Write
Ch 1 Sync Byte
00000000
0x0054
D32
Read/Write
Ch 2 Sync Byte
00000000
0x0058
D32
Read/Write
Ch 3 Sync Byte
00000000
0x005C
D32
Read/Write
Ch 4 Sync Byte
00000000
0x0060
D32
Read/Write
Interrupt Control
00000000
0x0064
D32
Read/Write
Interrupt Status
00000000
0x0068
D32
Read Only
Interrupt Edge/Level
FFFF7777
0x006C
D32
Read/Write
Interrupt High/Low
FFFFFFFF
0x0070-0x007C
---
--
RESERVED
--------
0x0080
D32
Read/Write
Ch 1Pin Source
00000020
0x0084
D32
Read/Write
Ch 2 Pin Source
00000020
0x0088
D32
Read/Write
Ch 3 Pin Source
00000020
0x008C
D32
Read/Write
Ch 4 Pin Source
00000020
0x0090
D32
Read Only
Ch 1Pin Status
000000XX
0x0094
D32
Read Only
Ch 2 Pin Status
000000XX
0x0098
D32
Read Only
Ch 3 Pin Status
000000XX
0x009C
D32
Read Only
Ch 4 Pin Status
000000XX
0x00A0
D32
Read/Write
Programmable Osc RAM Addr
00000000
0x00A4
D32
Read/Write
Programmable Osc RAM Data
00000000
0x00A8
D32
Read/Write
Programmable Osc Control/Status
00000000
0x00AC-0x00CC
---
--
RESERVED
--------
0x00D0
D32
Read Only
Ch1 FIFO Count
00000000
0x00D4
D32
Read Only
Ch2 FIFO Count
00000000
0x00D8
D32
Read Only
Ch3 FIFO Count
00000000
0x00DC
D32
Read Only
Ch4 FIFO Count
00000000
0x00E0
D32
Read Only
Ch1 FIFO Size
XXXXXXXX
0x00E4
D32
Read Only
Ch2 FIFO Size
XXXXXXXX
0x00E8
D32
Read Only
Ch3 FIFO Size
XXXXXXXX
0x00EC
D32
Read Only
Ch4 FIFO Size
XXXXXXXX
0x00F0-0x00F8
---
--
RESERVED
--------
0x00FC
D32
Read Only
Features Register
000000XX

PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: [phone]
2.1.1 Firmware Revision: Local Offset 0x0000
The Firmware ID register provides version information about the firmware on the board. This is useful for technical
support to identify the firmware version.
D31:16 HW Board Rev C411 = PC104P-SIO4BX Rev A
D15:8 Firmware Type ID 01 = SIO4B Standard
D7:0 Firmware Revision Firmware Version
2.1.2 Board Control: Local Offset 0x0004
The Board Control Register defines the general control functions for the board. The main function in this register
defines the Demand mode DMA channel requests. For Demand mode DMA, there are only two physical DMA
channels which must be shared between the eight serial channels (Rx and Tx for each of four channels). The
Demand Mode DMA Channel Request allows the software to multiplex the DMA channels. This is typically
handled by the driver –the end user should have no need to change this register.
D31 Board Reset
1 = Reset all Local registers, FIFOs, and USC to their default values
Notes: This bit will automatically clear to 0 following the board reset.
The USCs will need to be reinitialized following a Board Reset.
D30:D9 RESERVED
D8 Rx FIFO Stop on Full
1 = If Rx FIFO becomes full, stop receiving data (disable receiver).
D7 Demand Mode DMA Channel 1 Single Cycle Disable
D6:4 Demand Mode DMA Channel 1 Request
D6
D5
D4
Demand Mode DMA 1 Channel
0
0
0
Channel 1 Rx
1
0
0
Channel 1 Tx
0
1
0
Channel 2 Rx
1
1
0
Channel 2 Tx
0
0
1
Channel 3 Rx
1
0
1
Channel 3 Tx
0
1
1
Channel 4 Rx
1
1
1
Channel 4 Tx
D3 Demand Mode DMA Channel 0 Single Cycle Disable
D2:0 Demand Mode DMA Channel 0 Request
D2
D1
D0
Demand Mode DMA 0 Channel
0
0
0
Channel 1 Rx
1
0
0
Channel 1 Tx
0
1
0
Channel 2 Rx
1
1
0
Channel 2 Tx
0
0
1
Channel 3 Rx
1
0
1
Channel 3 Tx
0
1
1
Channel 4 Rx
1
1
1
Channel 4 Tx

PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: [phone]
2.1.3 Board Status: Local Offset 0x0008
The Board Status Register gives general overall status for a board. The Board Jumpers are physical jumpers which
can be used to distinguish between boards if multiple SIO4 boards are present in a system.
D31 Board Reset In Progress
D30:D16 RESERVED
D15 External Ch4 Rx FIFO Not Present
D14 External Ch4 Tx FIFO Not Present
D13 External Ch3 Rx FIFO Not Present
D12 External Ch3 Tx FIFO Not Present
D11 External Ch2 Rx FIFO Not Present
D10 External Ch2 Tx FIFO Not Present
D9 External Ch1 Rx FIFO Not Present
D8 External Ch1 Tx FIFO Not Present
D7:D2 RESERVED
D1 Board Jumper 1
0 = Jumper J5:3-4 installed
D0 Board Jumper 0
0 = Jumper J5:1-2 installed
2.1.5 Channel Tx Almost Flags: Local Offset 0x0010 / 0x0020 / 0x0030 / 0x0040
The Tx Almost Flag Registers are used to set the Almost Full and Almost Empty Flags for the transmit FIFOs. The
FIFO almost flags may be used to determine a fill level for a specific transfer size.
D31:16 Tx Almost Full Flag Value
Almost Full Flag will be asserted when the FIFO has space for “Almost Full Value”
words or fewer (i.e. FIFO contains (FIFO Size –Almost Full Value) words or more.)
D15:0Tx Almost Empty Flag Value
Almost Empty Flag will be asserted when the FIFO contains “Almost Empty Value”
words or fewer.
2.1.6 Channel Rx Almost Flags: Local Offset 0x0014 / 0x0024 / 0x0034 / 0x0044
The Rx Almost Flag Registers are used to set the Almost Full and Almost Empty Flags for the receive FIFOs. The
FIFO almost flags may be used to determine a fill level for a specific transfer size.
D31:16 Rx Almost Full Flag Value
Almost Full Flag will be asserted when the FIFO has space for “Almost Full Value”
words or fewer (i.e. FIFO contains (FIFO Size –Almost Full Value) words or more.)
D15:0 Rx Almost Empty Flag Value
Almost Empty Flag will be asserted when the FIFO contains “Almost Empty Value”
words or fewer.
2.1.7 Channel FIFO: Local Offset 0x0018 / 0x0028 / 0x0038 / 0x0048
The Channel FIFO Register passes serial data to/from the serial controller chips. The same register is used to access
both the Transmit FIFO (writes) and Receive FIFO (reads).
D31:8 RESERVED
D7:0 Channel FIFO Data

PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: [phone]
2.1.8 Channel Control/Status: Local Offset 0x001C / 0x002C / 0x003C / 0x004C
The Channel Control/Status Register provides the reset functions and data transceiver enable controls, and the FIFO
Flag status for each channel.
D31:16 RESERVED
D15:8 Channel Status Bits
D15 Channel Rx FIFO Full Flag Lo (Active Low -- 0=Rx Full)
D14 Channel Rx FIFO Almost Full Flag Lo (Active Low -- 0=Rx Almost Full)
D13 Channel Rx FIFO Almost Empty Flag Lo (Active Low -- 0=Rx Almost Empty)
D12 Channel Rx FIFO Empty Flag Lo (Active Low -- 0=Rx Empty)
D11 Channel Tx FIFO Full Flag Lo (Active Low -- 0=Tx Full)
D10 Channel Tx FIFO Almost Full Flag Lo (Active Low -- 0=Tx Almost Full)
D9 Channel Tx FIFO Almost Empty Flag Lo (Active Low -- 0=Tx Almost Empty)
D8 Channel Tx FIFO Empty Flag Lo (Active Low -- 0=Tx Empty)
D7:0 Channel Control Bits
D7 Reset USC (Pulsed)
‘1’ = Reset USC chip
Notes:
This value will automatically clear to ‘0’.
Following a USC Reset, the next access to the USC must be a write of 0x00 to Local
Offset 0x100 (Ch1/2) or Local Offset 0x300 (Ch3/4).
Since two channels share each USC (Ch1 & Ch2, Ch3 & Ch4), resetting a USC will
affect both channels.
D6:2 RESERVED
D1 Reset Channel Rx FIFO (Pulsed)
1 = Reset/Clear Channel Rx FIFOs.
Note: This value will automatically clear to ‘0’.
D0 Reset Channel Tx FIFO (Pulsed)
1 = Reset/Clear Channel Tx FIFOs.
Note: This value will automatically clear to ‘0’.
2.1.9 Channel Sync Detect Byte: Local Offset 0x0050 / 0x0054 / 0x0058 / 0x005C
The Sync Detect Byte allows an interrupt to be generated when the received data matches the Sync Detect Byte.
D31:8 RESERVED
D7:0Channel Sync Detect Byte
If the data being loaded into the Receive FIFO matches this data byte, an interrupt
request (Channel Sync Detect IRQ) will be generated. The interrupt source must be
enabled in the Interrupt Control Register in order for an interrupt to be generated.

PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: [phone]
2.1.10 Interrupt Registers
There are 32 on-board interrupt sources (in addition to USC interrupts and PLX interrupts) which may be
individually enabled. Four interrupt registers control the on-board interrupts –Interrupt Control, Interrupt Status,
Interrupt Edge/Level, and Interrupt Hi/Lo. The 32 Interrupt sources are:
IRQ #
Source
Default Level
Alternate Level
IRQ0
Channel 1 Sync Detected
Rising Edge
NONE
IRQ1
Channel 1 Tx FIFO Almost Empty
Rising Edge
Falling Edge
IRQ2
Channel 1 Rx FIFO Almost Full
Rising Edge
Falling Edge
IRQ3
Channel 1 USC Interrupt
Level Hi
NONE
IRQ4
Channel 2 Sync Detected
Rising Edge
NONE
IRQ5
Channel 2 Tx FIFO Almost Empty
Rising Edge
Falling Edge
IRQ6
Channel 2 Rx FIFO Almost Full
Rising Edge
Falling Edge
IRQ7
Channel 2 USC Interrupt
Level Hi
NONE
IRQ8
Channel 3 Sync Detected
Rising Edge
NONE
IRQ9
Channel 3 Tx FIFO Almost Empty
Rising Edge
Falling Edge
IRQ10
Channel 3 Rx FIFO Almost Full
Rising Edge
Falling Edge
IRQ11
Channel 3 USC Interrupt
Level Hi
NONE
IRQ12
Channel 4 Sync Detected
Rising Edge
NONE
IRQ13
Channel 4 Tx FIFO Almost Empty
Rising Edge
Falling Edge
IRQ14
Channel 4 Rx FIFO Almost Full
Rising Edge
Falling Edge
IRQ15
Channel 4 USC Interrupt
Level Hi
NONE
IRQ16
Channel 1 Tx FIFO Empty
Rising Edge
Falling Edge
IRQ17
Channel 1 Tx FIFO Full
Rising Edge
Falling Edge
IRQ18
Channel 1 Rx FIFO Empty
Rising Edge
Falling Edge
IRQ19
Channel 1 Rx FIFO Full
Rising Edge
Falling Edge
IRQ20
Channel 2 Tx FIFO Empty
Rising Edge
Falling Edge
IRQ21
Channel 2 Tx FIFO Full
Rising Edge
Falling Edge
IRQ22
Channel 2 Rx FIFO Empty
Rising Edge
Falling Edge
IRQ23
Channel 2 Rx FIFO Full
Rising Edge
Falling Edge
IRQ24
Channel 3 Tx FIFO Empty
Rising Edge
Falling Edge
IRQ25
Channel 3 Tx FIFO Full
Rising Edge
Falling Edge
IRQ26
Channel 3 Rx FIFO Empty
Rising Edge
Falling Edge
IRQ27
Channel 3 Rx FIFO Full
Rising Edge
Falling Edge
IRQ28
Channel 4 Tx FIFO Empty
Rising Edge
Falling Edge
IRQ29
Channel 4 Tx FIFO Full
Rising Edge
Falling Edge
IRQ30
Channel 4 Rx FIFO Empty
Rising Edge
Falling Edge
IRQ31
Channel 4 Rx FIFO Full
Rising Edge
Falling Edge
For all interrupt registers, the IRQ source (IRQ31:IRQ0) will correspond to the respective data bit (D31:D0) of each
register. (D0 = IRQ0, D1 = IRQ1, etc.)
All FIFO interrupts are edge triggered active high. This means that an interrupt will be asserted (assuming it is
enabled) when a FIFO Flag transitions from FALSE to TRUE (rising edge triggered) or TRUE to FALSE (falling
edge). For example: If Tx FIFO Empty Interrupt is set for Rising Edge Triggered, the interrupt will occur when the
FIFO transitions from NOT EMPTY to EMPTY. Likewise, if Tx FIFO Empty Interrupt is set as Falling Edge
Triggered, the interrupt will occur when the FIFO transitions from EMPTY to NOT EMPTY.
All Interrupt Sources share a single interrupt request back to the PCI9080 PLX chip. Likewise, all USC interrupt
sources share a single interrupt request back to the interrupt controller and must be further qualified in the USC chip.
See Section 3.4 Interrupts for further interrupt programming information.

PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: [phone]
2.1.10.1 Interrupt Control: Local Offset 0x0060
The Interrupt Control register individually enables each interrupt source. A ‘1’ enables each interrupt source; a ‘0’
disables. An interrupt source must be enabled for an interrupt to be generated.
2.1.10.2 Interrupt Status/Clear: Local Offset 0x0064
The Interrupt Status Register shows the status of each respective interrupt source. If an interrupt source is enabled in
the Interrupt Control Register, a ‘1’ in the Interrupt Status Register indicates the respective interrupt has occurred.
The interrupt source will remain latched until the interrupt is cleared, either by writing to the Interrupt Status/Clear
Register with a ‘1’ in the respective interrupt bit position, or the interrupt is disabled in the Interrupt Control register.
If an interrupt source is not asserted or the interrupt is not enabled, writing a ‘1’ to that bit in the Interrupt
Status/Clear Register will have no effect on the interrupt.
If the interrupt source is a level triggered interrupt (USC interrupt), the interrupt status may still be ‘1’ even if the
interrupt is disabled. This indicates the interrupt condition is true, regardless of whether the interrupt is enabled.
Likewise, if a level interrupt is enabled and the interrupt source is true, the interrupt status will be reasserted
immediately after clearing the interrupt, and an additional interrupt will be requested.
2.1.10.3 Interrupt Edge/Level & Interrupt Hi/Lo: Local Offset 0x0068 / 0x006C
The Interrupt Edge/Level and Interrupt Hi/Lo Registers define each interrupt source as level hi, level lo, rising edge,
or falling edge. All SIO4BX interrupts are edge triggered except the USC interrupts which are level triggered.
Since the interrupt behavior is fixed, the Interrupt Edge/Level register cannot be changed by the user. (Read Only)
The FIFO Flags may be defined as rising edge or falling edge via the Interrupt Hi/Lo Register. For example, a rising
edge of the Tx Empty source will generate an interrupt when the Tx FIFO becomes empty. Defining the source as
falling edge will trigger an interrupt when the Tx FIFO becomes “NOT Empty”.

PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: [phone]
2.1.11 Channel Pin Source: Local Offset 0x0080 / 0x0084 / 0x0088 / 0x008C
The Channel Pin Source Register configures the Output source for the Clocks, Data, RTS, and DCD outputs.
31
30
29
28
27
26
25
24
DCE/DTE
Mode Enable
Termination
Disable
Loopback
Enable
DCE/DTE
Mode
Transceiver Protocol Mode
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Loop
Int
Unused
TxD
Source
TxAuxC
Source
DCD
Source
RTS
Source
USC_DCD
Direction
USC_CTS
Direction
TxC
Source
USC_RxC
Source
USC_TxC
Source
Pin Source Register
D31 DCE/DTE Mode Enable
Setting this bit enables the DCE/DTE buffer control (D28) control and Loopback controls (D29
and D23). See Transceiver control for further information.
D30 Termination Disable
For RS422/RS485 and V.35, the RxC, RxAuxC, and RxD have built in termination at the
transceivers. These internal terminations may be disabled to allow external terminations to be
used. Setting this bit will disable the internal transceiver termination resistors.
D29 External Loopback Mode
When DCE/DTE Mode is enabled (Bit D31=1), this bit will automatically loopback the TxC/RxC,
TxD/RxD, and RTS/CTS signals at the cable (transceivers enabled).
Notes:
The DCE/DTE mode will select the set of signals (DCE or DTE) to be looped back
D28 DCE/DTE Mode
When DCE/DTE Mode is enabled (Bit D31=1), this bit set the mode to DCE (1) or DTE (0).
DCE/DTE mode changes the direction of the signals at the IO Connector.
D27:24 Transceiver Protocol Mode
D27
D26
D25
D24
Transceiver Mode
0
0
0
0
RS-422 / RS-485
0
0
0
1
RS-423
0
0
1
0
RS-232
0
0
1
1
RESERVED
0
1
0
X
RESERVED
0
1
1
0
V.35 Mode (V.35 / RS-232)
0
1
1
1
RESERVED
1
X
X
X
RESERVED

PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: [phone]
D23 Internal Loopback Mode
When DCE/DTE Mode is enabled (Bit D31=1), this bit will automatically loopback the TxC/RxC,
TxD/RxD, and RTS/CTS signals internal to the board.
D22:21 RESERVED
D20:19 Cable TxD Output Control
Allows TxD output to be used as a general purpose output.
D20
D19
TxD Source
0
X
USC_TxD
1
0
Output ‘0’
1
1
Output ‘1’
D18:17 Cable TxAuxC Output Control
Defines the Clock Source for the TxAuxC signal to the IO connector.
D18
D17
TxD Source
0
0
Tristate
0
1
On-board Programmable Clock
1
0
Output ‘0’
1
1
Output ‘1’
D16:15 Cable DCD Output Source
D16
D15
Output Source
Notes
0
0
USC_DCD Output
USC_DCD field (D12:D11) must equal ‘11’
0
1
RTS Output
Rx FIFO Almost Full
1
0
‘0’
Drive low
1
1
‘1’
Drive Hi
D14:13 Cable RTS Output Source
D14
D13
Output Source
Notes
0
0
USC_CTS Output
USC_CTS field (D10:D9) must equal ‘11’
0
1
RTS Output
Rx FIFO Almost Full
1
0
‘0’
Drive low
1
1
‘1’
Drive Hi

PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: [phone]
D12:11 USC_DCD Direction Setup
Defines the DCD direction for the USC DCD pin.
Notes:
If DCD is used as GPIO, set this field to ‘00’ and set Pin Source Register
D16:D15 for output / Pin Status Register D3 for input.
If set, the DCD direction must agree with the USC DCD setup (USC IOCR
D13:12) to ensure proper operation.
If field set to ‘11’ (Output), DCD Source field (D16:15) must be set to ‘00’.
D12
D11
DCD Buffer Direction
USC IOCR D13:D12 Setup
0
0
Buffer Disabled
XX (Don’t Care)
0
1
Input from IO Connector - DCD
0X (Input)
1
0
Reserved
XX (Don’t Care)
1
1
Output to IO Connector
1X (Output)
D10:9 USC_CTS Direction Setup
Defines the CTS direction for the USC CTS pin.
Notes:
If CTS is used as GPIO, set this field to ‘00’ and set Pin Source Register
D14:D13 for output / Pin Status Register D2 for input.
If set, the CTS direction must agree with the USC CTS setup (USC IOCR
D15:14) to ensure proper operation.
If field set to ‘11’ (Output), RTS Source field (D14:13) must be set to ‘00’.
D10
D9
CTS Buffer Direction
USC IOCR D15:D14 Setup
0
0
Tristate
XX (Don’t Care)
0
1
Input from IO Connector –CTS
0X (Input)
1
0
Reserved
XX (Don’t Care)
1
1
Output to IO Connector
1X (Output)
D8:6 Cable TxC Source
Defines the Clock Source for the TxC signal to the IO connector.
D8
D7
D6
TxC Source
0
0
0
Prog Clock
0
0
1
Inverted Prog Clock
0
1
0
‘0’ (Drive Line Lo)
0
1
1
‘1’ (Drive Line Hi)
1
0
0
USC_TxC
1
0
1
USC_RxC
1
1
0
Cable RxC Input
1
1
1
Cable RxAuxC Input

PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: [phone]
D5:3 USC_RxC Source
Defines the Clock Source for the USC_RxC pin. The clock source must agree with the USC
Clock setup (USC I/O Control Reg D5:3) to ensure the signal is not being driven by both the
USC and the FPGA.
D5
D4
D3
USC_RxC Source
USC IOCR D2:D0 Setup
0
0
0
Prog Clock
000 (Input)
0
0
1
Inverted Prog Clock
000 (Input)
0
1
0
‘0’
000 (Input)
0
1
1
‘1’
000 (Input)
1
0
0
Cable RxC Input
000 (Input)
1
0
1
Cable RxAuxC Input
000 (Input)
1
1
0
RESERVED
--------
1
1
1
Driven from USC
IOCR D2:D0 != 000 (Output)
D2:0 USC_TxC Source
Defines the Clock Source for the USC_TxC pin. Since this signal is bidirectional (it may be
used as either an input or output to the USC), the clock source must agree with the USC Clock
setup (USC IO Control Reg D2:0) to ensure the signal is not being driven by both the USC
and the FPGA.
D2
D1
D0
USC_TxC Source
USC IOCR D5:D3 Setup
0
0
0
Prog Clock
000 (Input)
0
0
1
Inverted Prog Clock
000 (Input)
0
1
0
‘0’
000 (Input)
0
1
1
‘1’
000 (Input)
1
0
0
Cable RxC Input
000 (Input)
1
0
1
Cable RxAuxC Input
000 (Input)
1
1
0
RESERVED
--------
1
1
1
Driven from USC
IOCR D5:D3 != 000 (Output)
2.1.12 Channel Pin Status: Local Offset 0x0090 / 0x0094 / 0x0098 / 0x009C
Unused inputs may be utilized as general purpose input signals. The Channel Pin Status Register allows the input
state of all the IO pins to be monitored. Output signals as well as inputs are included to aid in debug operation.
D31:D10 RESERVED
D9 TxAuxC Output
D8 RxAuxC Input
D7 DCD Output
D6 RTS Output
D5 TxD Output
D4 TxC Output
D3 DCD Input
D2 CTS Input
D1 RxD Input
D0 RxC Input

PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: [phone]
2.1.13 Programmable Clock Registers: Local Offset 0x00A0 / 0x00A4 / 0x00A8
The Programmable Clock Registers allow the user to program the on-board programmable oscillator and configure
the channel clock post-dividers. As GSC should provide software routines to program the clock, the user should
have no need to access these registers. See section 3.6 for more information.
2.1.14 FIFO Count Register: Local Offset 0x00D0 / 0x00D4 / 0x00D8 / 0x00DC
The FIFO Count Registers display the current number of words in each FIFO. This value, along with the FIFO Size
Registers, may be used to determine the amount of data which can be safely transferred without over-running (or
under-running) the FIFOs.
D31:D16 Number of words in Rx FIFO
D15:D0 Number of words in Tx FIFO
2.1.15 FIFO Size Register: Local Offset 0x00E0 / 0x00E4 / 0x00E8 / 0x00EC
The FIFO Size Registers display the sizes of the installed data FIFOs. This value is calculated at power-up This
value, along with the FIFO Count Registers, may be used to determine the amount of data which can be safely
transferred without over-running (or under-running) the FIFOs.
D31:D16 Size of installed Rx FIFO
D15:D0 Size of installed Tx FIFO
2.1.16 Features Register: Local Offset 0x00FC
The Features Register allows software to account for added features in the firmware versions. Bits will be assigned
as new features are added.
D31:16 RESERVED
D15:8 Features Rev Level
01 –RS232 support, update Pin Source
02 –Multiprotocol support
03 –Common Internal/External FIFO code
04 –Latched FIFO Overrun/Underrun Level
05 –Demand mode DMA Single Cycle for Tx
06 - Single Cycle DMA disable, update Pin Source TxAuxC
07 - Rx Underrun Only, Reset Status
08 - Clock to 50Hz with 10Hz resolution
09 - No Legacy Support (No Clock Control Register)
0A - Falling Int fix
D7 Demand Mode DMA Single Cycle Disable feature implemented
D6 Board Reset feature implemented
D5 FIFO Counters/Size implemented
D4 ‘1’
D3:0 Programmable Clock Configuration
0x3 = CY22393 - 4 Oscillators (Sio4B/BX configuration)

PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: [phone]
2.2 Universal Serial Controller Registers
The internal registers of the Zilog Z16C30 Universal Serial Controller (USC) are memory mapped into Local
Address space. It is beyond the scope of this manual to provide comprehensive USC programming information.
For detailed programming information, please refer to the Zilog High Speed Communication Controller Product
Specifications Databook for the Z16C30 and the Zilog Z16C30USC User’s Manual.These manuals may be
obtained directly from Zilog (www.zilog.com), or copies of these manuals may be downloaded from the General
Standards website (www.generalstandards.com).
Some specific setup information may be needed for a driver to interface to the USC. Typically, the driver will
handle the hardware specific characteristics and the end user will only need to be concerned with the driver interface
- the following hardware setup information may be safely ignored. If you aren’t sure if you need this information,
you probably don’t.
2.2.1 USC Reset
The four serial channels are implemented in two Z16C30 Universal Serial Controllers –Channels 1 and 2 share one
USC, and Channels 3 and 4 share the other. This implementation is important to realize since resetting a Z16C30
chip will have an effect on two serial channels. Since the USC chips are typically reset upon initialization, this
means a “Reset USC” for Channel 1 will also “Reset USC” for Channel 2. In addition to making the second reset
redundant and unnecessary, a Reset USC on one channel may inadvertently adversely affect normal operation on the
second channel. Therefore, care must be exercised when resetting a USC (USC Reset bit in the Board Control
Register), especially in multithreaded environments.
Since the USC Reset physically resets the USC, the first access to the USC following the reset must reinitialize the
BCR in the USC. To complete the Reset process, the user should write data 0x00 to USC base address offset 0x100
or 0x300 to correctly initialize the BCR. Following this initial byte write, the USC may be accessed normally.
Due to the ability for a USC Reset to affect two channels, it is recommended that a single USC Channel be Reset via
the RTReset bit of the USC Channel Command/Address Register (CACR).
2.2.2 8-Bit USC RegisterAccess
As the USC has a configurable bus interface, the USC must be set to match the 8-bit non-multiplex interface
implementation of the SIO4BX. This setup information must be programmed into the USC Bus Configuration
Register (BCR) upon initial power up and following every hardware reset of the USC. The BCR is accessible only
following a USC hardware reset –the first write to the USC following a USC Reset programs the BCR. Even
though the Zilog manual states the BCR has no specific address, the driver must use the channel USC base address –
0x100 for Ch 1 & Ch 2, 0x300 for Ch 3 & Ch 4 –as the BCR address. Failure to do so may result in improper setup.
Since the user interface to the USC is an 8 bit interface, the software only needs to set the lower byte to 0x00
(hardware implementation will program the upper byte of the BCR).
2.2.3 USC Data Transfer
Although the Z16C30 USC contains 32 byte internal FIFOs for data transfer, these are typically not used on the
SIO4BX. Since the SIO4BX has much deeper external FIFOs (or internal FPGA FIFOs), the internal USC FIFOs
are setup to immediately transfer data to/from the external FIFOs. Immediate transfer of received data to the
external FIFOs eliminates the possibility of data becoming “stuck” in the USC internal receive FIFOs, while
bypassing the USC internal transmit FIFOs ensures better control of the transmit data.
In order to automatically transfer data to and from the external FIFOs, the USC should use DMA to request a data
transfer whenever one byte is available in the USC internal FIFOs. This “DMA” should not be confused with the
DMA of data from the SIO4BX external FIFOs to the PCI interface. To accomplish the USC-to-External FIFO