Goodix GR551 Series Instruction Manual

GR551x Hardware Design Guidelines
Version: 2.1
Release Date: 2021-06-15
Shenzhen Goodix Technology Co., Ltd.

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Disclaimer
Information contained in this document is intended for your convenience only and is subject to change without prior
notice. It is your responsibility to ensure its application complies with technical specifications.
Shenzhen Goodix Technology Co., Ltd. (hereafter referred to as “Goodix”) makes no representation or guarantee for
this information, express or implied, oral or written, statutory or otherwise, including but not limited to representation
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Preface
Preface
Purpose
This document is to present the necessary circuit required for proper operation of GR551x Bluetooth System-on-Chips
(SoCs). Recommended schematic, chip interfaces, peripherals, schematic diagram, and PCB layout guidelines of the
GR551x SoC family are provided.
This Hardware Design Guidelines intends to help system designers build minimal Bluetooth Low Energy (Bluetooth LE)
hardware circuits and develop products.
Audience
This document is intended for:
• GR551x user
• GR551x tester
• Bluetooth product engineer
• Bluetooth LE system designer
Release Notes
This document is the eighth release of GR551x Hardware Design Guidelines, corresponding to GR551x SoC series.
Revision History
Version Date Description
1.0 2019-12-08 Initial release
1.3 2020-03-16 Updated the package pinout diagrams to the top views in “Pinout”.
1.5 2020-05-30
•Updated chip model numbers and pinout diagrams, package size diagrams, and reference
schematic diagrams;
•Changed power supplies and RF and explained by taking a QFN56 circuit as an example;
•Added “PCB Layout Reference Design”; updated “ESD Considerations”.
1.6 2020-06-30
•Updated the package layouts and data in the Appendix;
•Changed the maximum supply voltage from 4.38 V to 3.8 V; changed I/O voltage from 3.6 V
to 3.3 V (typical value).
•Added “Solutions for Improving ESD Protection Level on Products” by introducing the
hardware watchdog timer; added “Two-layer PCBs in QFN56”.
1.7 2020-08-30
Introduced the GR5515I0ND SoC:
•Added “GR5515I0ND” for pinout details;
•Added “External Flash” to describe recommended external Flash for GR5515I0ND;
•Added the reference schematic for GR5515I0ND in “Reference Design”;
Copyright © 2021 Shenzhen Goodix Technology Co., Ltd. I

Preface
Version Date Description
•Added “For External Flash Connection on GR5515I0ND” as reference design.
1.8 2020-11-27 Polished descriptions in "GR551x Overview" and "Pinout".
1.9 2021-03-03
•Updated description on the TEST_MODE pin; introduced the number of I/O pins in “GR551x
Overview”;
•Added description on PWM configuration in "I/O Pins";
•Updated the recommended Flash models for GR5515I0ND in "External Flash";
•Updated description on I/O voltage of GR5515I0ND;
•Changed the previous “ESD Considerations” into “ESD Protection Design” and updated
contents in this section.
2.0 2021-04-29
•Updated description on I/O voltage of GR5515I0ND in “Power Supply” and “FAQ”.
•Updated descriptions in “Power Supply Scheme”, “Power Supply”, “Clock”, “ESD Schematic
Design”, “PCB Layout Design” and “Two-layer PCBs in QFN Packages”.
2.1 2021-06-15
Add a note of not recommended for new designs for GR5515RGBD.
Updated the recommended external flash models for GR5515I0ND.
Copyright © 2021 Shenzhen Goodix Technology Co., Ltd. II

Contents
Contents
Preface.................................................................................................................................................................... I
1 GR551x Overview................................................................................................................................................1
1.1 Features............................................................................................................................................................... 1
1.2 Block Diagram......................................................................................................................................................3
2 Pinout................................................................................................................................................................. 5
2.1 GR5515IGND QFN56............................................................................................................................................5
2.2 GR5515I0ND QFN56............................................................................................................................................ 8
2.3 GR5515RGBD BGA68 (NRND)............................................................................................................................12
2.4 GR5515GGBD BGA55.........................................................................................................................................15
2.5 GR5513BEND QFN40......................................................................................................................................... 18
3 Minimal Design for GR551x SoC........................................................................................................................22
3.1 Schematic Design Guideline.............................................................................................................................. 22
3.1.1 Power Supply............................................................................................................................................ 22
3.1.1.1 Introduction......................................................................................................................................22
3.1.1.2 Power Supply Scheme......................................................................................................................23
3.1.1.3 I/O LDO.............................................................................................................................................25
3.1.2 Clock..........................................................................................................................................................27
3.1.2.1 Introduction......................................................................................................................................27
3.1.2.2 32 MHz Clock (XO)........................................................................................................................... 27
3.1.2.3 32.768 kHz Clock..............................................................................................................................28
3.1.3 RF.............................................................................................................................................................. 29
3.1.3.1 Introduction......................................................................................................................................29
3.1.3.2 RF Scheme........................................................................................................................................29
3.1.4 I/O Pins..................................................................................................................................................... 30
3.1.5 SWD Interfaces..........................................................................................................................................30
3.1.6 External Flash............................................................................................................................................31
3.2 PCB Design and Layout Guideline..................................................................................................................... 31
3.2.1 PCB Layer Stackup.................................................................................................................................... 32
3.2.2 Components Layout.................................................................................................................................. 32
3.2.3 Power Supply............................................................................................................................................ 33
3.2.3.1 DC-DC Switching Regulator.............................................................................................................. 33
3.2.3.2 RF Input Power Supply.....................................................................................................................34
3.2.4 Clock..........................................................................................................................................................35
3.2.5 RFIO Port...................................................................................................................................................36
3.2.6 Grounding................................................................................................................................................. 37
3.2.7 ESD Protection Design.............................................................................................................................. 37
3.2.7.1 System-level ESD Design.................................................................................................................. 38
3.2.7.2 ESD Considerations in Production, Transport, and Debugging........................................................ 43
Copyright © 2021 Shenzhen Goodix Technology Co., Ltd. III

Contents
4 Reference Design...............................................................................................................................................44
4.1 Reference Schematic Diagram...........................................................................................................................44
4.2 PCB Layout Reference Design............................................................................................................................48
4.2.1 Four-layer PCBs in QFN56 Package...........................................................................................................48
4.2.2 Two-layer PCBs in QFN Packages..............................................................................................................51
4.2.3 External Flash Connection for GR5515I0ND.............................................................................................52
4.2.4 Four-layer PCBs in BGA68 Package(NRND)...............................................................................................53
5 FAQ................................................................................................................................................................... 56
5.1 Can the Voltages of All GR551x I/O Pins Be Set to 3.3 V?................................................................................56
5.2 Why Is the Power Consumption in GR551x Sleep Modes High?...................................................................... 56
5.3 Can the RF PI Circuits Be Simplified or Removed?........................................................................................... 57
6 Glossary and Abbreviations...............................................................................................................................58
7 Appendix: QFN and BGA Assembly Guideline................................................................................................... 59
7.1 Package Information..........................................................................................................................................60
7.1.1 GR5515IGND/GR5515I0ND QFN56........................................................................................................... 60
7.1.2 GR5515RGBD BGA68 (NRND)................................................................................................................... 62
7.1.3 GR5515GGBD BGA55................................................................................................................................ 64
7.1.4 GR5513BEND QFN40................................................................................................................................ 66
7.2 Board Mounting Guideline................................................................................................................................ 68
7.2.1 Stencil Design for Perimeter Pads............................................................................................................ 68
7.2.2 Via Types and Solder Voiding................................................................................................................... 69
7.2.2.1 Stencil Thickness and Solder Paste.................................................................................................. 69
7.2.2.2 PCB Materials................................................................................................................................... 69
7.2.3 SMT Printing Process................................................................................................................................ 70
7.3 SMT Reflow Process.......................................................................................................................................... 70
7.4 Rework Guideline.............................................................................................................................................. 72
7.4.1 Component Removal................................................................................................................................ 73
7.4.2 Site Redress...............................................................................................................................................73
7.4.3 Solder Paste Printing.................................................................................................................................73
7.4.4 Component Placement............................................................................................................................. 74
7.4.5 Component Attachment........................................................................................................................... 74
7.5 RoHS Compliant.................................................................................................................................................74
7.6 SVHC Materials (REACH)....................................................................................................................................74
7.7 Halogen Free......................................................................................................................................................74
Copyright © 2021 Shenzhen Goodix Technology Co., Ltd. IV

GR551x Overview
1 GR551x Overview
The Goodix GR551x family is a single-mode, low-power Bluetooth 5.1 System-on-Chip (SoC). It can be configured as a
Broadcaster, an Observer, a Central, or a Peripheral and supports the combination of all the above roles, making it an
ideal choice for Internet of Things (IoT) and smart wearable devices.
Based on ARM® Cortex®-M4F CPU core, the GR551x integrates Bluetooth 5.1 Protocol Stack, a 2.4 GHz RF transceiver,
on-chip programmable Flash memory, RAM, and multiple peripherals.
The GR551x series includes GR5515IGND, GR5515RGBD, GR5515GGBD, GR5513BEND and GR5515I0ND.
Table 1-1 GR551x series
GR551x Series GR5515IGND GR5515RGBD GR5515GGBD GR5513BEND GR5515I0ND
CPU Cortex®-M4F Cortex®-M4F Cortex®-M4F Cortex®-M4F Cortex®-M4F
RAM 256 KB 256 KB 256 KB 128 KB 256 KB
Flash 1 MB 1 MB 1 MB 512 KB N/A
Package (mm) QFN56
(7 x 7 x 0.75)
BGA68
(5.3 x 5.3 x 0.88)
BGA55
(3.5 x 3.5 x 0.60)
QFN40
(5 x 5 x 0.75)
QFN56
(7 x 7 x 0.75)
I/O Number 39 39 29 22 39
Note:
The GR5515RGBD is not recommended for new designs.
1.1 Features
• A Bluetooth Low Energy (Bluetooth LE) 5.1 transceiver integrates Controller and Host layers
◦ Supported data rates: 1 Mbps, 2 Mbps, Long Range 500 kbps, Long Range 125 kbps
◦ TX power: -20 dBm to +7 dBm
◦ -97 dBm sensitivity (in 1 Mbps mode)
◦ -93 dBm sensitivity (in 2 Mbps mode)
◦ -99.5 dBm sensitivity (in Long Range 500 kbps mode)
◦ -103 dBm sensitivity (in Long Range 125 kbps mode)
◦ TX current: 3.05 mA @ 0 dBm, 1 Mbps
◦ RX current: 3.9 mA @ 1 Mbps
•ARM® Cortex®-M4F 32-bit micro-processor with floating point support
◦ Maximum frequency: 64 MHz
◦ Power consumption: 30 µA/MHz
• Memory
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GR551x Overview
◦ 256 KB RAM with retention (four 8 KB RAM blocks and seven 32 KB RAM blocks) for GR5515 series SoCs,
and 128 KB RAM with retention (four 8 KB RAM blocks and three 32 KB RAM blocks) for the GR5513 SoC.
◦ 1 MB Flash for GR5515 series SoCs (The GR5515I0ND SoC uses external QSPI Flash with various model
options.) and 512 KB Flash for the GR5513 SoC.
• Power management
◦ On-chip DC-DC Converter
◦ On-chip I/O LDO to provide I/O voltage and supply external components
◦ Supply voltage: 1.7 V to 3.8 V (The supply voltage of the GR5515I0ND SoC is equal to the working voltage of
external SPI Flash.)
◦ I/O voltage: 1.8 V to 3.3 V (Typical) (On GR5515I0ND, VDDIO0 is bonded to VIO_LDO_OUT internally and
I/O LDO is set to off mode in the application firmware by default, so VIO_LDO_OUT shall be connected to
VBATL.)
◦ OFF mode: 0.15 µA (Typical); nothing is on except VBAT, chip in reset mode
◦ Ultra deep sleep mode: 0.65 µA (Typical); I/O LDO off, no memory retention. Wake-up on an external GPIO
or an internal Timer.
◦ Sleep mode: 1.3 µA (Typical); Bluetooth LE link alive, I/O LDO off, supporting AON_RTC, AON GPIO and
Bluetooth LE Event, memory retention and wake-up on an external GPIO or an internal Timer.
• Peripherals
◦ 2 x QSPI interfaces, up to 32 MHz
◦ 2 x SPI interfaces (1 SPI Master Interface with 2 slave CS pins + 1 SPI Slave Interface), up to 32 MHz
◦ 2 x I2C interfaces at 100 kHz, 400 kHz, 1 MHz, 2 MHz
◦ 2 x I2S interfaces (1 I2S Master Interface + 1 I2S Slave Interface)
◦ 2 x UART interfaces, one with DMA channel.
◦ 13-bit ADC, up to 1 Msps, 8 channels (5 external test channels and 3 internal signal channels), supporting
both single-ended and differential inputs
◦ ISO 7816 interface
◦ 6-channel PWM
◦ Built-in temperature and voltage sensors
◦ 4 x Hardware timers
◦ 1 x AON hardware timer
◦ 2 x Watchdog timers(1 System Watchdog Timer and 1 Always-on watchdog timer)
◦ Calendar timer
◦ Wake-up comparator
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GR551x Overview
◦ Up to 39 multiplexed GPIO pins
• Security
◦ Complete secure computing engine:
- AES 128-bit/192-bit/256-bit symmetric encryption (ECB, CBC)
- Keyed Hash Message Authentication Code (HMAC)
- PKC
- TRNG
◦ Comprehensive security operation mechanism:
- Secure boot
- Encrypted firmware runs directly from Flash
- eFuse for encrypted key storage
- Differentiate application data key and firmware key, supporting one data key per device/product
• Packages
◦ QFN56: 7 mm x 7 mm
◦ BGA68: 5.3 mm x 5.3 mm
◦ BGA55: 3.5 mm x 3.5 mm
◦ QFN40: 5 mm x 5 mm
• Operating temperature range: -40°C to +85°C
1.2 Block Diagram
The block diagram of GR551x is shown in the figure below.
Copyright © 2021 Shenzhen Goodix Technology Co., Ltd. 3

GR551x Overview
PMU Subsystem
Bluetooth Subsystem
RF Transceiver Communicaon Core
XO
PLL
Mixer
CLK
Gen.
Dig.Front End Bluetooth LE
Modem
Bluetooth LE
MAC Packet Buffer
DC/DC
LP LDO
Sleep Osc.
RTC
Power
Sequencer
MCU Subsystem
SRAM
ROM
Security
Cores
Memory/State
Retenon
Wake up
LP Comp.
Always-On
Domain
Flash
Cache
Cache Ctrl. Flash & XIP
Ctrl.
ARM®Cortex®-
M4F
BB ADC
PA
System
WDT.
Dual.
Timer
TimerQSPI
I2S
ADC
GPIO
UART
PWM
SPI
I2C
ISO781
6
LNA
Figure 1-1 GR551x block diagram
Note:
For more details of each module in this block diagram, see GR551x Datasheet.
Copyright © 2021 Shenzhen Goodix Technology Co., Ltd. 4

Pinout
2 Pinout
GR551x is available in five packages: GR5515IGND QFN56, GR5515I0ND QFN56, GR5515RGBD BGA68, GR5515GGBD
BGA55 and GR5513BEND QFN40.
2.1 GR5515IGND QFN56
Figure 2-1 shows the pin assignments of GR5515IGND QFN56 package (top view).
VDD_VCOVDD_RF
TRX
GPIO_0
XON
GPIO_26
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_30 GPIO_31 GPIO_17 GPIO_16 GPIO_25 GPIO_24
GR5515IGND
QFN56
XOP
VDD_AMS
GPIO_28 GPIO_27
VBATT_RF
GPIO_8
VIO_LDO_OUT
GPIO_12
VDDIO_1
VBATL
VSS_BUCK
VSW
VREG
VDD_DIGCORE_1V
CHIP_EN
RF pin DigitalI/O & supplies pin Analog pin
GPIO_13 GPIO_14
42
41
40
39
38
37
36
35
34
33
32
31
AON_GPIO_5
MSIO0
AON_GPIO_4
AON_GPIO_3
AON_GPIO_2
AON_GPIO_1
AON_GPIO_0
TEST_MODE
MSIO1
MSIO2
30
29 RTC_P
GR5515IGND
QFN56
GPIO_9
GPIO_10
GPIO_11 GPIO_15
RTC_N
GPIO_29
AON_GPIO_7
AON_GPIO_6
MSIO3
MSIO4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
45 46 47 48 49 50 51 52 53 54 55 56 43 44
26 25 24 23 22 21 20 19 18 17 16 15 28 27
GR5515IGND QFN56
Figure 2-1 GR5515IGND QFN56 package pinout
Table 2-1 shows pin descriptions of GR5515IGND QFN56 package.
Copyright © 2021 Shenzhen Goodix Technology Co., Ltd. 5

Pinout
Table 2-1 GR5515IGND QFN56 pin descriptions
Pin # Pin Name Pin Type Description/Default Function Voltage Domain
1 VDD_VCO/VDD_RF Analog/RF supply
Synthesizer VCO supply. RF supply.
Connect to VREG.
2 TRX Analog/RF RX input and TX output
3 VBATT_RF Analog/RF Supply Connect to VBATL.
4 GPIO_0 Digital I/O SWDCLK VDDIO1
5 GPIO_1 Digital I/O SWDIO VDDIO1
6 GPIO_2 Digital I/O General purpose I/O VDDIO1
7 GPIO_3 Digital I/O General purpose I/O VDDIO1
8 GPIO_4 Digital I/O General purpose I/O VDDIO1
9 GPIO_5 Digital I/O General purpose I/O VDDIO1
10 GPIO_6 Digital I/O General purpose I/O VDDIO1
11 GPIO_7 Digital I/O General purpose I/O VDDIO1
12 GPIO_8 Digital I/O General purpose I/O VDDIO1
13 GPIO_9 Digital I/O General purpose I/O VDDIO1
14 GPIO_10 Digital I/O General purpose I/O VDDIO1
15 GPIO_11 Digital I/O General purpose I/O VDDIO1
16 GPIO_12 Digital I/O General purpose I/O VDDIO1
17 VDDIO_1 Digital I/O supply Digital I/O supply input VDDIO1
18 GPIO_13 Digital I/O General purpose I/O VDDIO1
19 GPIO_14 Digital I/O General purpose I/O VDDIO1
20 GPIO_15 Digital I/O General purpose I/O VDDIO1
21 CHIP_EN Mixed Signal IN
Master Enable for chip reset pin.
Minimum value of high level for CHIP_EN is 1 V.
22 VIO_LDO_OUT PMU Output of On-Chip I/O supply regulator
Connected internally
to VDDIO0
23 VDD_DIGCORE_1V PMU
Output of On-Chip LDO for digital core. Connect
to a 1 µF capacitor.
24 VREG PMU Feedback pin from switching regulator
25 VSW PMU DC-DC Converter switching node
26 VSS_BUCK PMU
DC-DC converter supply and general battery
GND
27 VBATL PMU Power supply input
28 RTC_N PMU RTC terminal -, 32.768 kHz crystal -
Copyright © 2021 Shenzhen Goodix Technology Co., Ltd. 6

Pinout
Pin # Pin Name Pin Type Description/Default Function Voltage Domain
29 RTC_P PMU RTC terminal +, 32.768 kHz crystal +
30 MSIO4 Mixed Signal I/O
Configurable to be a GPIO mixed signal (ADC
interface)
VBATL
31 MSIO3 Mixed Signal I/O
Configurable to be a GPIO mixed signal (ADC
interface)
VBATL
32 MSIO2 Mixed Signal I/O
Configurable to be a GPIO mixed signal (ADC
interface)
VBATL
33 MSIO1 Mixed Signal I/O
Configurable to be a GPIO mixed signal (ADC
interface)
VBATL
34 MSIO0 Mixed Signal I/O
Configurable to be a GPIO mixed signal (ADC
interface)
VBATL
35 TEST_MODE Digital I/O
Input pin, used to set test mode for FT or CP
factory test. In the application phase, the value
is set to 0 by default.
If TEST_MODE = 1, the chip is in test mode for
factory test.
If TEST_MODE = 0, the chip is in normal
operation mode.
VDDIO0
36 AON_GPIO_0 Digital I/O Always-on GPIO VDDIO0
37 AON_GPIO_1 Digital I/O Always-on GPIO VDDIO0
38 AON_GPIO_2 Digital I/O Always-on GPIO VDDIO0
39 AON_GPIO_3 Digital I/O Always-on GPIO VDDIO0
40 AON_GPIO_4 Digital I/O Always-on GPIO VDDIO0
41 AON_GPIO_5 Digital I/O Always-on GPIO VDDIO0
42 AON_GPIO_6 Digital I/O Always-on GPIO VDDIO0
43 AON_GPIO_7 Digital I/O Always-on GPIO VDDIO0
44 GPIO_24 Digital I/O General purpose I/O VDDIO0
45 GPIO_25 Digital I/O General purpose I/O VDDIO0
46 GPIO_16 Digital I/O General purpose I/O VDDIO0
47 GPIO_17 Digital I/O General purpose I/O VDDIO0
48 GPIO_31 Digital I/O General purpose I/O VDDIO0
49 GPIO_30 Digital I/O General purpose I/O VDDIO0
50 GPIO_26 Digital I/O General purpose I/O VDDIO0
51 GPIO_27 Digital I/O General purpose I/O VDDIO0
Copyright © 2021 Shenzhen Goodix Technology Co., Ltd. 7

Pinout
Pin # Pin Name Pin Type Description/Default Function Voltage Domain
52 GPIO_28 Digital I/O General purpose I/O VDDIO0
53 GPIO_29 Digital I/O General purpose I/O VDDIO0
54 VDD_AMS Analog/RF Supply AMS supply. Connect to VREG.
55 XON Analog/RF XO Crystal -
56 XOP Analog/RF XO Crystal +
2.2 GR5515I0ND QFN56
Figure 2-2 shows the pin assignments of GR5515I0ND QFN56 package (top view).
The pins (Pin 43 to Pin 53) of GR5515I0ND QFN56 package are different from those of GR5515IGND QFN56 package.
Copyright © 2021 Shenzhen Goodix Technology Co., Ltd. 8

Pinout
VDD_VCOVDD_RF
TRX
GPIO_0
XON
GPIO_25
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_24 GPIO_23 GPIO_22 GPIO_21 GPIO_20 GPIO_19
GR5515IGND
QFN56
XOP
VDD_AMS
GPIO_30 GPIO_16
VBATT_RF
GPIO_8
VIO_LDO_OUT
GPIO_12
VDDIO_1
VBATL
VSS_BUCK
VSW
VREG
VDD_DIGCORE_1V
CHIP_EN
RF pin DigitalI/O & supplies pin Analog pin
GPIO_13 GPIO_14
42
41
40
39
38
37
36
35
34
33
32
31
AON_GPIO_5
MSIO0
AON_GPIO_4
AON_GPIO_3
AON_GPIO_2
AON_GPIO_1
AON_GPIO_0
TEST_MODE
MSIO1
MSIO2
30
29 RTC_P
GR5515IGND
QFN56
GPIO_9
GPIO_10
GPIO_11 GPIO_15
RTC_N
GPIO_26 GPIO_18
AON_GPIO_6
MSIO3
MSIO4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
45 46 47 48 49 50 51 52 53 54 55 56 43 44
26 25 24 23 22 21 20 19 18 17 16 15 28 27
GR5515I0ND QFN56
External Flash pin
Figure 2-2 GR5515I0ND QFN56 package pinout
Table 2-2 shows pin descriptions of GR5515I0ND QFN56 package.
Table 2-2 GR5515I0ND QFN56 pin descriptions
Pin # Pin Name Pin Type Description/Default Function Voltage Domain
1 VDD_VCO/VDD_RF Analog/RF supply
Synthesizer VCO supply. RF supply.
Connect to VREG.
2 TRX Analog/RF RX input and TX output
3 VBATT_RF Analog/RF Supply Connect to VBATL.
Copyright © 2021 Shenzhen Goodix Technology Co., Ltd. 9

Pinout
Pin # Pin Name Pin Type Description/Default Function Voltage Domain
4 GPIO_0 Digital I/O SWDCLK VDDIO1
5 GPIO_1 Digital I/O SWDIO VDDIO1
6 GPIO_2 Digital I/O General purpose I/O VDDIO1
7 GPIO_3 Digital I/O General purpose I/O VDDIO1
8 GPIO_4 Digital I/O General purpose I/O VDDIO1
9 GPIO_5 Digital I/O General purpose I/O VDDIO1
10 GPIO_6 Digital I/O General purpose I/O VDDIO1
11 GPIO_7 Digital I/O General purpose I/O VDDIO1
12 GPIO_8 Digital I/O General purpose I/O VDDIO1
13 GPIO_9 Digital I/O General purpose I/O VDDIO1
14 GPIO_10 Digital I/O General purpose I/O VDDIO1
15 GPIO_11 Digital I/O General purpose I/O VDDIO1
16 GPIO_12 Digital I/O General purpose I/O VDDIO1
17 VDDIO_1 Digital I/O supply Digital I/O supply input VDDIO1
18 GPIO_13 Digital I/O General purpose I/O VDDIO1
19 GPIO_14 Digital I/O General purpose I/O VDDIO1
20 GPIO_15 Digital I/O General purpose I/O VDDIO1
21 CHIP_EN Mixed Signal IN
Master Enable for chip reset pin.
Minimum value of high level for CHIP_EN is 1 V.
22 VIO_LDO_OUT PMU
Connected to VBATL, output of on-chip I/O supply
regulator, used as power input pin of VDDIO0 digital
IO domain.
Connected internally to
VDDIO0
23 VDD_DIGCORE_1V PMU
Output of On-Chip LDO for digital core. Connect to a 1
µF capacitor.
24 VREG PMU Feedback pin from switching regulator
25 VSW PMU DC-DC Converter switching node
26 VSS_BUCK PMU DC-DC converter supply and general battery GND
27 VBATL PMU Power supply input
28 RTC_N PMU RTC terminal -, 32.768 kHz crystal -
29 RTC_P PMU RTC terminal +, 32.768 kHz crystal +
30 MSIO4 Mixed Signal I/O
Configurable to be a GPIO mixed signal (ADC
interface)
VBATL
31 MSIO3 Mixed Signal I/O
Configurable to be a GPIO mixed signal (ADC
interface)
VBATL
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Pinout
Pin # Pin Name Pin Type Description/Default Function Voltage Domain
32 MSIO2 Mixed Signal I/O
Configurable to be a GPIO mixed signal (ADC
interface)
VBATL
33 MSIO1 Mixed Signal I/O
Configurable to be a GPIO mixed signal (ADC
interface)
VBATL
34 MSIO0 Mixed Signal I/O
Configurable to be a GPIO mixed signal (ADC
interface)
VBATL
35 TEST_MODE Digital I/O
Input pin, used to set test mode for FT or CP factory
test. In the application phase, the value is set to 0 by
default.
If TEST_MODE = 1, the chip is in test mode for factory
test.
If TEST_MODE = 0, the chip is in normal operation
mode.
VDDIO0
36 AON_GPIO_0 Digital I/O Always-on GPIO VDDIO0
37 AON_GPIO_1 Digital I/O Always-on GPIO VDDIO0
38 AON_GPIO_2 Digital I/O Always-on GPIO VDDIO0
39 AON_GPIO_3 Digital I/O Always-on GPIO VDDIO0
40 AON_GPIO_4 Digital I/O Always-on GPIO VDDIO0
41 AON_GPIO_5 Digital I/O Always-on GPIO VDDIO0
42 AON_GPIO_6 Digital I/O Always-on GPIO VDDIO0
43 GPIO_18 Digital I/O Connect to an external Flash VDDIO0
44 GPIO_19 Digital I/O Connect to an external Flash VDDIO0
45 GPIO_20 Digital I/O Connect to an external Flash VDDIO0
46 GPIO_21 Digital I/O Connect to an external Flash VDDIO0
47 GPIO_22 Digital I/O Connect to an external Flash VDDIO0
48 GPIO_23 Digital I/O Connect to an external Flash VDDIO0
49 GPIO_24 Digital I/O General purpose I/O VDDIO0
50 GPIO_25 Digital I/O General purpose I/O VDDIO0
51 GPIO_16 Digital I/O General purpose I/O VDDIO0
52 GPIO_30 Digital I/O General purpose I/O VDDIO0
53 GPIO_26 Digital I/O General purpose I/O VDDIO0
54 VDD_AMS Analog/RF Supply AMS supply. Connect to VREG.
55 XON Analog/RF XO Crystal -
56 XOP Analog/RF XO Crystal +
Copyright © 2021 Shenzhen Goodix Technology Co., Ltd. 11

Pinout
2.3 GR5515RGBD BGA68 (NRND)
Figure 2-3 shows the pin assignments of GR5515RGBD BGA68 package (top view).
A
B
C
D
E
F
G
H
GR5515RGBD BGA68
VDD_VCO TPP XOP XON VDD_AMS GPIO28 GPIO27 GPIO26
VDD_RF TPN
GPIO29 GPIO31RF_GND RF_GND GPIO25
TRX
VBATT_RF
GPIO4 GPIO2 VDDIO_1
GPIO5 GPIO6 MSIO4
VDD_CORE GPIO11 CHIP_EN VBATH_LDO
_WBE PMUGND MSIO3 MSIO2
Analog pinDigital I/O & supplies pinRF pin
1 2 4 5 6 7 83
J
K
GPIO7 GPIO10 VIO_LDO
_OUT
GPIO3 VDD_DIG
CORE_1V VREG VBATH VSW VBATL MSIO1 RTC_N
9 10
RF_GND
GPIO1
GPIO0
DGND DGND
TEST_MODE
GPIO30 GPIO17
GPIO16
AON_GPIO1
AON_GPIO0
GPIO13 GPIO24
AON_GPIO6
AON_GPIO7
GPIO8
MISO0
RTC_P
GPIO14
GPIO15
GPIO9
GPIO12
AON_GPIO5
AON_GPIO4
AON_GPIIO3
AON_GPIO2
NC
Figure 2-3 GR5515RGBD BGA68 package pinout
Table 2-3 shows pin descriptions of GR5515RGBD BGA68 package.
Copyright © 2021 Shenzhen Goodix Technology Co., Ltd. 12

Pinout
Table 2-3 GR5515RGBD BGA68 package pin descriptions
Pin # Pin Name Pin Type Description/Default Function Voltage Domain
A1 VDD_VCO Analog/RF supply Synthesizer VCO supply: 1.1 V
A2 TPP Analog/RF Test Mux +output
A3 XOP Analog/RF XO crystal +
A4 XON Analog/RF XO crystal -
A5 VDD_AMS Analog/RF AMS supply 1.1 V
A6 GPIO28 Digital I/O General purpose I/O VDDIO0
A7 GPIO27 Digital I/O General purpose I/O VDDIO0
A8 GPIO26 Digital I/O General purpose I/O VDDIO0
A9 GPIO30 Digital I/O General purpose I/O VDDIO0
A10 GPIO17 Digital I/O General purpose I/O VDDIO0
B1 VDD_RF Analog/RF RF supply 1.1 V
B2 TPN Analog/RF Test Mux - output
B9 GPIO13 Digital I/O General purpose I/O VDDIO1
B10 GPIO24 Digital I/O General purpose I/O VDDIO0
C1 RF_GND Analog/RF RF ground
C3 RF_GND Analog/RF RF ground
C4 GPIO0 Digital I/O General purpose I/O, default SWDCLK VDDIO1
C5 GPIO29 Digital I/O General purpose I/O VDDIO0
C6 GPIO31 Digital I/O General purpose I/O VDDIO0
C7 GPIO25 Digital I/O General purpose I/O VDDIO0
C8 GPIO16 Digital I/O General purpose I/O VDDIO0
C10 GPIO14 Digital I/O General purpose I/O VDDIO1
D1 TRX Analog/RF RX input and TX output
D3 RF_GND Analog/RF RF ground
D8 NC - -
D9 AON_GPIO6 Digital I/O Always-on General purpose I/O VDDIO0
D10 GPIO15 Digital I/O General purpose I/O VDDIO1
E1 VBATT_RF Analog/RF Connect to VBATL
E3 GPIO1 Digital I/O General purpose I/O, default SWDIO VDDIO1
E5 DGND Digital GND Digital Ground
E6 DGND Digital GND Digital Ground
E8 AON_GPIO1 Digital I/O Always-on general purpose I/O VDDIO0
E9 AON_GPIO7 Digital I/O Always-on general purpose I/O VDDIO0
Copyright © 2021 Shenzhen Goodix Technology Co., Ltd. 13

Pinout
Pin # Pin Name Pin Type Description/Default Function Voltage Domain
E10 GPIO9 Digital I/O General purpose I/O VDDIO1
F1 GPIO4 Digital I/O General purpose I/O VDDIO1
F3 GPIO2 Digital I/O General purpose I/O VDDIO1
F5 VDDIO_1 Digital Supply I/O supply voltage input VDDIO1
F6 TEST_MODE Digital I/O
Input pin, used to set test mode for FT or CP factory
test. In the application phase, the value is set to 0 by
default.
If TEST_MODE = 1, the chip is in test mode for factory
test.
If TEST_MODE = 0, the chip is in normal operation
mode.
VDDIO0
F8 AON_GPIO0 Digital I/O Always-on general purpose I/O VDDIO0
F9 GPIO8 Digital I/O General purpose I/O VDDIO1
F10 GPIO12 Digital I/O General purpose I/O VDDIO1
G1 GPIO5 Digital I/O General purpose I/O VDDIO1
G3 GPIO6 Digital I/O General purpose I/O VDDIO1
G8 MSIO4 Mixed Signal I/O
Configurable to be a GPIO mixed signal (ADC
interface)
VBATL
G10 AON_GPIO5 Digital I/O Always-on general purpose I/O VDDIO0
H1 VDD_CORE Digital Supply Digital core supply
H3 GPIO11 Digital I/O General purpose I/O VDDIO1
H4 CHIP_EN Analog/PMU
Master Enable for chip reset pin.
Minimum value of high level for CHIP_EN is 1 V.
H5 VBATH_LDO_WBE Analog/PMU Connect to GND.
H6 PMUGND Analog/PMU DC-DC converter supply & general battery GND
H7 MSIO3 Mixed Signal I/O
Configurable to be a GPIO mixed signal (ADC
interface)
VBATL
H8 MSIO2 Mixed Signal I/O
Configurable to be a GPIO mixed signal (ADC
interface)
VBATL
H10 AON_GPIO4 Digital I/O Always-on general purpose I/O VDDIO0
J1 GPIO7 Digital I/O General purpose I/O VDDIO1
J2 GPIO10 Digital I/O General purpose I/O VDDIO1
J4 VIO_LDO_OUT Analog/PMU Output of On-Chip I/O supply regulator.
Connected internally
to VDDIO0
Copyright © 2021 Shenzhen Goodix Technology Co., Ltd. 14