Harman Kardon AVR 3550 User manual

AVR 3550 Audio/VideoReceiver
Service Manual
AVR 3550
Power for the Digital Revolution™
®

Technical Specifications
Audio Section
Stereo Mode
ContinuousAverage Power (FTC)
65Watts per channel, 20Hz–20kHz,
@ < 0.07%THD, both channels driven into 8 ohms
Five-Channel Surround Modes
Power Per Individual Channel
Front L&R channels:
55Watts per channel,
@ < 0.07%THD, 20Hz–20kHz into 8 ohms
Center channel:
55Watts,@ < 0.07%THD, 20Hz–20kHz into 8 ohms
Surround channels:
55Watts per channel,
@ < 0.07%THD, 20Hz–20kHz into 8 ohms
Input Sensitivity/Impedance
Linear (High Level) 200mV/47kohms
Signal-to-Noise Ratio (IHF-A) 95dB
Surround SystemAdjacent Channel Separation
Analog Decoding 40dB
(Pro Logic II,etc.)
Dolby Digital (AC-3) 55dB
DTS 55dB
Frequency Response
@ 1W (+0dB, –3dB) 10Hz–100kHz
High Instantaneous
Current Capability (HCC) ±28Amps
Transient Intermodulation
Distortion (TIM) Unmeasurable
RiseTime 16µsec
Slew Rate 40V/µsec
FM Tuner Section
Frequency Range 87.5–108MHz
Usable Sensitivity IHF 1.3 µV/13.2dBf
Signal-to-Noise Ratio Mono/Stereo:70/65dB (DIN)
Distortion Mono/Stereo:0.15/0.3%
Stereo Separation 35dB @ 1kHz
Selectivity ±300kHz:65dB
Image Rejection 80dB
IF Rejection 90dB
AM Tuner Section
Frequency Range 522–1620kHz
Signal-to-Noise Ratio 45dB
Usable Sensitivity Loop:500µV
Distortion 1kHz,50% Mod: 0.8%
Selectivity ±9kHz:30dB
Video Section
Video Format PAL/NTSC
Input Level/Impedance 1Vp-p/75 ohms
Output Level/Impedance 1Vp-p/75 ohms
Video Frequency
Response 10Hz–8MHz (–3dB)
General
Power Requirement AC 220-240V/50Hz
Power Consumption 72W idle, 580W maximum
(2 channels driven)
Dimensions (Max)
Width 440mm
Height 168mm
Depth 390mm
Weight 12.0 kg
Depth measurement includes knobs, buttons and terminal connections.
Height measurement includes feet and chassis.
All features and specifications are subject to change without notice.
Harman Kardon is a registered trademark,and Power for the digital revolution is a
trademark,of Harman International Industries,Inc.
is a trademark of Harman International Industries, Inc.
(Patent No.5,386,478).
*Manufactured under license from Dolby Laboratories.
“Dolby”,“Pro Logic”and the Double-D symbol are registered
trademarks of Dolby Laboratories.Confidential Unpublished
Works. ©1992–1999 Dolby Laboratories, Inc.All rights reserved.
†“DTS”and“DTS Digital Surround” are registered trademarks of
DigitalTheater Systems, Inc.
††UltraStereo is a registered trademark of UltraStereo Corp.
VMAx is a trademark of Harman International Industries, Inc.,and is an
implementation of Cooper BauckTransaural Stereo under patent license.
Logic 7 is a registered trademark of Lexicon,Inc.
Crystal is a registered trademark of Cirrus Logic Corp.
TM

48 TROUBLESHOOTING GUIDE
TROUBLESHOOTING
SYMPTOM CAUSE SOLUTION
Unit does not function when Main • No AC Power • Make certain AC power cord is plugged into a live outlet
Power Switch is pushed • Check to see whether outlet is switch-controlled
Display lights, but no sound • Intermittent input connections • Make certain that all input and speaker connections are secure
or picture • Mute is on • Press Mute button
• Volume control is down • Turn up volume control
Unit turns on, but front-panel • Display brightness is turned off • Follow the instructions in the Display Brightness section
display does not light up on page 30 so that the display is set to VFD FULL
No sound from any speaker; • Amplifier is in protection mode • Check speaker wire connections for shorts at receiver and
light around power switch is red due to possible short speaker ends
• Amplifier is in protection mode • Contact your local Harman Kardon service center, which you can
due to internal problems locate by visiting our Web site at www.harmankardon.com
No sound from surround or • Incorrect surround mode • Select a mode other than Stereo or Dolby 3 Stereo
center speakers • Input is monaural • There is no surround information from mono sources
• Incorrect configuration • Check speaker mode configuratioin
• Stereo or Mono program material • The surround decoder may not create center- or rear-channel
information from nonencoded programs
Unit does not respond to • Weak batteries in remote • Change remote batteries
remote commands • Wrong device selected • Press the AVR selector
• Remote sensor is obscured • Make certain front-panel sensor is visible to remote
or connect remote sensor
Intermittent buzzing in tuner • Local interference • Move unit or antenna away from computers, fluorescent
lights, motors or other electrical appliances
Letters flash in the channel indicator • Digital audio feed paused • Resume play for DVD
display and digital audio stops • Check that Digital Input is selected

AMPLIFIER SECTION BIAS ADJUSTMENT
CUP11517X (MAIN PCB)
Measurement condition
. No input signal or volume position is minimum.
Standard value.
. Ideal current = 48mA ( ±5%)
. Ideal DC Voltage = 21.12mV ( ±5%)
DC VOLTMETER..............Connect to CN61, CN62, CN63, CN64, CN65
NO. Channel Adjust for Adjustment
1 Front Left 21.12mV (±5%) VR61
CN61
VR61
2 Front Right 21.12mV (±5%)
21.12mV (±5%)
21.12mV (±5%)
21.12mV (±5%)
VR62
CN62
VR62
3 Center VR63
CN63
VR63
4 Surround Left VR64
CN64
VR64
5 Surround Right VR65
VR65
CN65

nBlock Diagram
SCF DAC DATT
DZFL1
LOUT1+
LOUT1-
SCF DAC DATT
DZFR1
ROUT1+
ROUT1-
SCF DAC DATT
DZFL2
LOUT2+
LOUT2-
SCF DAC DATT
DZFR2
ROUT2+
ROUT2-
SCF DAC DATT
DZFL3
LOUT3+
LOUT3-
SCF DAC DATT
DZFR3
ROUT3+
ROUT3-
Audio
I/F
Control
Register
AK4356
MCLK
LRCK
BICK
MCK
O
LRCK
BICK
XTI
XTO
Controller
CS
CCLK
CDTI
LRCK
BICK
SDOUT1
SDOUT2
SDOUT3
AC3
SDTI1
SDTI2
SDTI3

LOUT1-
ROUT
1+
1
LOUT1+
44
2
DZFL2 3
DZFR1 4
DZFL1 5
C
AD0 6
C
AD1 7
PDN 8
BICK 9
MCLK 10
DVDD 11
ROUT
1-43
LOUT
2+42
LOUT
2-41
ROUT
2+40
ROUT
2-
39
LOUT
3+38
LOUT
3-
37
ROUT
3+36
ROUT
3-35
AVSS
34
DVSS
12
SDTI
113
SDTI
214
SDTI
315
LRCK
16
SMUTE
17
CCLK
18
CDTI
19
CSN 20
DFS
021
CKS
022
33
32
31
30
29
28
27
26
25
24
23
AVDD
VREFH
DZFR2
DZFL3
DZFR3
DZFE
DIF2
DIF1
DIF0
CKS2
CKS1
AK4356VQ
Top View

PIN/FUNCTION
No. Pin Name I/O Function
1 LOUT1- O DAC1 Lch Negative Analog Output Pin
2 LOUT1+ O DAC1 Lch Positive Analog Output Pin
3 DZFL2 O DAC2 Lch Zero Input Detect Pin
4 DZFR1 O DAC1 Rch Zero Input Detect Pin
5 DZFL1 O DAC1 Lch Zero Input Detect Pin
6 CAD0 I Chip Address 0 Pin
7 CAD1 I Chip Address 1 Pin
8 PDN I Power-Down & Reset Pin
When “L”, the AK4356 is powered-down and the control registers are reset to
default state. If the state of CAD0-1 changes, then the AK4356 must be reset by PDN.
9 BICK I Audio Serial Data Clock Pin
10 MCLK I Master Clock Input Pin
11 DVDD - Digital Power Supply Pin, +4.75~+5.25V
12 DVSS - Digital Ground Pin
13 SDTI1 I DAC1 Audio Serial Data Input Pin
14 SDTI2 I DAC2 Audio Serial Data Input Pin
15 SDTI3 I DAC3 Audio Serial Data Input Pin
16 LRCK I Audio Input Channel Clock Pin
17 SMUTE I Soft Mute Pin (Note)
When this pin goes to “H”, soft mute cycle is initialized.
When returning to “L”, the output mute releases.
18 CCLK I Control Data Clock Pin
19 CDTI I Control Data Input Pin
20 CSN I Chip Select Pin
This pin should be held to “H” except for access.

No. Pin Name I/O Function
21 DFS0 I Double Speed Sampling Mode 0 Pin (Note)
“L”: Normal Speed, “H”: Double Speed at DFS1 bit = “0”.
22 CKS0 I Input Clock Select 0 Pin (Note)
23 CKS1 I Input Clock Select 1 Pin (Note)
24 CKS2 I Input Clock Select 2 Pin (Note)
25 DIF0 I Audio Data Interface Format 0 Pin (Note)
26 DIF1 I Audio Data Interface Format 1 Pin (Note)
27 DIF2 I Audio Data Interface Format 2 Pin (Note)
28 DZFE I Zero Input Detect Enable Pin (Note)
29 DZFR3 O DAC3 Rch Zero Input Detect Pin
30 DZFL3 O DAC3 Lch Zero Input Detect Pin
31 DZFR2 O DAC2 Rch Zero Input Detect Pin
32 VREFH I Positive Voltage Reference Input Pin, AVDD
33 AVDD - Analog Power Supply Pin
34 AVSS - Analog Ground Pin, +4.75~+5.25V
35 ROUT3- O DAC3 Rch Negative Analog Output Pin
36 ROUT3+ O DAC3 Rch Positive Analog Output Pin
37 LOUT3- O DAC3 Lch Negative Analog Output Pin
38 LOUT3+ O DAC3 Lch Positive Analog Output Pin
39 ROUT2- O DAC2 Rch Negative Analog Output Pin
40 ROUT2+ O DAC2 Rch Positive Analog Output Pin
41 LOUT2- O DAC2 Lch Negative Analog Output Pin
42 LOUT2+ O DAC2 Lch Positive Analog Output Pin
43 ROUT1- O DAC1 Rch Negative Analog Output Pin
44 ROUT1+ O DAC1 Rch Positive Analog Output Pin
Note:SMUTE, DFS0, CKS0, CKS1, CKS2, DIF0, DIF1, DIF2, DZFE pins are ORed with serial control register.

In
p
ut
Selector
Clock
Recovery Clock
Generator
DAIF
Decoder
AC-3/MPEG
Detect
DEM
µP I/F
Audio
I/F
X'tal
Oscillator
PDN
INT0
P/S=”L”
LRCK
BICK
SDTO
DAUX
MCKO2
XTOXTI
RAVDDAVSS
CDTI
CDTO
CCLK
CSN
DVDD
DVSS
TVDD
MCKO1
IIC
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
DIT
TX0
Error &
Detect
STATUS
INT1
Q-subcode
buffer
TX1
B,C,U,VOUT
8 to 3
VIN
Serial Control Mode
In
p
ut
Selector
Clock
Recovery Clock
Generator
DAIF
Decoder
AC-3/MPEG
Detect
DEM
Audio
I/F
X'tal
Oscillator
PDN
INT0
P/S=”H”
LRCK
BICK
SDTO
DAUX
XTOXTI
RAVDDAVSS
CM1
CM0
OCKS1
OCKS0
DVDD
DVSS
TVDD
IPS1
RX0
RX1
RX2
RX3
IPS0
DIF0
DIF1
DIF2
DIT
TX0
Error &
Detect
STATUS
INT1
TX1
B,C,U,VOUT
4 to 2
VIN
MCKO2
MCKO1
Parallel Control Mode

IPS0/RX4
RX3
1
AVSS
48
2
DIF0/RX5 3
TEST2 4
DIF1/RX6 5
AVSS 6
DIF2/RX7 7
IPS1/IIC 8
P/SN 9
XTL0 10
XTL1
AVSS
47
RX2
46
45 44
AVSS
43
RX0
42
AVSS
41
VCOM
40
R
39
AVDD
38
TVD
D
13
N
C
14
TX0 15 TX1 16
BOU
T
17 18
UOU
T
19
VOU
T
20
DVD
D
21
DVSS
22
MCKO1 23
36
35
34
33
32
31
30
29
28
27
26
INT0
OCKS0/CSN/CAD0
OCKS1/CCLK/SCL
CM1/CDTI/SDA
CM0/CDTO/CAD1
PDN
XTI
XTO
DAUX
MCKO2
BICK
AK4114VQ
Top View
COU
T
TEST1
RX1
INT1
37
LRCK
24
11
VIN 12 25 SDTO

PIN/FUNCTION
No. Pin Name I/O Function
IPS0 I Input Channel Select 0 Pin in Parallel Mode
1 RX4 I Receiver Channel 4 Pin in Serial Mode (Internal biased pin)
2 NC(AVSS) I No Connect
No internal bonding. This pin should be connected to AVSS.
DIF0 I Audio Data Interface Format 0 Pin in Parallel Mode
3 RX5 I Receiver Channel 5 Pin in Serial Mode (Internal biased pin)
4 TEST2 I TEST 2 pin
This pin should be connect to AVSS.
DIF1 I Audio Data Interface Format 1 Pin in Parallel Mode
5 RX6 I Receiver Channel 6 Pin in Serial Mode (Internal biased pin)
6 NC(AVSS) I No Connect
No internal bonding. This pin should be connected to AVSS.
DIF2 I Audio Data Interface Format 2 Pin in Parallel Mode
7 RX7 I Receiver Channel 7 Pin in Serial Mode (Internal biased pin)
IPS1 I Input Channel Select 1 Pin in Parallel Mode
8 IIC I
IIC Select Pin in Serial Mode.
“L”: 4-wire Serial, “H”: IIC
9 P/SN I Parallel/Serial Select Pin
“L”: Serial Mode, “H”: Parallel Mode
10 XTL0 I X’tal Frequency Select 0 Pin
11 XTL1 I X’tal Frequency Select 1 Pin
12 VIN I V-bit Input Pin for Transmitter Output
13 TVDD I Input Buffer Power Supply Pin, 3.3V or 5V
14 NC I No Connect
No internal bonding. This pin should be open or connected to DVSS.
15 TX0 O Transmit Channel (Through Data) Output 0 Pin
16 TX1 O When TX bit = “0”, Transmit Channel (Through Data) Output 1 Pin.
When TX bit = “1”, Transmit Channel (DAUX Data) Output Pin (Default).
17 BOUT O Block-Start Output Pin for Receiver Input
“H” during first 40 flames.
18 COUT O C-bit Output Pin for Receiver Input
19 UOUT O U-bit Output Pin for Receiver Input
20 VOUT O V-bit Output Pin for Receiver Input
21 DVDD I Digital Power Supply Pin, 3.3V
22 DVSS I Digital Ground Pin
23 MCKO1 O Master Clock Output 1 Pin
24 LRCK I/O Channel Clock Pin
25 SDTO O Audio Serial Data Output Pin
26 BICK I/O Audio Serial Data Clock Pin
27 MCKO2 O Master Clock Output 2 Pin
28 DAUX I Auxiliary Audio Data Input Pin
29 XTO O X'tal Output Pin
30 XTI I X'tal Input Pin

PIN/FUNCTION (Continued)
No. Pin Name I/O Function
31 PDN I Power-Down Mode Pin
When “L”, the AK4114 is powered-down and reset.
CM0 I Master Clock Operation Mode 0 Pin in Parallel Mode
CDTO O Control Data Output Pin in Serial Mode, IIC= “L”.32
CAD1 I Chip Address 1 Pin in Serial Mode, IIC= “H”.
CM1 I Master Clock Operation Mode 1 Pin in Parallel Mode
CDTI I Control Data Input Pin in Serial Mode, IIC= “L”.33
SDA I/O Control Data Pin in Serial Mode, IIC= “H”.
OCKS1 I Output Clock Select 1 Pin in Parallel Mode
CCLK I Control Data Clock Pin in Serial Mode, IIC= “L”34
SCL I Control Data Clock Pin in Serial Mode, IIC= “H”
OCKS0 I Output Clock Select 0 Pin in Parallel Mode
CSN I Chip Select Pin in Serial Mode, IIC=”L”.35
CAD0 I Chip Address 0 Pin in Serial Mode, IIC= “H”.
36 INT0 O Interrupt 0 Pin
37 INT1 O Interrupt 1 Pin
38 AVDD I Analog Power Supply Pin, 3.3V
39 R - External Resistor Pin
18kΩ+/-1% resistor should be connected to AVSS externally.
40 VCOM - Common Voltage Output Pin
0.47µF capacitor should be connected to AVSS externally.
41 AVSS I Analog Ground Pin
42 RX0 I Receiver Channel 0 Pin (Internal biased pin)
This channel is default in serial mode.
43 NC(AVSS) I No Connect
No internal bonding. This pin should be connected to AVSS.
44 RX1 I Receiver Channel 1 Pin (Internal biased pin)
45 TEST1 I TEST 1 pin.
This pin should be connected to AVSS.
46 RX2 I Receiver Channel 2 Pin (Internal biased pin)
47 NC(AVSS) I No Connect
No internal bonding. This pin should be connected to AVSS.
48 RX3 I Receiver Channel 3 Pin (Internal biased pin)
Note 1. All input pins except internal biased pins should not be left floating.

PIN ASSIGNMENT (74HCU04AFN : IC71,72 )
LOGIC SYMBOL
TRUTH TABLE
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
6A
6Y
5A
5Y
4A
4Y
Vcc
14
13
12
11
10
9
8
A
L
H
Y
H
L
1A (1)
(3)
(5)
(9)
(11)
(13)
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
(2)
(4)
(6)
(8)
(10)
(12)

© 2000 Fairchild Semiconductor Corporation DS005355 www.fairchildsemi.com
August 1984
Revised January2000
MM74HC4066 Quad Analog Switch
QuadAnalogSwitch (74HC4066D) : IC42
General Description
The MM74HC4066 devices are digitally controlled analog
switches utilizing advanced silicon-gate CMOS technology.
These switches have low “ON” resistance and low “OFF”
leakages. They are bidirectional switches, thus any analog
input may be used as an output and visa-versa. Also the
MM74HC4066 switches contain linearization circuitry
which lowers the “ON” resistance and increases switch lin-
earity. The MM74HC4066 devices allow control of up to
12V (peak) analog signals with digital control signals of the
same range. Each switch has its own control input which
disables each switch when LOW. All analog inputs and out-
puts and digital inputs are protected from electrostatic
damage by diodes to VCC and ground.
Features
■Typical switch enable time: 15 ns
■Wide analog input voltage range: 0–12V
■Low “ON” resistance: 30 typ. (MM74HC4066)
■Low quiescent current: 80 µA maximum (74HC)
■Matched switch characteristics
■Individual switch controls
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Schematic Diagram Connection Diagram
Top View
Truth Table
Order Number Package Number Package Description
MM74HC4066M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HC4066SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4066MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC4066N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Input Switch
CTL I/O–O/I
L“OFF”
H“ON”

∆Σ
Modulator
MCLK
AINL
LRCK
SCLK
SDTO
DIF
VCOM
Clock Divider
AINR
AGNDVA
Decimation
Filter
Serial I/O
Interface
Voltage Reference
TTL
DGNDVD
TST
∆Σ
Modulator
Decimation
Filter
PDN

1AINR
AINL
VCOM
NC
AGND
VA
VD
DGND
Top
View
2
3
4
5
6
7
8
TST
TTL
PDN
DIF
SCLK
MCLK
LRCK
SDTO
16
15
14
13
12
11
10
9

PIN/FUNCTION
No. Pin Name I/O Description
1 AINR I Rch Analog Input Pin
2 AINL I Lch Analog Input Pin
3 NC - NC Pin
No internal bonding.
4 VCOM O Common Voltage Output Pin
Normally connected to AGND with a 0.1µF ceramic capacitor in parallel with an
electrolytic capacitor less than 2.2µF.
5 AGND - Analog Ground Pin, 0V
6VA - Analog Power Supply Pin, +4.5∼+5.5V
7VD - Digital Power Supply Pin, +2.7∼+5.5V(fs=48kHz), +4.5∼+5.5V(fs=96kHz)
8 DGND - Digital Ground Pin, 0V
9 SDTO O Serial Data Output Pin
Data bits are presented MSB first, in 2’s complement format.
This pin is “L” in the power-down mode.
10 LRCK I Left/Right Channel Select Pin
The fs clock is input to this pin.
11 MCLK I Master Clock Input Pin
12 SCLK I Serial Data Input Pin
Output data is clocked out on the falling edge of SCLK.
13 PDN I Power-Down Pin
When “L”, the circuit is in power-down mode.
The AK5380 should always be reset upon power-up.
14 DIF I Serial Interface Format Pin
“L”: MSB justified, “H”: I2S
15 TTL I Digital Input Level Select Pin
“L”: CMOS level (VD=2.7∼5.5V), “H”: TTL level (VD=4.5∼5.5V)
16 TST I Test Pin (Internal pull-down pin)
This pin should be left open.
Note: All input pins except pull-down pins should not be left floating.

CM2054C Ise Electronics Corporation
:Grid Assignment Scale 3:1
Unit : mm
Sheet 4/5
G10 G9 G8 G7 G6 G5 G4 G3 G2 G1
G3-G10 G2 G1
S16
S15
S13
S12
S14
S17
S1
S2
S4
S6
S5
S8 S9
S11
S10
S3 S7
S7
S6
S2
S1
S3
S5 S4
S16
S15
S11
S10
S12
S14
S13
S18
S21
S3 S9
S15
S12S6
S1
S19
S22
S4
S7 S13
S16
S10