Hitachi SH7751 User manual

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Hitachi SuperHRISC engine
SH7751 Series
SH7751, SH7751R
Hardware Manual
ADE-602-201B
Rev. 3.0
4/11/2002
Hitachi, Ltd.

Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.

Rev. 3.0, 04/02, page iii of xxxviii
Preface
The SH-4 (SH7751 Series (SH7751, SH7751R)) microprocessor incorporates the 32-bit SH-4
CPU and is also equipped with peripheral functions necessary for configuring a user system.
The SH7751 Series is built in with a variety of peripheral functions such as cache memory,
memory management unit (MMU), interrupt controller, floating-point unit (FPU), timers, two
serial communication interfaces (SCI, SCIF), real-time clock (RTC), user break controller (UBC),
bus state controller (BSC) and PCI controller (PCIC). This series can be used in a wide range of
multimedia equipment. The bus controller is compatible with ROM, SRAM, DRAM, synchronous
DRAM and PCMCIA.
Target Readers: This manual is designed for use by people who design application systems using
the SH7751 or SH7751R.
To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is
required.
This hardware manual contains revisions related to the addition of R-mask functionality. Be sure
to check the text for the updated content.
Purpose: This manual provides the information of the hardware functions and electrical
characteristics of the SH7751 and SH7751R.
The SH-4 Programming Manual contains detailed information of executable instructions. Please
read the Programming Manual together with this manual.
How to Use the Book:

To understand general functions
 Read the manual from the beginning.
The manual explains the CPU, system control functions, peripheral functions and electrical
characteristics in that order.

To understanding CPU functions
 Refer to the separate SH-4 Programming Manual.
Explanatory Note: Bit sequence: upper bit at left, and lower bit at right
List of Related Documents: The latest documents are available on our Web site. Please make
sure that you have the latest version.
(http://www.hitachisemiconductor.com/)

Rev. 3.0, 04/02, page iv of xxxviii

User manuals for SH7751 and SH7751R
Name of Document Document No.
SH7751 Series Hardware Manual This manual
SH-4 Programming Manual ADE-602-156

User manuals for development tools
Name of Document Document No.
C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual ADE-702-246
Simulator/Debugger User’s Manual ADE-702-186
Hitachi Embedded Workshop User’s Manual ADE-702-201

Rev. 3.0, 04/02, page v of xxxviii
Contents
Section 1 Overview........................................................................................................... 1
1.1 SH7751 Series Features..................................................................................................... 1
1.2 Block Diagram .................................................................................................................. 10
1.3 Pin Arrangement ............................................................................................................... 11
1.4 Pin Functions..................................................................................................................... 13
1.4.1 Pin Functions (256-Pin QFP) ............................................................................... 13
1.4.2 Pin Functions (256-Pin BGA).............................................................................. 24
Section 2 Programming Model...................................................................................... 35
2.1 Data Formats ..................................................................................................................... 35
2.2 Register Configuration ...................................................................................................... 36
2.2.1 Privileged Mode and Banks ................................................................................. 36
2.2.2 General Registers ................................................................................................. 39
2.2.3 Floating-Point Registers....................................................................................... 41
2.2.4 Control Registers.................................................................................................. 43
2.2.5 System Registers .................................................................................................. 44
2.3 Memory-Mapped Registers............................................................................................... 46
2.4 Data Format in Registers................................................................................................... 47
2.5 Data Formats in Memory .................................................................................................. 47
2.6 Processor States................................................................................................................. 48
2.7 Processor Modes................................................................................................................ 49
Section 3 Memory Management Unit (MMU)......................................................... 51
3.1 Overview........................................................................................................................... 51
3.1.1 Features................................................................................................................ 51
3.1.2 Role of the MMU................................................................................................. 51
3.1.3 Register Configuration......................................................................................... 54
3.1.4 Caution................................................................................................................. 54
3.2 Register Descriptions......................................................................................................... 55
3.3 Address Space ................................................................................................................... 58
3.3.1 Physical Address Space........................................................................................ 58
3.3.2 External Memory Space....................................................................................... 61
3.3.3 Virtual Address Space.......................................................................................... 62
3.3.4 On-Chip RAM Space........................................................................................... 63
3.3.5 Address Translation.............................................................................................. 63
3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode.................... 64
3.3.7 Address Space Identifier (ASID).......................................................................... 64
3.4 TLB Functions................................................................................................................... 65
3.4.1 Unified TLB (UTLB) Configuration.................................................................... 65

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3.4.2 Instruction TLB (ITLB) Configuration................................................................ 69
3.4.3 Address Translation Method................................................................................ 69
3.5 MMU Functions................................................................................................................72
3.5.1 MMU Hardware Management ............................................................................. 72
3.5.2 MMU Software Management............................................................................... 72
3.5.3 MMU Instruction (LDTLB)................................................................................. 72
3.5.4 Hardware ITLB Miss Handling............................................................................ 73
3.5.5 Avoiding Synonym Problems .............................................................................. 74
3.6 MMU Exceptions.............................................................................................................. 75
3.6.1 Instruction TLB Multiple Hit Exception.............................................................. 75
3.6.2 Instruction TLB Miss Exception.......................................................................... 75
3.6.3 Instruction TLB Protection Violation Exception.................................................. 76
3.6.4 Data TLB Multiple Hit Exception........................................................................ 77
3.6.5 Data TLB Miss Exception.................................................................................... 78
3.6.6 Data TLB Protection Violation Exception........................................................... 79
3.6.7 Initial Page Write Exception ................................................................................ 79
3.7 Memory-Mapped TLB Configuration............................................................................... 80
3.7.1 ITLB Address Array............................................................................................. 81
3.7.2 ITLB Data Array 1............................................................................................... 82
3.7.3 ITLB Data Array 2............................................................................................... 83
3.7.4 UTLB Address Array........................................................................................... 83
3.7.5 UTLB Data Array 1.............................................................................................. 85
3.7.6 UTLB Data Array 2.............................................................................................. 86
Section 4 Caches................................................................................................................ 87
4.1 Overview........................................................................................................................... 87
4.1.1 Features................................................................................................................ 87
4.1.2 Register Configuration......................................................................................... 88
4.2 Register Descriptions......................................................................................................... 89
4.3 Operand Cache (OC)......................................................................................................... 91
4.3.1 Configuration ....................................................................................................... 91
4.3.2 Read Operation..................................................................................................... 94
4.3.3 Write Operation.................................................................................................... 95
4.3.4 Write-Back Buffer................................................................................................ 97
4.3.5 Write-Through Buffer .......................................................................................... 97
4.3.6 RAM Mode .......................................................................................................... 97
4.3.7 OC Index Mode.................................................................................................... 99
4.3.8 Coherency between Cache and External Memory ............................................... 99
4.3.9 Prefetch Operation................................................................................................ 99
4.4 Instruction Cache (IC).......................................................................................................99
4.4.1 Configuration ....................................................................................................... 99
4.4.2 Read Operation..................................................................................................... 102
4.4.3 IC Index Mode ..................................................................................................... 102

Rev. 3.0, 04/02, page vii of xxxviii
4.5 Memory-Mapped Cache Configuration (SH7751)............................................................ 103
4.5.1 IC Address Array ................................................................................................. 103
4.5.2 IC Data Array....................................................................................................... 104
4.5.3 OC Address Array................................................................................................ 105
4.5.4 OC Data Array ..................................................................................................... 106
4.6 Memory-Mapped Cache Configuration (SH7751R) ......................................................... 107
4.6.1 IC Address Array ................................................................................................. 108
4.6.2 IC Data Array....................................................................................................... 109
4.6.3 OC Address Array................................................................................................ 110
4.6.4 OC Data Array ..................................................................................................... 111
4.6.5 Summary of Memory-Mapped OC Addresses..................................................... 112
4.7 Store Queues ..................................................................................................................... 113
4.7.1 SQ Configuration ................................................................................................. 113
4.7.2 SQ Writes............................................................................................................. 113
4.7.3 Transfer to External Memory............................................................................... 113
4.7.4 Determination of SQ Access Exception............................................................... 115
4.7.5 SQ Read (SH7751R only).................................................................................... 115
4.7.6 SQ Usage Notes ................................................................................................... 116
Section 5 Exceptions......................................................................................................... 119
5.1 Overview........................................................................................................................... 119
5.1.1 Features................................................................................................................ 119
5.1.2 Register Configuration......................................................................................... 119
5.2 Register Descriptions......................................................................................................... 120
5.3 Exception Handling Functions.......................................................................................... 121
5.3.1 Exception Handling Flow..................................................................................... 121
5.3.2 Exception Handling Vector Addresses................................................................. 121
5.4 Exception Types and Priorities.......................................................................................... 122
5.5 Exception Flow ................................................................................................................. 125
5.5.1 Exception Flow .................................................................................................... 125
5.5.2 Exception Source Acceptance.............................................................................. 126
5.5.3 Exception Requests and BL Bit............................................................................ 128
5.5.4 Return from Exception Handling ......................................................................... 128
5.6 Description of Exceptions ................................................................................................. 128
5.6.1 Resets ................................................................................................................... 129
5.6.2 General Exceptions .............................................................................................. 134
5.6.3 Interrupts.............................................................................................................. 148
5.6.4 Priority Order with Multiple Exceptions.............................................................. 151
5.7 Usage Notes....................................................................................................................... 152
5.8 Restrictions........................................................................................................................ 153
Section 6 Floating-Point Unit........................................................................................ 155
6.1 Overview........................................................................................................................... 155

Rev. 3.0, 04/02, page viii of xxxviii
6.2 Data Formats ..................................................................................................................... 155
6.2.1 Floating-Point Format.......................................................................................... 155
6.2.2 Non-Numbers (NaN)............................................................................................ 157
6.2.3 Denormalized Numbers........................................................................................ 158
6.3 Registers............................................................................................................................ 159
6.3.1 Floating-Point Registers....................................................................................... 159
6.3.2 Floating-Point Status/Control Register (FPSCR)................................................. 161
6.3.3 Floating-Point Communication Register (FPUL)................................................. 162
6.4 Rounding........................................................................................................................... 162
6.5 Floating-Point Exceptions................................................................................................. 163
6.6 Graphics Support Functions.............................................................................................. 164
6.6.1 Geometric Operation Instructions ........................................................................ 164
6.6.2 Pair Single-Precision Data Transfer..................................................................... 166
Section 7 Instruction Set.................................................................................................. 167
7.1 Execution Environment..................................................................................................... 167
7.2 Addressing Modes............................................................................................................. 169
7.3 Instruction Set ................................................................................................................... 173
Section 8 Pipelining.......................................................................................................... 187
8.1 Pipelines............................................................................................................................ 187
8.2 Parallel-Executability........................................................................................................ 194
8.3 Execution Cycles and Pipeline Stalling............................................................................. 198
Section 9 Power-Down Modes...................................................................................... 215
9.1 Overview........................................................................................................................... 215
9.1.1 Types of Power-Down Modes.............................................................................. 215
9.1.2 Register Configuration......................................................................................... 217
9.1.3 Pin Configuration................................................................................................. 217
9.2 Register Descriptions......................................................................................................... 218
9.2.1 Standby Control Register (STBCR)..................................................................... 218
9.2.2 Peripheral Module Pin High Impedance Control................................................. 220
9.2.3 Peripheral Module Pin Pull-Up Control............................................................... 220
9.2.4 Standby Control Register 2 (STBCR2)................................................................ 221
9.2.5 Clock Stop Register 00 (CLKSTP00) .................................................................. 222
9.2.6 Clock Stop Clear Register 00 (CLKSTPCLR00)................................................. 223
9.3 Sleep Mode........................................................................................................................ 224
9.3.1 Transition to Sleep Mode..................................................................................... 224
9.3.2 Exit from Sleep Mode.......................................................................................... 224
9.4 Deep Sleep Mode .............................................................................................................. 224
9.4.1 Transition to Deep Sleep Mode............................................................................ 224
9.4.2 Exit from Deep Sleep Mode................................................................................. 225
9.5 Pin Sleep Mode ................................................................................................................. 225

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9.5.1 Transition to Pin Sleep Mode............................................................................... 225
9.5.2 Exit from Pin Sleep Mode.................................................................................... 225
9.6 Standby Mode ................................................................................................................... 225
9.6.1 Transition to Standby Mode................................................................................. 225
9.6.2 Exit from Standby Mode...................................................................................... 226
9.6.3 Clock Pause Function........................................................................................... 227
9.7 Module Standby Function................................................................................................. 227
9.7.1 Transition to Module Standby Function............................................................... 227
9.7.2 Exit from Module Standby Function.................................................................... 228
9.8 Hardware Standby Mode................................................................................................... 229
9.8.1 Transition to Hardware Standby Mode ................................................................ 229
9.8.2 Exit from Hardware Standby Mode ..................................................................... 229
9.8.3 Usage Notes.......................................................................................................... 230
9.9 STATUS Pin Change Timing............................................................................................ 230
9.9.1 In Reset................................................................................................................. 230
9.9.2 In Exit from Standby Mode.................................................................................. 231
9.9.3 In Exit from Sleep Mode...................................................................................... 233
9.9.4 In Exit from Deep Sleep Mode............................................................................. 236
9.9.5 Hardware Standby Mode Timing......................................................................... 238
Section 10 Clock Oscillation Circuits............................................................................ 241
10.1 Overview........................................................................................................................... 241
10.1.1 Features................................................................................................................ 241
10.2 Overview of CPG.............................................................................................................. 243
10.2.1 Block Diagram of CPG........................................................................................ 243
10.2.2 CPG Pin Configuration ........................................................................................ 246
10.2.3 CPG Register Configuration ................................................................................ 246
10.3 Clock Operating Modes..................................................................................................... 247
10.4 CPG Register Description ................................................................................................. 249
10.4.1 Frequency Control Register (FRQCR)................................................................. 249
10.5 Changing the Frequency.................................................................................................... 251
10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is Off)............ 251
10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is On)............. 251
10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 is On)....................... 252
10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 is Off)...................... 252
10.5.5 Changing CPU or Peripheral Module Clock Division Ratio................................ 252
10.6 Output Clock Control........................................................................................................ 253
10.7 Overview of Watchdog Timer........................................................................................... 253
10.7.1 Block Diagram ..................................................................................................... 253
10.7.2 Register Configuration......................................................................................... 254
10.8 WDT Register Descriptions .............................................................................................. 254
10.8.1 Watchdog Timer Counter (WTCNT)................................................................... 254
10.8.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 255