Holtek HT82M75REW User manual

HT82M75REW/HT82K75REW
2.4GHz Transceiver 8-Bit OTP MCU
Rev. 1.00 1 June 11, 2010
General Description
The device is an 8-bit high performance, RISC architec-
ture microcontroller devices specifically designed for
multiple I/O, mouse/keyboard appliances and SPI con-
trol product applications. The advantages of low power
consumption, I/O flexibility, Timer functions, Watchdog
timer, Power Down, wake-up functions together with the
optional peripherals such as EEPROM Memory and RF
transceiver provide the devices with versatility for indus-
trial control, consumer products, subsystem controllers,
RF module control, etc.
Features
·Operating voltage:
fSYS= 6MHz: 1.8V~3.3V
·Internal 6MHz RC oscillator for fSYS
·Power down and wake-up functions to reduce
power consumption
·Two bit to define microcontroller system clock
(fSYS/1, fSYS/2, fSYS/4)
·All instructions executed in one or two machine
cycles
·Table read instructions
·63 powerful instructions
·6-level subroutine nesting
·Bit manipulation instruction
·Program Memory: 4K´15
·Data Memory: 128´8~160´8
·Watchdog Timer function
·Up to 40 bidirectional I/O lines with pull-high options
·All I/O pins have falling and rising edge wake-up
function
·Single 16-bit internal timer with overflow interrupt
and timer input
·Low voltage reset function (LVR) for DC_DC output
controlled by configuration option
·Built-in DC/DC to provide stable 2.8V, 3.0V, 3.3V
with error ±5% selected by configuration options
·Low voltage detector (LVD) with levels
1.8V/2.0V/2.2V/2.5V/2.8V ±5% for battery input
(BAT_IN) selected by application program
·Wide range of available package types
·EEPROM Memory with 128´8 capacity
·RF Transceiver with 2.4GHz RF frequency
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Selection Table
Part No. Program
Memory
Data
Memory
Data
EEPROM I/O Timer DC/DC
Converter
SPI
Interface
RF
Transceiver
Built-in
OSC Stack Package
HT82M75REW 4K´15 128´8 128´8 15 16-bit´1ÖÖÖÖ640QFN
(6´6´0.85mm)
HT82K75REW 4K´15 160´8 128´8 31 16-bit´1ÖÖ Ö Ö6 64LQFP
Note: 1. There are additional peripherals named RF Transceiver with RF frequency of 2.4GHz and Data EEPROM
with capacity of 128 bytes in HT82M75REW and HT82K75REW devices. All information related to the
RF Transceiver and EEPROM Data Memory will be described in the corresponding section respectively.
2. As devices exist in more than one package format, the table reflects the situation for the package with the
most pins.
Block Diagram
Pin Assignment
HT82M75REW/HT82K75REW
Rev. 1.00 2 June 11, 2010
1 6 - b i t
T i m e r
S P I
I n t e r f a c e
I/O
P o r t s
O T P
P r o g r a m M e m o r y
R A M
D a t a M e m o r y
S t a c k
8 - b i t
R I S o r e
I n t e r r u p t
o n t r o l l e r
R e s e t
i r c u i t
W a t c h d o g
T i m e r
W a t c h d o g T i m e r
O s c i l l a t o r
V o l t a g e
D e t e c t o r
I n t e r n a l
R O s c i l l a t o r D / D
R F
T r a n s m i t t e r
E E P R O M
D a t a M e m o r y
4 7
4 6
4 5
4 4
4 3
4 2
4 1
2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 94 8
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 61 7 1 8 1 9 2 0
H T 8 2 K 7 5 R E W
6 4 L Q F P - A
P A 6
P A 7
P D 0
P D 1
P D 2
P D 3
P D 4
P D 5
P D 6
P D 7
G P I O 2
G N D _ D
G P I O 1
G P I O 0
V D D _ D
V D D _ 2 V 2
P B 3
P B 2
P B 1
P E 0
P E 1
P E 2
P E 3
P E 4
P E 5
P E 6
P E 7
V S S
V D D
V D D _ R F 2
N
R F _ N
P B 4 P B 5 P B 6 P B 7
L X
V S S L X
B A T _ I N
V D D
V S S
R E S
P A 0 P A 1 P A 2 P A 3 P A 4 P A 5
R F _ P N V D D _ R F I D B 5 L O O P _ D B 5 V D D _ V O V D D _ P V D D _ P L L G D N _ P L L
X T A L _ P X T A L _ N D B 4 V D D _ A V D D _ G R / V D D _ B G V D D _ 3 V
H T 8 2 M 7 5 R E W
4 0 Q F N - A
R F _ N
V D D _ R F 2
N
V D D
V S S
V D D
B A T _ I N
V S S L X
L X
R E S
V D D _ 3 V / V D D _ G R / V D D _ B G
V D D _ A
X T A L _ N
X T A L _ P
V D D _ P L L
V D D _ P
V D D _ V O
L O O P _
V D D _ R F 1
R F _ P
P B 6 P B 7 P A 0 P A 1 P A 2 / T M R P A 3 R A 4 P A 5
P A 6 P A 7
1
2
3
4
5
6
7
8
9
1 0
1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 13 23 33 43 53 63 73 83 94 0 V D D _ 2 V 2
V D D _ D
G P I O 0
G P I O 1
G P I O 2
P B 1
P B 2
P B 3
P B 4
P B 5
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Pin Description
The following table only includes the pins which are directly related to the MCU. The pin descriptions of the additional
peripheral functions are located at the corresponding section of the datasheet along with the relevant peripheral func-
tion functional description.
Pin Name I/O Options Description
PA0~PA1
PA2/TMR
PA3~PA7
I/O Pull-high
Wake-up
Bidirectional 8-bit input/output port. Each pin can be configured as a
wake-up input (both falling and rising edge) by a configuration option. Soft-
ware instructions determine if the pin is a CMOS output or Schmitt Trigger
input. Configuration options determine if the pins have pull-high resistors.
PA2 is shared with the external timer input pin TMR.
PB0/SCS
PB1~PB7 I/O
Pull-high or
Wake-up
CMOS/NMO
S
Bidirectional 8-bit input/output port. Each pin can be configured as a
wake-up input (both falling and rising edge) by a configuration option. Soft-
ware instructions determine if the pin is a CMOS output or Schmitt Trigger
input. Configuration options determine if the pins have pull-high resistors.
Also a configuration option determines if the PB0 is a CMOS output type or
NMOS output type. PB0 is shared with SCS of the SPI interface.
PC0~PC1
PC2/INT
PC3~PC4
PC5/SDI
PC6/SDO
PC7/SCK
I/O
Pull-high or
Wake-up
CMOS/NMO
S
Bidirectional 8-bit input/output port. Each pin can be configured as a
wake-up input (both falling and rising edge) by a configuration option. Soft-
ware instructions determine if the pin is a CMOS output or Schmitt Trigger
input. Configuration options determine if the pins have pull-high resistors.
Also a configuration option determines if the PC pins are CMOS output type
or NMOS output type. The INT is shared with PC2, PC5~PC7 are shared
with the SPI interface.
PD0~PD7
(HT82K75R only) I/O Pull-high or Wake-up
Bidirectional 8-bit input/output port. Each nibble can be configured as
wake-up inputs (both falling and rising edge) by a configuration option. Soft-
ware instructions determine if the pin is a CMOS output or Schmitt Trigger
input. Configuration options determine if the pins have pull-high resistors.
PE0~PE7
(HT82K75R only) I/O Pull-high or Wake-up
Bidirectional 8-bit input/output port. Each nibble can be configured as
wake-up inputs (both falling and rising edge) by a configuration option. Soft-
ware instructions determine if the pin is a CMOS output or Schmitt Trigger
input. Configuration options determine if the pins have pull-high resistors.
VSS ¾¾ Negative power supply, ground
RES I¾Schmitt Trigger reset input. Active low
VDD ¾¾ Positive power supply
BAT_IN I ¾Battery input
LX I ¾DC/DC LX switch
VSSLX I ¾DC/DC ground
HT82M75REW/HT82K75REW
Rev. 1.00 3 June 11, 2010
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Pin Description for EEPROM Memory
Pin Name Type Description
VDDP ¾External Positive power supply for EEPROM Memory
VSSP ¾External Negative power supply for EEPROM Memory, ground
SDA I/O Internal Serial data input/output signal
Internal connected with MCU I/O line.
SCL I Serial clock input signal
Internal connected with MCU I/O line.
NC ¾Implies that the pin is ²Not Connected²and can therefore not be used.
Note: The pin descriptions for all external pins with the exception of the EEPROM VDDP and VSSP pins are
described in the preceding MCU section.
VDDP and VSSP should be externally connected to the MCU power supply named VDD and VSS respectively.
The SDA and SCL lines here are internal connected to the MCU I/O pins PC0 and PC1 respectively for these
devices.
Pin Description for RF Transceiver
Pin Name Type Description
RF_P I/O External Differential RF input/output (+)
RF_N I/O External Differential RF input/output (-)
VDD_RF1 I External RF transceiver power supply (1)
VDD_RF2 I External RF transceiver power supply (1)
GPIO0
GPIO1 I/O External General Purpose digital I/O It is also used as an external TX/RX switch control
GPIO2 I/O External General Purpose digital I/O
It is also used as an external Power Amplifier (P.A.) enable control.
VDD_D I External RF transceiver digital circuit power supply (+)
GND_D I External RF transceiver digital circuit power supply (-)
VDD_2V2 O External RF transceiver DC-DC output voltage
It cannot be used.
VDD_3V I External RF transceiver 3V input for a DC-DC regulator
GND_GR ¾External RF transceiver Guard-Ring ground
VDD_A I External RF transceiver power supply for analog circuits (1)
XTAL_P I External RF transceiver 32MHz Crystal input (+)
XTAL_N I External RF transceiver 32MHz Crystal input (-)
VDD_PLL I External RF transceiver PLL power supply (1)
VDD_CP I External RF transceiver Charge pump power supply (1)
VDD_VCO I External RF transceiver Voltage-controlled oscillator power supply (1)
LOOP_C I/O External RF transceiver PLL loop filter external capacitor
It is connected to the external 47pF capacitor.
VDD_GR I External RF transceiver Guard-Ring power supply (1)
VDD_BG O External RF transceiver Bandgap power supply (1)
DB4 I External Test pin
It is connected to ground.
DB5 I External Test pin
It is connected to ground.
HT82M75REW/HT82K75REW
Rev. 1.00 4 June 11, 2010
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Pin Name Type Description
SI I Internal RF Transceiver Slave SPI Serial Data Input Signal
Internally connected to the MCU Master SPI SDO output signal
SO O Internal RF Transceiver Slave SPI Serial Data Output Signal
Internally connected to the MCU Master SPI SDI input signal
SCLK I Internal RF Transceiver Slave SPI Serial Clock Input Signal
Internally connected to the MCU Master SPI SCK output signal
SEN I Internal RF Transceiver Slave SPI Serial interface Enable Input Signal
Internally connected to the MCU Master SPI SCS output signal
INT IInternal RF Transceiver Interrupt Output Signal
Internally connected to the MCU INT input signal
RST IInternal RF Transceiver global hardware reset input signal, active low.
Internally connected to the MCU I/O pin configured as output type.
NC ¾Implies that the pin is ²Not Connected²and can therefore not be used.
Notes: (1) Connecting bypass capacitor(s) as close to the pin as possible.
(2) The pin descriptions for all external pins except the RF Transceiver pins listed in the above table are de-
scribed in the preceding MCU section.
(3) The INT and RST lines are internally connected to the MCU I/O pins PC2 and PC3 respectively for the
HT82M75REW and HT82K75REW devices.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°Cto125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-40°Cto85°C
IOL Total ..............................................................150mA IOH Total............................................................-100mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings²may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics Ta=25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
VBAT BAT_IN Operating Voltage ¾¾ 1.8 2.2 3.3 V
IDD Operating Current (Crystal OSC) 3V No load, fSYS= 6MHz ¾36mA
ISTB Standby Current ¾No load, system HALT
WDT disable, LVR disable ¾¾
20 mA
VIL1 Input Low Voltage for I/O
(Schmitt Trigger) ¾¾ 0¾0.3VDD V
VIH1 Input High Voltage for I/O
(Schmitt Trigger) ¾¾
0.7VDD ¾VDD V
VIL2 Input Low Voltage (RES) ¾¾ 0¾0.3VDD V
VIH2 Input High Voltage (RES) ¾¾
0.9VDD ¾VDD V
IOL1 Other I/O Pins Sink Current 3V VOL=0.1VDD 4¾¾
mA
IOH1 Other I/O Pins Source Current 3V VOH=0.9VDD -2.5 -4.5 ¾mA
RPH1 Other Pins Internal Pull-high
Resistance 3V ¾10 30 50 kW
HT82M75REW/HT82K75REW
Rev. 1.00 5 June 11, 2010
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D.C. Characteristics for EEPROM Memory Ta= -40°C~85°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VCC Conditions
ICC1*Operating Current 3V Read at 100kHz ¾¾ 1mA
ICC2*Operating Current 3V Write at 100kHz ¾¾ 3mA
ISTB* Standby Current 3V VIN=0 or VCC ¾¾ 3mA
Note: ²*²The operating current ICC1 and ICC2 listed here are the additional currents consumed when the EEPROM
Memory operates in Read Operation and Write Operation respectively. If the EEPROM is operating, the ICC1
or ICC2 should be added to calculate the relevant operating current of the device for different conditions. To
calculate the standby current for the whole device, the standby current shown above should also be taken into
account.
A.C. Characteristics Ta= -40°C~85°C
Symbol Parameter Remark Standard Mode* Unit
Min. Max.
fSK SCL Clock Frequency ¾¾
100 kHz
tHIGH Clock High Time ¾4000 ¾ns
tLOW Clock Low Time ¾4700 ¾ns
trSDA and SCL Rise Time Note ¾1000 ns
tfSDA and SCL Fall Time Note ¾300 ns
tHD:STA START Condition Hold Time After this period the first clock
pulse is generated 4000 ¾ns
tSU:STA START Condition Setup Time Only relevant for repeated START
condition 4000 ¾ns
tHD:DAT Data Input Hold Time ¾0¾ns
tSU:DAT Data Input Setup Time ¾200 ¾ns
tSU:STO STOP Condition Setup Time ¾4000 ¾ns
tAA Output Valid from Clock ¾¾
3500 ns
tBUF Bus Free Time Time in which the bus must be free
before a new transmission can start 4700 ¾ns
tSP Input Filter Time Constant
(SDA and SCL Pins) Noise suppression time ¾100 ns
tWR Write Cycle Time ¾¾
5ms
Note: These parameters are periodically sampled but not 100% tested
* The standard mode means VCC=2.2V to 3.6V
For relative timing, refer to timing diagrams
HT82M75REW/HT82K75REW
Rev. 1.00 6 June 11, 2010
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A.C. Characteristics for EEPROM Memory Ta=25°C
Symbol Parameter
Test Conditions
Min. Typ. Max. Unit
VDD Conditions
fSYS System Clock 3V ¾5.7 6 6.3 MHz
tRCSYS Watchdog OSC Period 3V ¾¾
71 ¾ms
tWDT1 Watchdog Time-out Period with
6-stage Prescaler 3V WDTS=1 ¾4.57 ¾ms
tRES External Reset Low Pulse Width ¾¾ 1¾¾
ms
tSST System Start-up Timer ¾¾ ¾
512 ¾1/fSYS
tLVR Low Voltage Width to Reset ¾¾ 0.25 1 2 ms
tWake-up MCU Wake-up Timer ¾¾ ¾¾
1ms
tconfigure Watchdog Time-out Period ¾¾ ¾
1024 ¾tRCSYS
Power-On Reset Characteristics Ta=25°C
Symbol Parameter
Test Conditions
Min. Typ. Max. Unit
VDD Conditions
IPOR Operating current 1.8V~
3.3V ¾¾
1.0 ¾mA
RRVDD VDD Rise Rate to Ensure
Power-on Reset ¾Without 0.1mF between
VDD and VSS
0.05 ¾¾ V/ms
VPOR Maximum VDD Start Voltage to
Ensure Power-on Reset ¾Without 0.1mF between
VDD and VSS ,Ta=25°C0.9 ¾1.5 V
tPOR Power-on Reset Low Pulse
Width ¾
Without 0.1mF between
VDD and VSS
2¾¾ms
With 0.1mF between
VDD and VSS
10 ¾¾ms
HT82M75REW/HT82K75REW
Rev. 1.00 7 June 11, 2010
T i m e
V
D D
V
P O R
R R
V D D
t
P O R
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RF Transceiver D.C. Characteristics VDD=3V, Ta=25°C
Symbol Test Conditions Min. Typ. Max. Unit
ITX RF Transceiver TX Active. At 0 dBm output power DC-DC
Off* ¾21 30 mA
IRX
RF Transceiver RX Active in Normal Mode (250 Kbps) DC-DC
Off* ¾19 28 mA
RF Transceiver RX Active in Turbo Mode (1M bps) DC-DC
Off* ¾21 30 mA
ISTB RF Transceiver in STANDBY mode. Partial 32MHz clock and Sleep
clock remains active. RF/MAC/BB, system clock shutdown. ¾60 80 mA
IDS
RF Transceiver in DEEP_SLEEP mode. Power to digital circuit re-
mains active to retain Registers and FIFOs. All the other power is
shutdown.
¾3.2 10.0 mA
IPD
RF Transceiver in POWER_DOWN mode. Minimum wake-up cir-
cuit remains active. All power is shutdown. Register and FIFO data
are not retained.
¾0.6 2.0 mA
Note: ²*²The operating current ITX or IRX listed here is the additional current consumed when the RF Transceiver op-
erates in Active TX mode or Active RX mode. If the RF Transceiver is active, either ITX or IRX should be added
to calculate the relevant operating current of the device for different operating mode. To calculate the standby
current for the whole device, the standby current shown above including ISTB,I
DS and IPD should be taken into
account for different Power Saving Mode.
RF Transceiver A.C. Characteristics VDD=3V, Ta=25°C, LO frequency=2.445GHz, DC-DC Off
Receiver
Parameters Test Conditions Min. Typ. Max. Unit
RF Input Frequency ¾2.400 ¾2.495 GHz
RF Sensitivity At antenna input with O-QPSK
signal, PER £0.1%
250Kbps ¾-90 ¾dBm
1 Mbps ¾-80 ¾dBm
Maximum RF Input ¾¾ 5¾dBm
Adjacent Channel Rejection @±5MHz, 250Kbps
(-82dBm + 20 dB = -62dBm) ¾20
-62 ¾dBc dBm
Alternative Channel Rejection @±10 MHz, 250Kbps
(-82dBm + 40 dB = -42dBm) ¾40
-42 ¾dBc dBm
LO Leakage
Measured at the balun matching the
network with the input frequency at
2.4~2.5GHz
¾-60 ¾dBm
Noise figure
(Including matching) ¾¾
8¾dB
HT82M75REW/HT82K75REW
Rev. 1.00 8 June 11, 2010
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Transmitter VDD=3V, Ta=25°C, LO frequency=2.445GHz, 250 Kbps, DC-DC Off
Parameters Test Conditions Min. Typ. Max. Unit
RF carrier frequency ¾2.400 ¾2.495 GHz
Maximum RF output power At 0 dBm output power setting -3 0 ¾dBm
RF output power Accuracy ¾¾¾±4dBm
RF output power control range ¾¾ 36 ¾dB
TX gain control resolution ¾0.1 ¾0.5 dB
Carrier suppression ¾¾ -30 ¾dBc
TX spectrum mask for O-QPSK signal Offset frequency > 3.5 MHz
At 0 dBm output power
¾¾
-30 dBm
¾¾
-20 dBc
TX EVM ¾¾ 30 ¾%
Synthesizer VDD=3V, Ta=25°C, LO frequency=2.445GHz, 250 Kbps, DC-DC Off
Parameters Test Conditions Min. Typ. Max. Unit
PLL Stable Time ¾¾ 130 ¾ms
PLL Programming resolution ¾¾ 1¾MHz
HT82M75REW/HT82K75REW
Rev. 1.00 9 June 11, 2010
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HT82M75REW/HT82K75REW
Rev. 1.00 10 June 11, 2010
System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to the inter-
nal system architecture. The devices take advantage of
the usual features found within RISC microcontrollers
providing increased speed of operation and enhanced
performance. The pipelining scheme is implemented in
such a way that instruction fetching and instruction exe-
cution are overlapped, hence instructions are effectively
executed in one cycle, with the exception of branch or
call instructions. An 8-bit wide ALU is used in practically
all operations of the instruction set. It carries out arith-
metic operations, logic operations, rotation, increment,
decrement, branch decisions, etc. The internal data
path is simplified by moving data through the Accumula-
tor and the ALU. Certain internal registers are imple-
mented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural fea-
tures ensure that a minimum of external components is
required to provide a functional I/O control system with
maximum reliability and flexibility.
Clocking and Pipelining
The main system clock, derived from either a Crys-
tal/Resonator or RC oscillator is subdivided into four in-
ternally generated non-overlapping clocks, T1~T4. The
Program Counter is incremented at the beginning of the
T1 clock during which time a new instruction is fetched.
The remaining T2~T4 clocks carry out the decoding and
execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive in-
struction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions where the contents of the Program
Counter are changed, such as subroutine calls or
jumps, in which case the instruction will take one more
instruction cycle to execute.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to com-
plete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications
Program Counter
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP²or ²CALL²that demand a jump to a
non-consecutive Program Memory address. It must be
noted that only the lower 8 bits, known as the Program
Counter Low Register, are directly addressable by user.
F e t c h I n s t . ( P )
E x e c u t e I n s t . ( P - 1 ) F e t c h I n s t . ( P + 1 )
E x e c u t e I n s t . ( P ) F e t c h I n s t . ( P + 2 )
E x e c u t e I n s t . ( P + 1 )
P P + 1 P + 2
S y s t e m l o c k
P h a s e l o c k T 1
P r o g r a m o u n t e r
P h a s e l o c k T 2
P h a s e l o c k T 3
P h a s e l o c k T 4
P i p e l i n i n g
System Clocking and Pipelining
F e t c h I n s t . 1 E x e c u t e I n s t . 1
F e t c h I n s t . 2
F l u s h P i p e l i n e
1
2
3
4
5
6D E L A Y :
M O V A , [ 1 2 H ]
A L L D E L A Y
P L [ 1 2 H ]
:
:
N O P
E x e c u t e I n s t . 2
F e t c h I n s t . 3
F e t c h I n s t . 6 E x e c u t e I n s t . 6
F e t c h I n s t . 7
Instruction Fetching
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HT82M75REW/HT82K75REW
Rev. 1.00 11 June 11, 2010
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For condi-
tional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is dis-
carded and a dummy cycle takes its place while the cor-
rect instruction is obtained.
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writeable regis-
ter. By transferring data directly into this register, a short
program jump can be executed directly, however, as
only this low byte is available for manipulation, the
jumps are limited to the present page of memory, that is
256 locations. When such program jumps are executed
it should also be noted that a dummy cycle will be in-
serted.
The lower byte of the Program Counter is fully accessi-
ble under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
Stack
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack has 6 levels and is neither part of the data nor part
of the program space, and is neither readable nor
writeable. The activated level is indexed by the Stack
Pointer, SP, and is neither readable nor writeable. At a
subroutine call or interrupt acknowledge signal, the con-
tents of the Program Counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, sig-
naled by a return instruction, RET or RETI, the Program
Counter is restored to its previous value from the stack.
After a device reset, the Stack Pointer will point to the
top of the stack.
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the ac-
knowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine in-
struction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
Mode
Program Counter Bits
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Initial Reset 0 00000000000
SPI Interrupt 0 00000000100
Timer/Event Counter Overflow 0 00000001000
External interrupt 0 00000001100
Skip Program Counter + 2
Loading PCL PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Program Counter
Note: PC11~PC8: Current Program Counter bits @7~@0: PCL bits
#11~#0: Instruction code address bits S11~S0: Stack register bits
P r o g r a m o u n t e r
S t a c k L e v e l 1
S t a c k L e v e l 2
S t a c k L e v e l 3
S t a c k L e v e l 6
P r o g r a m
M e m o r y
T o p o f S t a c k
S t a c k
P o i n t e r
B o t t o m o f S t a c k
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Arithmetic and Logic Unit -ALU
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic op-
erations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related in-
struction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or oper-
ations may result in carry, borrow or other status
changes, the status register will be correspondingly up-
dated to reflect these changes. The ALU supports the
following functions:
·Arithmetic operations: ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
·Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
·Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
·Increment and Decrement INCA, INC, DECA, DEC
·Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
SIZA, SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user
code or program is stored. The device is supplied with
One-Time Programmable, OTP, memory where users
can program their application code into the device. By
using the appropriate programming tools, OTP devices
offer users the flexibility to freely develop their applica-
tions which may be useful during debug or for products
requiring frequent upgrades or program changes. OTP
devices are also applicable for use in applications that
require low or medium volume production runs.
Structure
The Program Memory has a capacity of 4K´15 bits. The
Program Memory is addressed by the Program Counter
and also contains data, table information and interrupt
entries. Table data, which can be setup in any location
within the Program Memory, is addressed by separate
table pointer registers.
Special Vectors
Within the Program Memory, certain locations are re-
served for special usage such as reset and interrupts.
·Location 000H
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated,
the program will jump to this location and begin execu-
tion.
·Location 004H
This vector is used by serial interface. When 8-bits of
data have been received or transmitted success-fully
from serial interface. The program will jump to this lo-
cation and begin execution if the interrupt is enable
and the stack is not full.
·Location 008H
This vector is used by the timer/event counter. If a
counter overflow occurs, the program will jump to this
location and begin execution if the timer interrupt is
enabled and the stack is not full.
·Location 00CH
This vector is used by the external interrupt. If the INT
external input pin on the device receives a high to low
transition, the program will jump to this location and
begin execution, if the interrupt is enabled and the
stack is not full.
·Table location
Any location in the program memory can be used as
look-up tables. There are three method to read the
ROM data by two table read instructions: ²TABRDC²
and ²TABRDL², transfer the contents of the
lower-order byte to the specified data memory, and
the higher-order byte to TBLH (08H).
F F F H
1 5 b i t s
SPI
I n t e r r u p t V e c t o r
T i m e r / E v e n t o u n t e r
I n t e r r u p t V e c t o r
004H
008H
0 0 H
I n i t i a l i s a t i o n
V e c t o r
000H
E x t e r n a l
I n t e r r u p t V e c t o r
Program Memory Structure
Instruction
Table Location Bits
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
TABRDC[m] PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL[m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0
Table Location
Note: PC11~PC8: Current program counter bits when TBHP is disabled
TBHP register bit3~bit0 when TBHP is enabled
@7~@0: Table Pointer TBLP bits
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HT82M75REW/HT82K75REW
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¨The three methods are shown as follows: The in-
structions ²TABRDC [m]²(the current page, one
page=256words), where the table location is de-
fined by TBLP (07H) in the current page. And the
configuration option TBHP is disabled (default).
¨The instructions ²TABRDC [m]², where the table lo-
cation is defined by registers TBLP (07H) and
TBHP (01FH). And the configuration option TBHP
is enabled.
¨The instructions ²TABRDL [m]², where the table lo-
cation is defined by register TBLP (07H) in the last
page (F00H~FFFH).
Only the destination of the lower-order byte in the ta-
ble is well-defined, the other bits of the table word are
transferred to the lower portion of TBLH, and the re-
maining 1-bit words are read as ²0². The Table
Higher-order byte register (TBLH) is read only. The ta-
ble pointer (TBLP, TBHP) is a read/write register (07H,
1FH), which indicates the table location. Before ac-
cessing the table, the location must be placed in the
TBLP and TBHP (If the configuration option TBHP is
disabled, the value in TBHP has no effect). The TBLH
is read only and cannot be restored. If the main rou-
tine and the ISR (Interrupt Service Routine) both em-
ploy the table read instruction, the contents of the
TBLH in the
main routine are likely to be changed by the table read
instruction used in the ISR. Errors can occur. In other
words, using the table read instruction in the main rou-
tine and the ISR simultaneously should be avoided.
However, if the table read instruction has to be applied
in both the main routine and the ISR, the interrupt
should be disabled prior to the table read instruction. It
will not be enabled until the TBLH has been backed
up. All table related instructions require two cycles to
complete the operation. These areas may function as
normal program memory depending on the require-
ments.
Once TBHP is enabled, the instruction ²TABRDC [m]²
reads the ROM data as defined by TBLP and TBHP
value. Otherwise, the configuration option TBHP is
disabled, the instruction ²TABRDC [m]²reads the
ROM data as defined by TBLP and the current pro-
gram counter bits.
Table Program Example
The following example shows how the table pointer and
table data is defined and retrieved from the
microcontroller. This example uses raw table data lo-
cated in the last page which is stored there using the
ORG statement. The value at this ORG statement is
²F00H²which refers to the start address of the last page
within the 4K Program Memory of device. The table
pointer is setup here to have an initial value of ²06H².
This will ensure that the first data read from the data ta-
ble will be at the Program Memory address ²F06H²or 6
locations after the start of the last page. Note that the
value for the table pointer is referenced to the first ad-
dress of the present page if the ²TABRDC [m]²instruc-
tion is being used. The high byte of the table data which
in this case is equal to zero will be transferred to the
TBLH register automatically when the ²TABRDL [m]²in-
struction is executed.
P r o g r a m
M e m o r y
P r o g r a m o u n t e r
H i g h B y t e
T B L P
T B L H S p e c i f i e d b y [ m ]
T a b l e o n t e n t s H i g h B y t e T a b l e o n t e n t s L o w B y t e
Table Read -TBLP only
P r o g r a m
M e m o r y
T B L H S p e c i f i e d b y [ m ]
H i g h B y t e o f T a b l e o n t e n t s L o w B y t e o f T a b l e o n t e n t s
T B L P
T B H P
Table Read -TBLP/TBHP
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tempreg1 db ? ; temporary register #1
tempreg2 db ? ; temporary register #2
:
:
mov a,06h ; initialise table pointer - note that this address
; is referenced
mov tblp,a ; to the last page or present page
:
:
tabrdl tempreg1 ; transfers value in table referenced by table pointer
; to tempregl
; data at prog. memory address ²F06H²transferred to
; tempreg1 and TBLH
dec tblp ; reduce value of table pointer by one
tabrdl tempreg2 ; transfers value in table referenced by table pointer
; to tempreg2
; data at prog.memory address ²F05H²transferred to
; tempreg2 and TBLH
; in this example the data ²1AH²is transferred to
; tempreg1 and data ²0FH²to register tempreg2
; the value ²00H²will be transferred to the high byte
; register TBLH
:
:
org F00h ; sets initial address of last page
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection
if both the main routine and Interrupt Service Routine use the table read instructions. If using the table read instructions,
the Interrupt Service Routines may change the value of TBLH and subsequently cause errors if used again by the main
routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However,
in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete
their operation.
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HT82M75REW/HT82K75REW
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Data Memory
The Data Memory is a volatile area of 8-bit wide RAM
internal memory and is the location where temporary in-
formation is stored. Divided into two sections, the first of
these is an area of RAM where special function registers
are located. These registers have fixed locations and
are necessary for correct operation of the device. Many
of these registers can be read from and written to di-
rectly under program control, however, some remain
protected from user manipulation. The second area of
Data Memory is reserved for general purpose use. All
locations within this area are read and write accessible
under program control.
Structure
The two sections of Data Memory, the Special Purpose
and General Purpose Data Memory are located at con-
secutive locations. All are implemented in RAM and are
8-bit wide. The start address of the Data Memory for all
devices is the address ²00H². Registers which are com-
mon to all microcontrollers, such as ACC, PCL, etc.,
have the same Data Memory address.
General Purpose Data Memory
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user pro-
gram for both read and write operations. By using the
²SET [m].i²and ²CLR [m].i²instructions, individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory.
Special Purpose Data Memory
This area of Data Memory is where registers, necessary
for the correct operation of the microcontroller, are
stored. Most of the registers are both readable and
writeable but some are protected and are readable only,
the details of which are located under the relevant Spe-
cial Function Register section. Note that for locations
that are unused, any read instruction to these addresses
will return the value ²00H².
G e n e r a l P u r p o s e
D a t a M e m o r y
S p e c i a l P u r p o s e
D a t a M e m o r y
00H
40H
D F H
3 F H
H T 8 2 K 7 5 R E W
G e n e r a l P u r p o s e
D a t a M e m o r y
S p e c i a l P u r p o s e
D a t a M e m o r y
00H
40H
B F H
3 F H
H T 8 2 M 7 5 R E W
Data Memory Structure
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HT82M75REW/HT82K75REW
Rev. 1.00 16 June 11, 2010
S p e c i a l P u r p o s e
D a t a M e m o r y
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0 A H
0 B H
0 H
0 D H
0 E H
0 F H
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1 A H
1 B H
1 H
1 D H
1 E H
1 F H
B F H
G e n e r a l P u r p o s e
D a t a M e m o r y
( 1 2 8 B y t e s )
40H
20H
21H
22H
23H
24H
S p e c i a l P u r p o s e
D a t a M e m o r y
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0 A H
0 B H
0 H
0 D H
0 E H
0 F H
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1 A H
1 B H
1 H
1 D H
1 E H
1 F H
: U n u s e d ,
r e a d a s " 0 0 "
D F H
G e n e r a l P u r p o s e
D a t a M e m o r y
( 1 6 0 B y t e s )
I A R 0
M P 0
I A R 1
M P 1
A
P L
T B L P
T B L H
W D T S
S T A T U S
I N T
T M R H
T M R L
T M R
P T R
P A
P A
P B
P B
P
P
P D
P D
P E
P E
T L R
T B H P
S P I R
S B R
S B D R
40H
20H
21H
22H
23H
24H
I A R 0
M P 0
I A R 1
M P 1
A
P L
T B L P
T B L H
W D T S
S T A T U S
I N T
T M R H
T M R L
T M R
P T R
P A
P A
P B
P B
P
P
T L R
T B H P
S P I R
S B R
S B D R
H T 8 2 M 7 5 R E W H T 8 2 K 7 5 R E W
Special Purpose Data Memory Structure
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HT82M75REW/HT82K75REW
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Special Function Registers
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the Data
Memory area. These registers ensure correct operation
of internal functions such as timers, interrupts, etc., as
well as external functions such as I/O data control. The
location of these registers within the Data Memory be-
gins at the address 00H. Any unused Data Memory lo-
cations between these special function registers and the
point where the General Purpose Memory begins is re-
served and attempting to read data from these locations
will return a value of 00H.
Indirect Addressing Register -IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, al-
though having their locations in normal RAM register
space, do not actually physically exist as normal regis-
ters. The method of indirect addressing for RAM data
manipulation uses these Indirect Addressing Registers
and Memory Pointers, in contrast to direct memory ad-
dressing, where the actual memory address is speci-
fied. Actions on the IAR0 and IAR1 registers will result in
no actual read or write operation to these registers but
rather to the memory location specified by their corre-
sponding Memory Pointer, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together only access data from
Bank 0, while the IAR1 and MP1 register pair can ac-
cess data from all of the data banks if the Data Memory
is divided into 2 or more banks. As the Indirect Ad-
dressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will
return a result of ²00H²and writing to the registers indi-
rectly will result in no operation.
Memory Pointer -MP0, MP1
For all devices, two Memory Pointers, known as MP0
and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be
manipulated in the same way as normal registers pro-
viding a convenient way with which to address and track
data. When any operation to the relevant Indirect Ad-
dressing Registers is carried out, the actual address that
the microcontroller is directed to, is the address speci-
fied by the related Memory Pointer. MP0 can only ac-
cess data in Bank 0 while MP1 can access all data
banks if the Data Memory is divided into 2 or more
banks.
data .section ¢data¢
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 ¢code¢
org 00h
start:
mov a,04h ; setup size of block
mov block,a
mov a,offset adres1; Accumulator loaded with first RAM address
mov mp,a ; setup memory pointer with first RAM address
loop:
clr IAR0 ; clear the data at address defined by MP0
inc mp0 ; increment memory pointer
sdz block ; check if last memory location has been cleared
jmp loop
continue:
The important point to note here is that in the example shown above, no reference is made to specific Data Memory ad-
dresses.
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Accumulator -ACC
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
Program Counter Low Register -PCL
To provide additional program control functions, the low
byte of the Program Counter is made accessible to pro-
grammers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily imple-
mented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory lo-
cation, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are per-
mitted. When such operations are used, note that a
dummy cycle will be inserted.
Look-up Table Registers -TBLP, TBLH, TBHP
These two special function registers are used to control
operation of the look-up table which is stored in the Pro-
gram Memory. TBLP is the table pointer and indicates
the location where the table data is located. Its value
must be setup before any table read commands are ex-
ecuted. Its value can be changed, for example using the
²INC²or ²DEC²instructions, allowing for easy table data
pointing and reading. TBLH is the location where the
high order byte of the table data is stored after a table
read data instruction has been executed. Note that the
lower order table data byte is transferred to a user de-
fined location. Once TBHP is enabled, the instruction
²TABRDC [m]²reads the ROM data as defined by TBLP
and TBHP value.
Otherwise, the configuration option TBHP is disabled,
the instruction ²TABRDC [m]²reads the ROM data as
defined by TBLP and the current program counter bits.
Status Register -STATUS
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system manage-
ment flags are used to record the status and operation of
the microcontroller.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, opera-
tions related to the status register may give different re-
sults due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT²or ²HALT²in-
struction. The PDF flag is affected only by executing the
²HALT²or ²CLR WDT²instruction or during a system
power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
·Cis set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place dur-
ing a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
·AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nib-
ble into the low nibble in subtraction; otherwise AC is
cleared.
·Zis set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
·OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
·PDF is cleared by a system power-up or executing the
²CLR WDT²instruction. PDF is set by executing the
²HALT²instruction.
·TO is cleared by a system power-up or executing the
²CLR WDT²or ²HALT²instruction. TO is set by a
WDT time-out.
T O P D F O V Z A
S T A T U S R e g i s t e r
A r i t m e t i c / L o g i c O p e r a t i o n F l a g s
a r r y f l a g
A u x i l i a r y c a r r y f l a g
Z e r o f l a g
O v e r f l o w f l a g
S y s t e m M a n a g e m e n t F l a g s
P o w e r d o w n f l a g
W a t c h d o g t i m e - o u t f l a g
N o t i m p l e m e n t e d , r e a d a s " 0 "
b 7 b 0
Status Register
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In addition, on entering an interrupt sequence or execut-
ing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the interrupt rou-
tine can change the status register, precautions must be
taken to correctly save it.
Interrupt Control Registers -INTC
The microcontroller provides an internal timer/event
counter overflow interrupt. By setting various bits within
this register using standard bit manipulation instruc-
tions, the enable/disable function of each interrupt can
be independently controlled. A master interrupt bit within
this register, the EMI bit, acts like a global enable/dis-
able and is used to set all of the interrupt enable bits on
or off. This bit is cleared when an interrupt routine is en-
tered to disable further interrupt and is set by executing
the ²RETI²instruction.
Timer/Event Counter Registers -
TMRH, TMRL, TMRC
All devices possess a single internal 16-bit count-up
timer. An associated register pair known as
TMRL/TMRH is the location where the timer 16-bit value
is located. This register can also be preloaded with fixed
data to allow different time intervals to be setup. An as-
sociated control register, known as TMRC, contains the
setup information for this timer, which determines in
what mode the timer is to be used as well as containing
the timer on/off control function.
Watchdog Timer Register -WDTS
The Watchdog function in the microcontroller provides
an automatic reset function giving the microcontroller a
means of protection against spurious jumps to incorrect
Program Memory addresses. To implement this, a timer
is provided within the microcontroller which will issue a
reset command when its value overflows.To provide
variable Watchdog Timer reset times, the Watchdog
Timer clock source can be divided by various division ra-
tios, the value of which is set using the WDTS register.
By writing directly to this register, the appropriate divi-
sion ratio for the Watchdog Timer clock source can be
setup. Note that only the lower 3 bits are used to set divi-
sion ratios between 1 and 128.
Input/Output Ports and Control Registers
Within the area of Special Function Registers, the I/O
registers and their associated control registers play a
prominent role. All I/O ports have correspondingly des-
ignated registers known as PA, PB, etc. These labeled
I/O registers are mapped to specific addresses within
the Data Memory as shown in the Data Memory table,
which are used to transfer the appropriate output or in-
put data on that port. With each I/O port there is an asso-
ciated control register known as PAC, PBC, etc., also
mapped to specific addresses with the Data Memory.
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on
their I/O ports. With the input or output designation of ev-
ery pin fully under user program control, pull-high op-
tions for all ports and Wake-up option for all I/O pins, the
user is provided with an I/O structure to meet the needs
of a wide range of application possibilities.
The microcontroller provides 24 or 40 bit bidirectional in-
put/output lines labeled with port names known as PA,
PB, etc. These I/O ports are mapped to the Data Mem-
ory with addresses as shown in the Special Purpose
Data Memory table. All of these I/O lines can be used for
input and output operations and one line as an input
only. For input operation, these ports are non-latching,
which means the inputs must be ready at the T2 rising
edge of instruction ²MOV A,[m]², where m denotes the
port address. For output operation, all the data is latched
and remains unchanged until the output latch is rewritten.
Pull-high Resistors
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an exter-
nal resistor. To eliminate the need for these external re-
sistors, I/O pins, when configured as an input have the
capability of being connected to an internal pull-high re-
sistor. The pull-high resistors are selectable via configu-
ration options and are implemented using weak PMOS
transistors. The individual pull-high resistor is selected
to be connected to each pin on Port A by a configuration
option. A configuration option can determine if the
pull-high resistors are connected to the lower significant
four pins or higher significant four pins on each I/O port
except Port A.
Port Pin Wake-up
If the HALT instruction is executed, the device will enter
the Power Down Mode, where the system clock will stop
resulting in power being conserved, a feature that is im-
portant for battery and other low-power applications.
Various methods exist to wake-up the microcontroller,
one of which is to change the logic condition on one of
the port pins from high to low. After a HALT instruction
forces the microcontroller into entering the Power Down
Mode, the processor will remain in a low-power state un-
til the logic condition of the selected wake-up pin on the
port pin changes from high to low. This function is espe-
cially suitable for applications that can be woken up via
external switches. All of the I/O pins can be configured
to have the capability to wake-up the device by high to
low and low to high edges using different configuring
ways. It means once the I/O pin is configured to have the
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HT82M75REW/HT82K75REW
Rev. 1.00 20 June 11, 2010
wake-up capability, the device can be woken up by any
I/O transition. For more details, refer to the Configura-
tion Option Section later.
I/O Port Control Registers
Each I/O port has its own control register known as PAC,
PBC, etc., to control the input/output configuration. With
this control register, each CMOS/NMOS output or input
with or without pull-high resistor structures can be re-
configured dynamically under software control. Each of
the I/O ports is directly mapped to a bit in its associated
port control register. PC and PB can be set CMOS or
NMOS output for option.
For the I/O pin to function as an input, the corresponding
bit of the control register must be written as a ²1². This
will then allow the logic state of the input pin to be di-
rectly read by instructions. When the corresponding bit
of the control register is written as a ²0², the I/O pin will
be setup as a CMOS/NMOS output. If the pin is currently
setup as an output, instructions can still be used to read
the output register. However, it should be noted that the
program will in fact only read the status of the output
data latch and not the actual logic status of the output
pin.
Pin-shared Functions
The flexibility of the microcontroller range is greatly en-
hanced by the use of pins that have more than one func-
tion. Limited numbers of pins can force serious design
constraints on designers but by supplying pins with
multi-functions, many of these difficulties can be over-
come. For some pins, the chosen function of the
multi-function I/O pins is set by configuration options
while for others the function is set by application pro-
gram control.
·External Timer Clock Input
The external timer pin TMR is pin-shared with the I/O
pin PA2. To configure this pin to operate as timer input,
the corresponding control bits in the timer control reg-
ister must be correctly set. For applications that do not
require an external timer input, this pin can be used as
a normal I/O pin. Note that if used as a normal I/O pin
the timer mode control bits in the timer control register
must select the timer mode, which has an internal
clock source, to prevent the input pin from interfering
with the timer operation.
·External Interrupt Input
The external interrupt pin INT is pin-shared with the
I/O pin PC2. For applications not requiring an external
interrupt input, the pin-shared external interrupt pin
can be used as a normal I/O pin, however to do this,
the external interrupt enable bits in the INTC register
must be disabled.
I/O Pin Structures
The diagrams illustrate the I/O pin internal structures. As
the exact logical construction of the I/O pin may differ
from these drawings, they are supplied as a guide only
to assist with the functional understanding of the I/O
pins.
Programming Considerations
Within the user program, one of the first things to con-
sider is port initialisation. After a reset, all of the data and
port control register will be set high. This means that all
I/O pins will default to an input state, the level of which
depends on the other connected circuitry and whether
pull-high options have been selected. If the control reg-
isters, known as PAC, PBC, etc., are programmed to
setup some pins as outputs, these output pins will have
VD D
M
U
X
o n t r o l B i t
D a t a B u s
W r i t e o n t r o l R e g i s t e r
h i p R e s e t
R e a d o n t r o l R e g i s t e r
W r i t e D a t a R e g i s t e r
D a t a B i t
DQ
K SQ
DQ
K
S
Q
W a k e - u p f o r a n y I / O p o r t
R e a d D a t a R e g i s t e r
W a k e - u p o p t i o n f o r a n y I / O p o r t
P u l l - H i g h
O p t i o n W e a k
P u l l - u p
P u l l - L o w
P A 2 / T M R
P A O u t p u t
o n f i g u r a t i o n
I / O P o r t
Input/Output Ports
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