HP Vectra VE5 2 Product manual

Technical Reference
Manual
Hardware and BIOS
HP Vectra VE 5/xx Series 2 PC

NOTICE
Information contained in this document is subject to change without notice.
Hewlett-Packard makes no warranty of any kind with regard to this material, including, but not
limited to, the implied warranties of merchantability and fitness for a particular purpose.
Hewlett-Packard shall not be liable for errors contained herein or for incidental or consequential
damages in connection with the furnishing, performance, or use of this material.
Hewlett-Packard shall not be liable for errors contained herein or for incidental or consequential
damages in connection with the furnishing, performance, or use of this material.
Hewlett-Packard assumes no responsibility for the use or reliability of its software on equipment
that is not furnished by Hewlett-Packard.
This document contains proprietary information which is protected by copyright. All rights are
reserved. No part of this document may be photocopied, reproduced, or translated into another
language without the prior written consent of Hewlett-Packard Company.
Centronics® is a U.S. registered trademark of Centronics Data Computer Corporation.
Microsoft®, Windows and MS-DOS® are registered trademarks of Microsoft Corporation.
OS/2™ is a trademark of International Business Machines Corporation.
PENTIUM™ is a trademark of Intel Corporation.

Table of Contents
NOTICE......................................................................................................................................................2
PREFACE...................................................................................................................................................5
ORDERING INFORMATION FOR THE PHOENIX BIOS MANUAL..................................................5
CONVENTIONS.........................................................................................................................................5
BIBLIOGRAPHY.......................................................................................................................................6
1 SYSTEM OVERVIEW.............................................................................................. 7
SYSTEM OVERVIEW...............................................................................................................................7
HP VECTRA VE 5/XX SERIES – VE 5/XX SERIES 2 COMPARISON ..................................................7
VE 5/XX SERIES 2 PC BLOCK DIAGRAM............................................................................................8
PRINCIPAL COMPONENTS AND FEATURES .....................................................................................8
FLASH ROM............................................................................................................................................9
VE 5/XX SERIES 2 SYSTEM BOARD....................................................................................................9
VE 5/XX MT SERIES 4 DESKTOP BACKPLANE................................................................................10
PROCESSOR.......................................................................................................................................... 10
SUPERSCALAR ARCHITECTURE....................................................................................................... 10
FLOATING POINT UNIT (FPU)............................................................................................................10
DYNAMIC BRANCH PREDICTION.....................................................................................................11
INSTRUCTION AND DATA CACHE....................................................................................................11
DATA INTEGRITY ............................................................................................................................... 11
PCI CHIP SET........................................................................................................................................12
PCI, CACHE AND MEMORY CONTROLLER (82437FX)....................................................................13
DATA PATH UNIT (82438FX).............................................................................................................. 14
THE PCI/ISA BRIDGE AND IDE CONTROLLER (82371FB)...............................................................14
THE 82438FX AND 82371FB FEATURE SUMMARY..........................................................................15
SUPER I/O CHIP....................................................................................................................................16
NS PC87332VF FEATURE SUMMARY................................................................................................16
FLEXIBLE DRIVE CONTROLLER (FDC)............................................................................................16
SERIAL/PARALLEL PORTS................................................................................................................. 17
GRAPHICS/INTEGRATED VIDEO....................................................................................................... 17
IDE TO PCI CONTROLLER..................................................................................................................18
FLASH ROM.......................................................................................................................................... 18
SECURITY FEATURES.........................................................................................................................18
PHYSICAL CHARACTERISTICS ......................................................................................................... 18
ELECTRICAL SPECIFICATIONS.........................................................................................................19
POWER AVAILABILITY (CONTINUOUS OPERATION):...................................................................19
ENVIRONMENTAL SPECIFICATIONS ............................................................................................... 20

2 SUMMARY OF THE HP/PHOENIX BIOS..............................................................21
HP/PHOENIX BIOS DESCRIPTION .....................................................................................................21
OVERVIEW OF ADDRESS SPACE.......................................................................................................21
I/O ADDRESSES USED BY THE SYSTEM* ........................................................................................21
BIOS I/O PORT MAP.............................................................................................................................22
ADDRESSING SYSTEM BOARD COMPONENTS...............................................................................23
3 DESKTOP MANAGEMENT INTERFACE ............................................................. 25
DMI INFORMATION STRUCTURE......................................................................................................25
ACCESSING BIOS DMI INFORMATION.............................................................................................26
THE DMI HEADER ...............................................................................................................................27
VERIFYING THE DMI INFORMATION STRUCTURE........................................................................ 27
DMI SUB-STRUCTURE TABLES..........................................................................................................28
4 POWER-ON SELF-TESTS AND ERROR MESSAGES ........................................ 31
POWER-ON SELF TEST (POST)...........................................................................................................31
SHADOW RAM ..................................................................................................................................... 31
ERROR MESSAGES..............................................................................................................................33
BEEP CODES.........................................................................................................................................35
5 THE ULTRA VGA VIDEO CONTROLLERS.......................................................... 36
THE MATROX MGA MILLENNIUM VIDEO ADAPTER BOARD....................................................36
VIDEO MEMORY ................................................................................................................................. 36
AVAILABLE VIDEO RESOLUTIONS..................................................................................................36
VESA CONNECTOR.............................................................................................................................37
FURTHER INFORMATION...................................................................................................................37
THE INTEGRATED ULTRA VGA VIDEO CONTROLLER...............................................................37
VIDEO MEMORY ................................................................................................................................. 38
VIDEO MODES.....................................................................................................................................38
AVAILABLE BIOS VIDEO RESOLUTIONS.........................................................................................41
VESA CONNECTOR.............................................................................................................................42
DB15 CONNECTOR PINOUT ...............................................................................................................42
VIDEO CONTROLLER SUMMARY.....................................................................................................42

PREFACE
This manual is a technical reference and BIOS document for engineers and technicians
providing system level support. It is assumed that the reader possesses a detailed
understanding of AT-compatible microprocessor functions and digital addressing techniques.
Technical information that is readily available from other sources, such as manufacturer’s
proprietary publications, has not been reproduced.
This manual contains summary information only. For additional reference material, refer to the
bibliography.
ORDERING INFORMATION FOR THE PHOENIX BIOS MANUAL
System BIOS for IBM PCs, Compatibles, and EISA Computers (ISBN 0-201-57760-7) by
Phoenix Technologies is available in many bookstores. It can also be ordered directly from the
publisher as follows:
In the U.S.A.
Call Addison-Wesley in Massachusetts at [phone], and be prepared to give a credit
card number and expiry date.
In Europe
Send your request to Addison-Wesley at the address given below, and be prepared to give a
credit card number and expiry date.
Addison-Wesley
Concertgebouwplein 25
1071 LM Amsterdam, The Netherlands
Tel: [phone]
Fax: [phone]
CONVENTIONS
The following conventions are used throughout this manual to identify specific elements:
• Hexadecimal numbers are identified by a lower case h.
For example, 0FFFFFFFh or 32F5h
• Binary numbers and bit patterns are identified by a lower case b.
For example, 1101b or 10011011b

BIBLIOGRAPHY
• System BIOS for IBM PCs, Compatibles, and EISA Computers (ISBN 0-201-57760-7) by
Phoenix Technologies. Addison-Wesley (publisher).
The following Hewlett-Packard publications may also assist the reader of this manual.
• HP Vectra VE 5/xx series 2 PC
User’s Guide (D4000-90001, as supplied with PC).
• HP Vectra VE 5/xx series 2 PC
Familiarization Guide (D4000-90901)
•
HP Vectra PC Service Handbook (Volume 1) - 9th edition
The following Intel® publication provides more detailed information:
•
Pentium Processor (241595-002)

1 SYSTEM OVERVIEW
This chapter provides a description of the HP Vectra VE 5/xx series 2 PC with detailed system
specifications.
SYSTEM OVERVIEW
The HP Vectra VE 5/xx series 2 PC is a Pentium processor, ISA/PCI-based PC and features
the Intel Triton chip set.
HP VECTRA VE 5/XX SERIES – VE 5/XX SERIES 2 COMPARISON
Vectra VE 5/xx series Vectra VE 5/xx series 2
Processor Pentium 75 (VE 5/75)
Pentium 90 (VE 5/90) Pentium 75
Pentium 100
Level-two cache memory Optional 256 KB cache Optional 256 KB cache
Main memory 8 MB or 16 MB standard
128 MB maximum 8 MB or 16 MB standard
128 MB maximum
Video controller Cirrus Logic 5434
32-bit Ultra VGA integrated on PCI
bus
Cirrus Logic 5434
64-bit Ultra VGA integrated on PCI
bus
Video memory 1 MB standard 1 MB standard (32-bit)
upgradable to 2 MB (64-bit)
Enhanced IDE hard disk controller CMD PCI0640B
Integrated on PCI bus
dedicated for hard disk drives
Integrated in chip set (part of
82371FB multipurpose chip)
Integrated on PCI bus
Primary channel dedicated for hard
disk drives
Secondary channel recommended for
CD-ROM drives
Secondary IDE controller None No secondary IDE controller
(Two channels on enhanced IDE
controller - see above)
Flexible disk controller Integrated in NS 87332 Super I/O
chip on ISA bus Integrated in NS306 Super I/O chip
on ISA bus
Serial / parallel port controller Integrated in NS 87332 Super I/O
chip on ISA bus Integrated in NS306 Super I/O chip
on ISA bus

VE 5/XX SERIES 2 PC BLOCK DIAGRAM
Pentium
Processor Optional
256 KB
Level-Two
Cache
Intel Triton
82437/8FX
Chipset
Memory
(8 MB -
128 MB)
PCI
Accessory
Board Slots
PCI Bus
Intel
82371FB
PCI/ISA
Bridge
IDE Controller Channel 1
IDE Controller Channel 2
CL-5436
Video
Controller
ISA Bus
SMC932
Super I/O
Controller
I/O
Decode
Logic
BIOS
Flash
ROM
ISA
Accessory
Board Slots
Keyboard
Mouse
Serial 2 Serial 1
Parallel
FDD
Flash
Support
Host Bus
PRINCIPAL COMPONENTS AND FEATURES
The main features of the system board are:
• supports Pentium processors of several different clock speeds (75, 90, 100, 120, 133
MHz, 150 and 166 MHz) with accompanying voltage regulator module (VRM)
• an integrated 64-bit Ultra VGA controller on the PCI bus
• an Enhanced IDE controller with two channels on the PCI bus
• a primary IDE channel for two IDE hard disk drives
• a secondary IDE channel for an IDE CD-ROM drive
• a combined controller on the ISA bus for
• 2 flexible disk drives and/or tape drives
• 2 serial ports
• 1 parallel port
• sockets for DRAM main memory: the Vectra VE 5/xx series 2 PCs provide six sockets for
main memory, allowing installation of up to 128 MB

• a system ROM (using flash ROM technology) that can be easily updated with the latest
firmware, using the
Phlash.exe program supplied with the firmware upgrade. The system
ROM contains:
• the BIOS (system BIOS, video BIOS and low option ROM)
• a power-on hardware test that allows you to view the results of the diagnostics as well
as a corrective action message (error message utility)
• menu-driven SETUP with context-sensitive help (in US English only)
• a keyboard/mouse controller and interface
• two-level password protection using administrator and user passwords.
FLASH ROM
The PC uses 128 KB of 200 ns, Flash ROM. The HP BIOS boot code contains SETUP, video
BIOS, error messages, and ISA and PCI initialization. During programming of the Flash ROM,
the power supply switch and the reset button are disabled to prevent accidental interruption.
VE 5/XX SERIES 2 SYSTEM BOARD
*This video upgrade applieso nly to themodels with integrated video controller.

VE 5/XX MT SERIES 4 DESKTOP BACKPLANE
PROCESSOR
The Pentium processor uses 64-bit architecture and is 100% software compatible with Intel’s
family of x86 processors. All application software written for Intel 386 and Intel 486 processors
can run on the Pentium without modification. The Pentium processor contains all the features
of the Intel 486 processor, with the following added features which enhance performance:
• Superscalar Architecture
• Floating Point Unit
• Dynamic Branch Prediction
• Instruction and Data cache
• Data Integrity
• Supports MultiProcessor Specification (MPS) 1.1
• PCI bus architecture
• Advanced Power Management capability for reducing power consumption
The processor is seated in a Zero Insertion Force (ZIF) socket.
SUPERSCALAR ARCHITECTURE
The Pentium processor’s superscalar architecture has two instructions pipelines and a floating-
point unit, each capable of independent operation. The two pipelines allow the Pentium to
execute two integer instructions in parallel, in a single clock cycle. Using these pipelines halves
the instruction execution time and almost doubles the performance of the processor, compared
with an Intel 486 microprocessor of the same frequency.
Frequently, the microprocessor can issue two instructions at once (one instruction to each
pipeline). This is called instruction pairing. Each instruction must be simple. One pipeline will
always receive the next sequential instruction of the one issued to the other pipeline.
FLOATING POINT UNIT (FPU)
The Floating Point Unit incorporates optimized algorithms and dedicated hardware for multiply,
divide, and add functions. This increases the processing speed of common operations by a
factor of three.

DYNAMIC BRANCH PREDICTION
The Pentium processor uses dynamic branch prediction. To dynamically predict instruction
branches, the processor uses two prefetch buffers. One buffer is used to prefetch code in a
linear way, and one to prefetch code depending on the contents of the Branch Target Buffer
(BTB). The BTB is a small cache which keeps a record of the last instruction and address used.
It uses this information to predict the way that the instruction will branch the next time it is used.
When it has made a correct prediction, the branch is executed without delay, thereby
enhancing performance.
INSTRUCTION AND DATA CACHE
The Pentium processor has separate code and data caches on-chip. Each cache is 8 KB in size
with a 32-bit line. The cache acts as temporary storage for data and instructions from the main
memory. As the system is likely to use the same data several times, it is faster to get it from
the on-chip cache than from the main memory.
Each cache has a dedicated Translation Lookaside Buffer (TLB). The TLB is a cache of the
most recently accessed memory pages. The data cache is configured to be Write-Back on a
line-by-line basis (a line is an area of memory of a fixed size).
The data cache tags (directory entries used to reference cached memory pages) are triple
ported to support two data transfers and an inquire cycle in the same clock cycle. The code
cache tags are also triple ported to support snooping (a way of tracking accesses to main
memory by other devices) and split line accesses.
Individual pages of memory can be configured as cacheable or non-cacheable by software or
hardware. They can also be enabled and disabled by hardware or software.
DATA INTEGRITY
The processor uses a number of techniques to maintain data integrity. It employs two methods
of error detection:
• Data Parity Checking
This is supported on a byte-by-byte basis, generating parity bits for data addresses sent
out of the microprocessor. These parity bits are not used by the external subsystems.
• Internally
The processor uses functional redundancy checking to provide maximum error detection
of the processor and its interface.

PCI CHIP SET
The chip set consists of four devices:
• The PCI, Cache, and Memory Controller (82437FX)
• Two Data Path Units (82438FX)
• The PCI/ISA bridge and IDE controller (82371FB)
The 82437FX and 82438FX2 devices provide the core cache and memory system architecture,
and the PCI interface.
Pentium
Processor
Host Bus
82438FX
Data Path Unit
82438FX
Data Path Unit
Main
Memory
Level-Two
Cache
PCI Bus ISA Bus
82371FB
PCI/ISA Bridge
PCI
Master
PCI
Slave
APIC
ISA Bus
Controller
IDE
Controller
BIOS
82437FX PCI, Cache and
Memory Controller
Cache
Controller
Write
Buffer
PCI
Master
Main
Memory
Controller
PCI
Slave

PCI, CACHE AND MEMORY CONTROLLER (82437FX)
The 82437FX device integrates cache and memory control functions and provides bus control
functions for the transfer of information between the microprocessor, cache, main memory and
the PCI bus. The cache controller supports the Pentium Cache Write-Back mode and 256 KB
of direct mapped, write-back level-two cache, using synchronous pipeline burst SRAMs.
82437FX Feature Summary
Function Features
Cache controller • Direct mapped organization
• Buffered write-back
• External cache tags
• 32-byte line size
• Uses synchronous pipeline burst SRAM or asynchronous SRAM
• Supports 3-1-1-1* burst reads
Write buffer • Buffers all processor writes to main memory
• Buffers memory writes to PCI for selected memory regions
• Supports 3-1-1-1* write access timing
DRAM controller • Uses dedicated DRAM memory address and data buses
• Page mode - one or two pages open simultaneously
• Supports pipelined accesses
• Full RAS/CAS programmability
• Flexible bank configurations (each bank programmable for DRAM
size, bank width and single or double-sided modules)
• Self configuring bank start addresses
• Shadow RAM support for the memory region 640 KB -
1 MB (in 16 KB segments)
• System management memory support
• RAS only refresh
• Fast memory access 7-2-2-2* with Extended Data Out (EDO) memory
PCI slave interface • Becomes processor (local) bus master to generate DRAM
requests on behalf of other PCI bus masters
• Supports PCI bus burst cycles
• Supports posted writes to DRAM for PCI burst writes
• Supports read-ahead from DRAM for PCI burst reads
PCI master interface • Provides for programmable PCI bus memory regions in memory
address map
• Supports PCI bus burst cycles for 64-bit and 32-bit misaligned Pentium
reads and writes
• Optional posting of PCI memory and I/O writes
• Optional buffering of PCI memory writes
• Optional read-ahead for processor to PCI accesses
PCI bus arbiter • Supports PCI bus arbitration for up to four masters
• Supports rotating priority scheme
*The Pentium's internal cache has a 32-byte line size, which is four times the width of the Pentium's
host data bus. Burst reads and writes by the Pentium involve a full cache line, and so require four
back-to-back cycles to complete. The first cycle in each burst of four always requires more time to
complete than the three subsequent cycles. This is because the first cycle includes the addressing
phase and precharge timing (for memory).

DATA PATH UNIT (82438FX)
The 82438FX component contains a 64-bit data path between the host bus and main memory.
A 4×64-bit deep buffer provides 3-1-1-1 writes to main memory.
This buffer is used for:
• writes from processor to main memory
• level-two cache write back cycles
• transfers from PCI to main memory.
THE PCI/ISA BRIDGE AND IDE CONTROLLER (82371FB)
The 82371FB device serves as a bridge between the PCI bus and the ISA expansion bus, and
incorporates a two-channel PCI IDE controller. It incorporates the logic for a PCI interface, a
DMA interface, a DMA controller that supports fast DMA transfers, data buffers to isolate the
PCI and ISA buses, Timer/Counter logic, and NMI control logic.
The 82371FB PCI/ISA bridge also provides decode for the following peripheral devices:
• Flash BIOS
• Real Time Clock/CMOS Memory
• Keyboard/Mouse Controller
• Flexible Disk Controller
• Two Serial Ports
• One Parallel Port
• PCI Accessory Board Slots.
IDE to PCI Controller
This IDE to PCI controller implementation supports the full Enhanced IDE feature set. The
BIOS uses the auto-detected drive geometry information to select the fastest configuration
supported by each installed IDE drive.
• Supports data transfer rate of up to 22 MB/s.
• 32-bit Windows and DOS I/O transfers (many IDE controllers use Windows integral IDE
driver which only supports 16-bit I/O transfers).

THE 82438FX AND 82371FB FEATURE SUMMARY
Function Features
Data buffer
(for 82438FX and 82371FB
together)
• Provides a high performance 64-bit data path between the
processor (local) bus and main memory
• Provides a 32-bit data path to the PCI bus
• Provides a 4-deep x 64-bits wide write buffer for all processor
writes to main memory
• Provides a one-level posted write buffer for all processor writes
to PCI bus memory
PCI master / slave interface
(for 82371FB only) • Fully compatible with PCI specification • Supports PCI-to-ISA / ISA-to-PCI bus master cycle translations
• Supports programmable memory regions to provide fast positive
decode for PCI master accesses
• Implements subtractive decoding for unclaimed PCI cycles
• Supports PCI-to-ISA posted memory writes
• Translates DMA transfers for PCI slaves
• Supports PCI address/data parity generation and checking
ISA bus controller
(for 82371FB only) • Fully compatible with ISA bus standard • Supports asynchronous ISA bus operation up to 16 MHz
• Integrates:
• two 82C37A DMA controllers
• two 82C59A interrupt controllers
• 82C54 timer
• hidden ISA refresh controller
• support for BIOS
• port A, B and NMI logic
Fast IDE controller
(for 82371FB only) • Supports PIO and Bus Master IDE • Supports up to Mode 4 timings
• Up to 22 MB/s transfer rate
• 8×32-bit buffer for Bus Master IDE PCI burst transfers

SUPER I/O CHIP
The basic input/output control functions are provided by the Super I/O chip, the NS306. This
chip is 100% compatible with ISA architecture and provides:
• an integrated flexible drive controller that supports 3.5-inch and 5.25-inch flexible disk
drives, and tape drives
• a multi-mode parallel port
• two serial ports
• keyboard controller
• RTC
• 256 bytes of CMOS memory.
NS PC87332VF FEATURE SUMMARY
Function Features
Flexible disk controller • Software compatible with the DP8473, the 765A, and the N82077
• 16-byte FIFO (default disabled)
• Burst and non-burst modes
• Perpendicular recording drive support
• New high-performance internal digital data separator (no external filter
components required)
• Low-power CMOS with enhanced power-down mode
• Automatic media-sense support
UARTs • Software compatible with the PC16550A and PC16450
• MIDI compatible
Bidirectional parallel port • Enhanced Parallel Port (EPP) compatible
• Extended Capabilities Port (ECP) compatible
• Bidirectional under either software or hardware control
• Ability to multiplex FDC signals on parallel port pins for external FDD
• Includes protection circuit against damage caused when printer is
switched on, or operated at higher voltages
Address decoder Provides selection of all primary and secondary ISA addresses including
COM 1 - 4 and LPT 1 - 2
Enhanced power
management • Special configuration registers for power down
• Enhanced programmable power down FDC command
• Auto power down and wake up modes
• 3 special pins for power management
• Typical current consumption during power down is less than 10µA
• Reduced pin leakage current
FLEXIBLE DRIVE CONTROLLER (FDC)
The FDC is software and register compatible with the 82077AA, and 100% IBM compatible. It
has an A and B drive-swapping capability and a non-burst DMA option.

SERIAL/PARALLEL PORTS
The Super I/O chip supports two serial ports and one bidirectional parallel port. The serial ports
are high speed UARTs with 16 Byte FIFOs, and can be programmed as COM1, COM2, COM3,
COM4, or disabled.
The parallel port can operate in four modes:
• Standard mode (PC/XT, PC/AT, and PS/2 compatible)
• Bidirectional mode (PC/XT, PC/AT, and PS/2 compatible)
• Enhanced mode (Enhanced Parallel Port or EPP compatible)
• High speed mode (MS/HP Extended Capabilities Port or ECP compatible).
It can be programmed as LPT1 (378h, IRQ7), LPT2 (278h, IRQ5), or disabled.
GRAPHICS/INTEGRATED VIDEO
The integrated video subsystem is composed of a PCI bus video controller and a DRAM array.
The Vectra VE 5/xx series 2 PC uses the Cirrus :Logic 5436 video controller that supports
video resolutions of up to 1280 x 1024.
Video Controller
The S3 Trio 765 64V+ and S3 Trio 764 video controllers offer full compatibility with VGA. In
addition, the features are enhanced beyond Super VGA by hardware which accelerates
graphical user interface operation in environments such as Microsoft Windows or OS/2.
NOTE The S3 Trio 765 64V+ and S3 Trio 764 video drivers
are not compatible.
D3xxxA models use the S3 Trio 765 64V+.
D3xxxB models use the S3 Trio 764.
The enhanced features include:
• direct connectivity to PCI bus
• true acceleration for 8, 16 and 32-bit pixel depths
• 60 MHz clock for video memory
• fully programmable Pixel Clock Generator up to 135 MHz
• supports 2 MB DRAM
• fast linear addressing with full software relocation.
Video DRAM
The Vectra VE 5/xx series 2 PC is supplied with 1 MB of video DRAM as standard. An
additional 1 MB video DRAM accessory can be installed, to give a total of 2 MB video DRAM.
The upgrade consists of two 512 KB video memory chips.
Video Resolutions Supported
A table detailing all the video resolutions supported can be found in chapter 5 of this manual.

IDE TO PCI CONTROLLER
This IDE to PCI controller implementation supports the full Enhanced IDE feature set. The
BIOS uses the auto-detected drive geometry information to select the fastest configuration
supported by each installed IDE drive.
• Supports data transfer rate of up to 12 MB/s.
• 32-bit Windows and DOS I/O transfers (many IDE controllers use Windows integral IDE
driver which only supports 16-bit I/O transfers).
FLASH ROM
The PC uses 128 KB of 200ns, Flash ROM. The HP BIOS boot code contains SETUP, video
BIOS, error messages, and ISA and PCI initialization. During programming of the Flash ROM,
the power supply switch and the reset button are disabled to prevent accidental interruption.
SECURITY FEATURES
The PC has many security features to protect stored data, to protect the SETUP configuration,
and to prevent unauthorized operation of software applications:
• user password
• administrator password (system configuration protection)
• power-on prompt, with user of administrator password
• power-on keyboard and mouse lock, with user password
• space bar power-on protection (feature can be disabled in SETUP)
• communications port protection (ports can be disabled in SETUP)
• flexible disk drive protection (disks can be read and/or write protected in SETUP)
• boot protection (boot on flexible disk, CD-ROM, and hard disk can be enabled or disabled
in SETUP)
• cover lock and, in the desktop, security bracket.
PHYSICAL CHARACTERISTICS
Desktop Unit
Weight: 0 lbs (9 kg)
Dimensions: 15.3 inches (D) by 16.5 inches (W) by 4.9 inches (H)
(39 cm by 42 cm by 12.5 cm)
Footprint: 1.8 sq ft (0.17 m2)
Mini-Tower Unit
Weight: 28.7 lbs (13 kg)
Dimensions: 17.3 inches (D) by 7.6 inches (W) by 17.2 inches (H)
(44 cm by 19.2 cm by 43.8 cm)
Footprint: 0.9 sq ft (0.084 m2)
Keyboard
Flat: 18 inches (W) by 7 inches (D) by 1.3 inches (H)
(464mm by 178mm by 33mm)
Standing: 18 inches (W) by 7 inches (D) by 2 inches (H)
(464mm by 178mm by 51mm)

ELECTRICAL SPECIFICATIONS
Desktop Models
Input voltage:
The Desktop VE 5/xx series 2 PCs are equipped with a 100 W (rated) power supply.
This power supply requires an input voltage in the following range:
• 100-127 Vac and 200-240 Vac auto-ranging at a frequency of 50 and 60 Hz.
POWER AVAILABILITY (CONTINUOUS OPERATION):
• 100 W continuous.
• For each ISA accessory board:
4.5 A at 5 V
1.5 A at 12 V
0.3 A at -12 V
0.1 A at -5 V.
• For PCI accessory boards:
4.5 A at 5 V
0.5 A at 12 V
0.1 A at -12 V
Mini-Tower Models
Input voltage:
The Mini-Tower VE 5/xx series 2 PCs are equipped with a 160 W continuous (rated) power
supply.
This power supply requires an input voltage in the following range:
• 100-127 Vac and 176-264 Vac at a frequency of 47 Hz to 63 Hz, with manual switching
between 115 and 230 V.
Heat Dissipation:
• Maximum thermal dissipation: 91 kcal per hour (360 BTUs per hour).
Power Availability (Continuous Operation):
• 160 W continuous, 200 W peak.
• For each ISA accessory board:
1.4 A at 5 V
0.13 A at 12 V
0.1 A at -12 V
0.03 A at -5 V.
• For PCI accessory boards:
3 x 5V PCI slots.

ENVIRONMENTAL SPECIFICATIONS
Desktop Unit (with hard disk)
Operating Temperature + 40° to 104° F (+5°C to +40°C)
Recommended Operating Temperature +59°F to +158°F (+15°C to +30°C)
Storage Temperature -40°F to +158°F (-40°C to +70°C)
Over Temperature Shutdown +122°F (+50°C)
Operating Humidity 15% to 80% (relative)
Storage Humidity 8% to 80% (relative)
Operating Altitude 10000 ft (3100m) max
Storage Altitude 15000ft (4600m) max
Mini-Tower Unit (with hard disk)
Operating Temperature + 41° to 104° F (+5°C to +40°C)
Recommended Operating Temperature +59°F to +158°F (+15°C to +30°C)
Storage Temperature -40°F to +158°F (-40°C to +70°C)
Over Temperature Shutdown +122°F (+50°C)
Operating Humidity 15% to 80% (relative)
Storage Humidity 8% to 80% (relative)
Operating Altitude 10000 ft (3100m) max
Storage Altitude 15000ft (4600m) max
NOTE Operating temperature and humidity ranges may
vary depending upon the mass storage devices
installed. High humidity levels can cause improper
operation of disk drives. Low humidity levels can
aggravate static electricity problems and cause
excessive wear of the disk surface.
The 6 MB video upgrade module is available only from Matrox Electronic Systems Limited.