11
2 System Board
Devices on the Processor-Local Bus
Chip-Set
The Intel 82450KX chip-set comprises eight chips. Six of them are
concerned with controlling memory accesses, and are located below the
memory module sockets. These are the four datapath units, the memory
controller chip, and the Mem/PL bridge chip. They are described in the sub-
section of this chapter entitled “Main Memory”.
The remaining two chips are the PL/PCI bridge chip (OPB, Intel S82454KX),
and the PCI/ISA bridge chip (system I/O chip, SIO-A, Intel S82379AB).
The Processor-Local bus is 64 bits wide, and is clocked at 66 MHz. Although
carrying 64-bits of data, it is in fact composed of 141 signals. These are
implemented using GTL+ (Intel’s adaptation of Gunning Transceiver Logic).
To reduce voltage over- and under-shoots, the signals are clamped to a 0 to
1.5 voltage range, and are filtered to prevent the logic edges from becoming
too steep (that is, there is a minimum constraint on the rise and fall times, as
well as the usual maximum constraint).
Cache Memory
There are two integrated circuits sealed within a single Pentium Pro
package. One of these contains the Level-2 (L2) cache memory chip; the
other contains the processor chip, which itself includes two banks of Level-1
(L1) cache memory.
The amount of cache memory is set by Intel at the time of manufacture, so
cannot be changed. Each L1 cache memory has a capacity of 8 KB, and is
set-associative (4-way for the I-cache, and dual-ported 2-way set associative
for the D-cache). The L2 cache memory has a capacity 256 KB or 512 KB,
depending on the part number of the processor, and is composed of four-
way set-associative static RAM.
Data is stored in lines of 32-bytes (256 bits). Thus two consecutive 128-bit
transfers with the main memory are involved for each transaction.
Optional Second Microprocessor
The two processors must be operating at the same bus speed and the same
processor speed, with the switch settings set accordingly for the slower of
the two. In fact, only 200 MHz processors are presently supported by HP.
The two processors should have the same amount of level-two (L2) cache
memory. Although a mixed configuration would work, it would not give
optimum performance.